AS3911-BQFT [AMSCO]

NFC Initiator / HF Reader IC; NFC发起者/ HF阅读器IC
AS3911-BQFT
型号: AS3911-BQFT
厂家: AMS(艾迈斯)    AMS(艾迈斯)
描述:

NFC Initiator / HF Reader IC
NFC发起者/ HF阅读器IC

文件: 总149页 (文件大小:1107K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
AS3911  
NFC Initiator / HF Reader IC  
The AS3911 is a highly integrated NFC Initiator / HF Reader IC.  
It includes the analog front end (AFE) and a highly integrated  
data framing system for ISO 18092 (NFCIP-1) initiator, ISO 18092  
(NFCIP-1) active target, ISO 14443 A and B reader (including  
high bit rates) and FeliCa™ reader. Implementation of other  
standard and custom protocols is possible through using the  
AFE and implementing framing in the external microcontroller  
(Stream and Transparent modes).  
General Description  
Compared with concurrent NFC devices designed with the  
mobile phone in mind, the AS3911 is positioned perfectly for  
the infrastructure side of the NFC system, where users need  
optimal RF performance and flexibility combined with low  
power.  
With ams’ unique Automatic Antenna Tuning technology, the  
device is optimized for applications with directly driven  
antennas. The AS3911 is alone in the domain of HF Reader ICs  
in that it contains two differential low impedance (1Ω) antenna  
drivers.  
The AS3911 includes several features, which make it  
incomparable for low power applications. It contains a low  
power capacitive sensor, which can be used to detect the  
presence of a card without switching on the reader field.  
Additionally, the presence of a card can also be detected by  
performing a measurement of amplitude or phase of signal on  
antenna LC tank and comparing it to stored reference. It also  
contains a low power RC oscillator and wake-up timer, which  
can be used to wake the system after a defined time period and  
check for the presence of a tag using one or more techniques  
of low power detection of card presence (capacitive, phase or  
amplitude).  
The AS3911 is designed to operate from a wide power supply  
range from 2.4V to 5.5V; peripheral interface IO pins support  
power supply range from 1.65V to 5.5V.  
For further understanding in regards to the contents of the  
datasheet, please refer to the Reference Guide located at the end  
of the document.  
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 1  
G e n e r a l D e s c r i p t i o n  
Key Benefits & Features  
The benefits and features of AS3911, NFC Initiator / HF Reader  
IC are listed below:  
Figure 1:  
Added Value for AS3911  
Benefits  
Features  
ISO 18092 (NFCIP-1) Active P2P  
ISO14443 A, B and FeliCa (TM)  
NFC Active P2P support  
High data transfer with ASK VHBR and fast  
SPI  
Support of VHBR (3.4 Mbit/s PICC to PCD framing, 6.8 Mbit/s AFE  
and PCD to PICC framing)  
6μA consumption at sensing every 100ms  
Capacitive sensing - Wake-up  
Automatic Antenna Tuning system providing tuning of antenna  
LC tank  
Antenna tuning on the fly  
Stable modulation index at ASK modulation Automatic modulation index adjustment  
AM and PM (I/Q) demodulator channels with automatic  
selection  
No communication holes  
High output power for EMVCo readers  
High Rx sensitivity  
Up to 1 W in case of differential output  
User selectable and automatic gain control  
Transparent and Stream modes to implement other standard  
and custom protocols  
Allows implementation of custom framings  
Multi Antenna support  
Possibility of driving two antennas in single ended mode  
Oscillator input capable of operating with 13.56 MHz or 27.12  
MHz crystal with fast start-up  
Smaller Oscillator size  
Easy FIFO handling  
10 M bit SPI with 96 bytes FIFO  
Wide supply voltage range from 2.4 V to 5.5 V  
Fits Temperature requirements for various  
applications  
Wide temperature range: -40°C to 125°C  
QFN 5x5 LD32 package  
Small outline, good cooling through  
exposed pad  
AS3911 – 2  
ams Datasheet, Confidential: 2013-Oct [2-03]  
General Description  
Applications  
The AS3911 is suitable for a wide range of applications  
including:  
• EMV Payment  
• Access Control  
• NFC Infrastructure  
• Ticketing  
Block Diagram  
The functional blocks of this device for reference are  
shown below:  
Figure 2:  
AS3911 Block Diagram  
VDD_IO  
XTO  
XTI  
VDD  
XTAL  
Oscillator  
POR & Bias  
Regulators  
LOGIC  
1
RFO  
Transmitter  
FIFO  
RFO 2  
SPI  
Level  
Shifters  
Control  
Logic  
Phase &  
Amplitude  
Detector  
IRQ  
A/D Converter  
MCU_CLK  
SPI  
Interface  
RFI1  
RFI2  
Receiver  
TRIMx  
Framing  
External Field  
Detector  
RC  
Oscillator  
Wake-up  
Timer  
AS3911  
Capacitor  
Sensor  
CSI  
CSO  
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 3  
P i n A s s i g n m e n t  
The AS3911 pin assignments are described below.  
Pin Assignment  
Figure 3:  
Pin Diagram  
AS3911 Pin Assignment: This figure  
shows the pin assignment and location  
viewed from top.  
32 31 30 29 28 27 26 25  
1
2
3
4
5
6
7
8
VDD_IO  
CSO  
24  
23  
22  
21  
20  
19  
18  
17  
AGD  
RFI2  
RFI1  
VSP_D  
XTO  
VSS  
AS3911  
XTI  
VSN_D  
VSP_A  
VDD  
TRIM2_0  
TRIM1_0  
TRIM2_1  
TRIM1_1  
9
10 11 12 13 14 15 16  
Figure 4:  
Pin Description  
Pin Number  
Pin Name  
Pin Type  
Description  
32-pin QFN  
V
1
2
3
4
Supply pad  
Positive supply for peripheral communication  
Capacitor sensor output  
DD_IO  
CSO  
VSP_D  
XTO  
Analog  
output  
Digital supply regulator output  
Xtal oscillator output  
Analog input  
/ Digital input  
5
6
7
8
XTI  
Xtal oscillator input  
VSN_D  
VSP_A  
Supply pad  
Digital ground  
Analog  
output  
Analog supply regulator output  
External positive supply  
V
Supply pad  
DD  
AS3911 – 4  
ams Datasheet, Confidential: 2013-Oct [2-03]  
Pin Assignment  
Pin Number  
Pin Name  
Pin Type  
Description  
32-pin QFN  
9
VSP_RF  
RFO1  
Supply regulator output for antenna drivers  
Antenna driver output  
Analog  
output  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
RFO2  
VSN_RF  
TRIM1_3  
TRIM2_3  
TRIM1_2  
TRIM2_2  
TRIM1_1  
TRIM2_1  
TRIM1_0  
TRIM2_0  
VSS  
Supply pad  
Ground of antenna drivers  
Analog input Input to trim antenna resonant circuit  
Supply pad  
Ground, die substrate potential  
RFI1  
RFI2  
Analog input Receiver input  
AGD  
Analog I/O  
Analog reference voltage  
CSI  
Analog input Capacitor sensor input  
VSN_A  
IRQ  
Supply pad  
Analog ground  
Interrupt request output  
Microcontroller clock output  
Digital output  
MCU_CLK  
Digitaloutput  
/ tristate  
29  
MISO  
Serial Peripheral Interface data output  
30  
31  
32  
#
MOSI  
SCLK  
/SS  
Serial Peripheral Interface data input  
Digital input  
Exposed Pad  
Serial Peripheral Interface clock  
Serial Peripheral Interface enable (active low)  
Ground, die substract potential, connect to VSS on PCB  
VSS  
Note: Pins in bold have different functionality in comparison to the AS3910.  
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 5  
A b s o l u t e M a x i m u m R a t i n g s  
Stresses beyond those listed under “Absolute Maximum  
Absolute Maximum Ratings  
Ratings” may cause permanent damage to the device. These are  
stress ratings only. Functional operation of the device at these  
or any other conditions beyond those indicated under  
“Operating Conditions” is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect  
device reliability.  
Figure 5:  
Absolute Maximum Ratings  
Symbol  
Parameter  
Min  
Max  
Unit  
Comments  
Electrical Parameters  
V
DC supply voltage  
-0.5  
-0.5  
6.0  
6.0  
V
V
DD  
DC_IO supply  
voltage  
V
DD_IO  
Input pin voltage  
TRIM pins  
V
-0.5  
-0.5  
30.0  
6.5  
V
V
INTRIM  
Input pin voltage for  
peripheral  
V
IN  
communication pins  
Input pin voltage for  
analog pins  
V
-0.5  
-100  
0
6.0  
100  
250  
V
INA  
Input current  
(latch-up immunity)  
I
mA  
mA  
Norm: JEDEC 78  
scr  
Drive capability of  
output driver  
I
outmax  
Electrostatic Discharge  
kV  
Continuous Power Dissipation  
Electrostatic  
discharge  
Norm: MIL 883 E method 3015 (Human  
Body Model)  
ESD  
2
Total power  
dissipation (all  
supplies and  
outputs)  
P
300  
mW  
t
Temperature Ranges and Storage Conditions  
Storage temperature -55 125 °C  
T
strg  
AS3911 – 6  
ams Datasheet, Confidential: 2013-Oct [2-03]  
Absolute M aximum R atings  
Symbol  
Parameter  
Min  
Max  
Unit  
Comments  
Norm: IPC/JEDEC J-STD-020. The reflow  
peak soldering temperature (body  
temperature) is specified according  
IPC/JEDEC J-STD-020 “Moisture/Reflow  
Sensitivity Classification for  
Package body  
temperature  
T
260  
°C  
body  
Non-hermetic Solid State Surface Mount  
Devices.The lead finish for Pb-free  
leaded packages is matte tin (100% Sn).  
Humidity  
non-condensing  
5
85  
%
Moisture Sensitive  
Level  
Represents a max. floor life time of 168  
MSL  
3
h
Thermal Resistance  
36.4 C/W  
θ
Theta ja  
@ 85°C room temperature  
ja  
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 7  
E l e c t r i c a l C h a ra c t e r i s t i c s  
All limits are guaranteed. The parameters with min and max  
values are guaranteed with production tests or SQC (Statistical  
Quality Control) methods.  
Electrical Characteristics  
Operating Conditions  
All defined tolerances for external components in this  
specification need to be assured over the whole operation  
condition range and also over lifetime.  
Figure 6:  
Operating Conditions  
Symbol  
Parameter  
Min  
Max  
Unit  
Comments  
V
In case power supply is  
lower than 2.6V, PSSR  
cannot be improved using  
internal regulators  
(minimum regulated  
voltage is 2.4V)  
Positive supply voltage  
2.4  
5.5  
V
DD  
Peripheral  
communication supply  
voltage  
V
1.65  
5.5  
V
DD_IO  
VSS  
Negative supply voltage  
Junction temperature  
0
0
V
T
-40  
125  
°C  
JUN  
Minimum RFI input signal  
definition is meant for NFC  
receive mode. In HF reader  
mode and NFC transmit  
mode, the recommended  
V
V
RFI input amplitude  
150 milli  
3
RFI_A  
pp  
signal level is 2.5V  
pp  
DC/AC Characteristics for Digital Inputs and  
Outputs  
CMOS Inputs:  
Valid for input pins /SS, MOSI, and SCLK  
Figure 7:  
CMOS Inputs  
Symbol  
Parameter  
Min  
Max  
Unit  
V
V
0.7 * V  
DD_IO  
High level input voltage  
Low level input voltage  
Input leakage current  
IH  
V
0.3 * V  
DD_IO  
V
IL  
I
1
μA  
LEAK  
AS3911 – 8  
ams Datasheet, Confidential: 2013-Oct [2-03]  
Elec trical Charac teristics  
CMOS Outputs:  
Valid for output pins MISO, IRQ and MCU_CLK, io_18=0 (See “IO  
Configuration Register 2” on page 64).  
Figure 8:  
CMOS Outputs  
Symbol  
Parameter  
Conditions  
Min  
Type  
Max  
Unit  
0.9 *  
V
High level input voltage  
Low level input voltage  
V
OH  
V
DD_IO  
I
= 1mA  
= 1mA  
SOURCE  
I
SINK  
0.1 *  
V
V
OL  
V
DD_IO  
C
Capacitive load  
50  
pF  
L
R
Output Resistance  
250  
10  
500  
Ω
O
Pull-down can be  
enabled while MISO  
output is in tristate.  
The activation is  
controlled by  
Pull-down resistance pin  
MOSI  
R
kΩ  
PD  
register setting.  
Electrical Specification  
V
= 3.3V, Temperature 25°C unless noted otherwise.  
DD  
3.3V supply mode, regulated voltages set to 3.4V, 27.12 MHz  
Xtal connected to XTO and XTI.  
Figure 9:  
Electrical Specification  
Symbol  
Parameter  
Min  
Typ Max  
Unit  
Comments  
Register 00 set to 0F (no clock on  
h
h
MCU_CLK), register 01 set to 80 (3V  
supply mode), register 02 set to 00  
h h  
Supply current in  
Power-down  
mode  
h
h
I
0.7  
3.5  
2
7
μA  
PD  
register 03 set to 08 , other registers in  
h
h
default state.  
Register 00 set to 0F (no clock on  
h
h
MCU_CLK), register 01 set to 80 (3V  
h
h
Supply current in  
initial NFC Target  
mode  
supply mode), register 02 set to 00  
h
h
I
μA  
NFCT  
register 03 set to 80 (enable NFC  
h
h
Target mode), other registers in default  
state.  
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 9  
E l e c t r i c a l C h a ra c t e r i s t i c s  
Symbol  
Parameter  
Min  
Typ Max  
Unit  
Comments  
Register 00 set to 0F (no clock on  
h
h
MCU_CLK), register 01 set to 80 (3V  
h
h
supply mode), register 02 set to 04  
(enable Wake-up mode), register  
h
h
Supply current in  
Wake-up mode  
I
3.6  
6
μA  
WU  
03 set to 08 , register 31 set to 08  
h
h
h
h
(100ms timeout, IRQ at every timeout),  
other registers in default state.  
Register 00 set to 0F (no clock on  
h
h
MCU_CLK), register 01 set to 80 (3V  
h
h
Capacitive sensor  
supply current  
I
1.1  
5.4  
2
mA  
mA  
supply mode), register 02 set to 00 ,  
CS  
h
h
analog test mode 14, other registers in  
default state.  
Register 00 set to 0F (no clock on  
h
h
MCU_CLK), register 01 set to C0 (3V  
h
h
Supply current in  
Ready mode  
supply mode, disable VSP_D), register  
02 set to 80 , register 03 set to 08 ,  
I
7.5  
RD  
h
h
h
h
other registers in default state, short  
VSP_A and VSP_D.  
Register 00 set to 0F , register 01 set  
h
h
h
to C0 (3V supply mode, disable  
h
VSP_D), register 02 set to E8 (one  
h
h
Supply current all  
active  
channel Rx, enable Tx), register 03 set  
h
I
8.7  
12.5  
mA  
AL  
to 08, register 0B set to 00, register 27  
h
h
set to FF (all RFO segments disabled),  
other registers in default state, short  
VSP_A and VSP_D.  
Register 00 set to 0F , register 01 set  
h
h
h
to C0 (3V supply mode, disable  
h
VSP_D), register 02 set to E8 (one  
h
h
Supply current all  
active, low power  
receiver mode  
channel Rx, enable Tx), register 03 set  
h
I
6.8  
10  
mA  
LP  
to 08, register 0B set to 80 (low power  
h
mode), register 27 set to FF (all RFO  
h
segments disabled), other registers in  
default state, short VSP_A and VSP_D.  
AS3911 – 10  
ams Datasheet, Confidential: 2013-Oct [2-03]  
Elec trical Charac teristics  
Symbol  
Parameter  
Min  
Typ Max  
Unit  
Comments  
I
= 10 mA  
RFO  
The following measurement procedure  
which cancels resistance of  
measurement setup is used:  
• All driver segments are switched  
on, resistance is measured,  
• All driver segments except the  
MSB segment are switched on,  
resistance is measured,  
RFO1 and RFO2  
driver output  
resistance  
R
0.6  
1.8  
Ω
RFO  
• Difference between the two  
measurements is resistance of  
MSB segment,  
• Resistance of MSB segment  
divided by two is the value of  
R
.
RFO  
f
=848 kHz, AM channel with peak  
RFI input  
sensitivity  
SUB  
V
mV  
0.5  
10  
RFI  
rms  
detector input stage selected.  
RFI input  
resistance  
R
15  
kΩ  
RFI  
Power on Reset  
voltage  
V
1.2  
1.4  
1.65  
2.0  
V
POR  
Register 00 set to 0F (no clock on  
h
h
MCU_CLK), register 01 set to C0 (3V  
h
h
supply mode, disable VSP_D), register  
02 set to 80 , register 03 set to 08 ,  
V
AGD voltage  
1.5  
1.6  
V
AGD  
h
h
h
h
other registers in default state, short  
VSP_A and VSP_D.  
Manual regulator mode, regulated  
voltage set to 3.0V, measured on pin  
VSP_RF: register 00 set to 0F , register  
h
h
Regulated  
voltage  
V
2.85  
3.0  
0.7  
3.15  
V
REG  
01 set to 80 (3V supply mode),  
h
h
register 02 set to E8 (one channel Rx,  
h
h
enable Tx), register 2A set to D8 .  
h
h
13.56MHz or 27.12MHz crystal  
R = 50 Ω max, load capacitance  
S
Oscillatorstart-up  
time  
T
ms  
according to crystal specification, IRQ is  
issued once the oscillator frequency is  
stable.  
OSC  
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 11  
D e t a i l e d D e s c r i p t i o n  
The circuit diagram in Figure 2 shows the AS3911 building  
blocks.  
Detailed Description  
Figure 10:  
Minimum Configuration with Single Sided Antenna Driving Including EMC Filter  
+1.6V ~ +5.5V  
+2.4V ~ +5.5V  
VDD_IO  
VDD  
AGD  
/SS  
MISO  
MOSI  
SCLK  
IRQ  
VSS  
μC  
VSP_A  
VSN_A  
VSP_D  
MCU_CLK  
XTI  
VSN_D  
AS3911  
XTO  
VSP_RF  
VSN_RF  
TRIM1_x  
TRIM2_x  
RF01  
RF02  
Antenna  
Coil  
CSO  
CSI  
RFI1  
RFI2  
Figure 11:  
Minimum Configuration with Differential Antenna Driving Including EMC Filter  
+1.6V ~ +5.5V  
+2.4V ~ +5.5V  
VDD_IO  
VDD  
AGD  
/SS  
MISO  
MOSI  
SCLK  
IRQ  
VSS  
µC  
VSP_A  
VSN_A  
VSP_D  
MCU_CLK  
XTI  
VSN_D  
AS3911  
XTO  
VSP_RF  
VSN_RF  
TRIM1_x  
TRIM2_x  
RF01  
RF02  
CSO  
CSI  
RFI1  
RFI2  
Antenna  
Coil  
AS3911 – 12  
ams Datasheet, Confidential: 2013-Oct [2-03]  
Detailed Descript ion  
Transmitter  
The transmitter incorporates drivers which drive external  
antenna through pins RFO1 and RFO2. Single sided and  
differential driving is possible. The transmitter block  
additionally contains a sub-block which modulates transmitted  
signal (OOK or configurable AM modulation).  
The AS3911 transmitter is indented to directly drive antennas  
(without 50Ω cable, usually antenna is on the same PCB). Oper-  
ation with 50Ω cable is also possible, but in that case some of  
the advanced features are not possible.  
Receiver  
The receiver detects transponder modulation superimposed on  
the 13.56MHz carrier signal. The receiver contains two receive  
chains (one for AM and another for PM demodulation) which  
are composed of a peak detector followed by two gain and  
filtering stages and a final digitizer stage. The filter  
characteristics are adjusted to optimize performance over  
different ISO modes and bit rates (sub-carrier frequencies from  
212 kHz to 6.8 MHz are supported). The receiver chain inputs  
are RFI1 and RFI2 pins; output of digitizer stage is demodulated  
sub-carrier signal. The receiver chain incorporates several  
features which enable reliable operation in challenging phase  
and noise conditions.  
Phase and Amplitude Detector  
The phase detector is observing the phase difference between  
the transmitter output signals (RFO1 and RFO2) and the input  
signals RFI1 and RFI2. Signals RFI1 and RFI2 are proportional to  
the signal on the antenna LC tank. RFI1 and RFI2 signals are also  
used to run the self-mixer which generates output proportional  
to their amplitude. The phase detector and self-mixer blocks  
are used for several purposes:  
• PM demodulation by observing RFI1 and RFI2 phase  
variation (LF signal is fed to the Receiver)  
• Average phase difference between RFOx pins and RFIx  
pins is used to check antenna tuning  
• Output of mixer is used to measure amplitude of signal  
present on pins RFI1 and RFI2  
A/D Converter  
The AS3911 contains a built in A/D Converter. Its input can be  
multiplexed from different sources and is used in several  
applications (measurement of RF amplitude and phase,  
calibration of modulation depth…). The result of A/D  
conversion is stored in a register which can be read through the  
SPI interface.  
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 13  
D e t a i l e d D e s c r i p t i o n  
Capacitive Sensor  
The Capacitive sensor is used to implement low power  
detection of transponder presence. Capacitive sensor performs  
measurement of capacitance between its two electrodes.  
Presence of an object (card, hand) changes the capacitance.  
During calibration the reference capacitance, which represents  
parasitic capacitance of environment is stored. In normal  
operation capacitance is periodically measured and compared  
to stored reference value. When the measured capacitance is  
larger than stored reference value (threshold value can be  
defined in a register) an interrupt is sent to external controller.  
External Field Detector  
The External Field Detector is a low power block which is used  
in NFC mode to detect presence of external RF field. It supports  
two different detection thresholds, Peer Detection Threshold  
and Collision Avoidance Threshold. Peer Detection Threshold is  
used in the NFCIP-1 target mode to detect presence of initiator  
field. It is also used in active communication initiator mode to  
detect activation of target field. Collision Avoidance Threshold  
is used to detect a presence of RF field during NFCIP-1 RF  
Collision Avoidance procedure.  
Quartz Crystal Oscillator  
The quartz crystal oscillator can operate with 13.56 MHz and  
27.12 MHz crystals. At start-up the transconductance of the  
oscillator is increased to achieve fast start-up. Since the start-up  
time varies depending on crystal type, temperature and other  
parameters, the oscillator amplitude is observed and an  
interrupt is sent when stable operation is reached to inform the  
controller that the clock signal is stable and reader field can be  
switched on. The use of 27.12 MHz crystal is mandatory in case  
VHBR framing is used.  
It also provides a clock signal to the external microcontroller  
(MCU_CLK) according to setting in the control register.  
Power Supply Regulators  
Integrated power supply regulators ensure high power supply  
rejection of a complete reader system. In case PSRR of the reader  
system has to be improved, the command Adjust Regulators is  
sent. As result of this command, the power supply level of V  
DD  
is measured in maximum load conditions and the regulated  
voltage reference is set 250 mV below this measured level to  
assure a stable regulated supply. The resulting regulated  
voltage is stored in a register. It is also possible to define  
regulated voltage by writing a configuration register. In order  
to decouple any noise sources from different parts of IC there  
are three regulators integrated with separated external  
blocking capacitors (regulated voltage of all is the same in 3.3V  
supply mode). One regulator is for the analog blocks, one for  
AS3911 – 14  
ams Datasheet, Confidential: 2013-Oct [2-03]  
Detailed Descript ion  
digital blocks, there is also a separate one for the antenna  
drivers. In case of low cost applications some (or all) regulators  
may not be used to save on external components.  
This block additionally generates a reference voltage for the  
analog processing (AGD - analog ground). This voltage also has  
an associated external buffer capacitor.  
POR and Bias  
This block contains the bias current and voltage generator  
which provides bias currents and reference voltages to all other  
blocks. It also incorporates a Power on Reset (POR) circuit which  
provides a reset at power-up and at low supply levels.  
RC Oscillator and Wake-up Timer  
The AS3911 includes several possibilities of low power  
detection of a card presence (capacitive sensor, phase  
measurement, amplitude measurement). RC oscillator and  
register configurable Wake-up timer are used to schedule  
periodic detection. When presence of a card is detected an  
interrupt is sent to controller.  
ISO14443 and NFCIP-1 Framing  
This block performs framing for receive and transmit according  
to the selected ISO mode and bit rate settings.  
In reception it takes demodulated sub-carrier signal from  
Receiver. It recognizes the SOF, EOF and data bits, performs  
parity and CRC check, organizes the received data in bytes and  
places them in the FIFO.  
During transmit, it operates inversely, it takes bytes from FIFO,  
generates parity and CRC bits, adds SOF and EOF and performs  
final encoding before passing modulation signal to transmitter.  
In Transparent mode, the framing and FIFO are bypassed, the  
digitized sub-carrier signal, which is Receiver output, is directly  
sent to MISO pin, signal applied to MOSI pin is directly used to  
modulate the transmitter.  
FIFO  
The AS3911 contains a 96 byte FIFO. Depending on the mode,  
it contains either data which has been received or data which  
is to be transmitted.  
Control Logic  
The control logic contains I/O registers which define operation  
of device.  
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 15  
A p p l i c a t i o n I n fo r m a t i o n  
SPI Interface  
A 4-wire Serial Peripheral Interface (SPI) is used for  
communication between external microcontroller and the  
AS3911.  
Application Information  
Operating Modes  
The AS3911 operating mode is defined by the contents of the  
Operation Control Register.  
At power-up all bits of the Operation Control Register are set to  
0, the AS3911 is in Power-down mode. In this mode AFE static  
power consumption is minimized, only the POR and part of the  
bias are active, the regulators are transparent and are not  
operating. The SPI is still functional in this mode so all settings  
of ISO mode definition and configuration registers can be done.  
Control bit en (bit 7 of the Operation Control Register) is  
controlling the quartz crystal oscillator and regulators. When  
this bit is set, the device enters in Ready mode. In this mode  
the quartz crystal oscillator and regulators are enabled. An  
interrupt is sent to inform the microcontroller when the  
oscillator frequency is stable.  
Enable of Receiver and Transmitter are separated so it is  
possible to operate one without switching on the other (control  
bits rx_en and tx_en). In some cases this may be useful, in case  
the reader field has to be maintained and there is no  
transponder response expected receiver can be switched-off to  
save current. Another example is NFCIP-1 active  
communication receive mode in which RF field is generated by  
the initiator and only Receiver operates.  
Asserting the Operation Control Register bit wu while the other  
bits are set to 0 puts the AS3911 into the Wake-up mode which  
is used to perform low power detection of card presence. In this  
mode the low power RC oscillator and register configurable  
Wake-up timer are used to schedule periodic measurement(s).  
When a difference to the predefined reference is detected an  
interrupt is sent to wake-up the micro. Capacitive sensor, phase  
measurement and amplitude measurement are available.  
Transmitter  
The Transmitter contains two identical push-pull driver blocks  
connected to the pins RFO1 and RFO2. These drivers are  
differentially driving external antenna LC tank. It is also possible  
to operate only one of the two drivers by setting the IO  
Configuration Register 1 bit single. Each driver is composed of  
8 segments having binary weighted output resistance. The MSB  
segment typical ON resistance is 2Ω, when all segments are  
turned on; the output resistance is typically 1Ω. Usually all  
segments are turned on to define the normal transmission  
(non-modulated) level. It is also possible to switch off certain  
AS3911 – 16  
ams Datasheet, Confidential: 2013-Oct [2-03]  
Application I nform ation  
segments when driving the non-modulated level to reduce the  
amplitude of signal on the antenna and/or to reduce the  
antenna Q factor without making any hardware changes. The  
RFO Normal Level Definition Register defines which segments  
are turned on to define the normal transmission  
(non-modulated) level. Default setting is that all segments are  
turned on.  
Using the single driver mode the number and therefore the cost  
of the antenna LC tank components is halved, but also the  
output power is reduced. In single mode it possible to connect  
two antenna LC tanks to the two RFO outputs and multiplex  
between them by controlling the IO Configuration Register 1  
bit rfo2.  
In order to transmit the data the transmitter output level needs  
to be modulated. The AM and OOK modulation are supported.  
The type of modulation is defined by setting the bit tr_am in  
the Auxiliary Definition Register. For the operation modes  
supported by the AS3911 framing the setting of modulation  
type is done automatically by sending direct command Analog  
Preset.  
During the OOK modulation (for example ISO14443A) the  
Transmitter drivers stop driving the carrier frequency; drivers  
are frozen in state before the modulation. As consequence the  
amplitude of the antenna LC tank oscillation decays, the time  
constant of the decay is defined with the LC tank Q factor. The  
decay time in case of OOK modulation can be shortened by  
asserting the Auxiliary Definition Register bit ook_hr. When this  
bit is set to logic one the drivers are put in tristate during the  
OOK modulation.  
AM modulation (for example ISO14443B) is done by increasing  
the output driver impedance during the modulation time. This  
is done by reducing the number of driver segments which are  
turned on. The AM modulated level can be automatically  
adjusted to the target modulation depth by defining the target  
modulation depth in the AM Modulation Depth Control  
Register and sending the Calibrate Modulation Depth direct  
command. Please refer to AM Modulation Depth: Definition and  
Calibration for further details.  
Slow Transmitter Ramping  
When transmitter is enabled it starts to drive the antenna LC  
tank with full power, the ramping of field emitted by antenna  
is defined by antenna LC tank Q factor.  
However there are some reader systems where the reader field  
has to transition with a longer transition time when it is  
enabled. The STIF (Syndicat des transports d'Ile de France)  
specification requires a transition time from 10% to 90% of field  
longer than or equal to 10 μs.  
The AS3911 supports that feature. It is realized by collapsing  
VSP_RF regulated voltage when transmitter is disabled and  
ramping it when transmitter is enabled. Typical transition time  
is 15 μs at 3V supply and 20 μs at 5V supply.  
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 17  
A p p l i c a t i o n I n fo r m a t i o n  
Procedure to implement the slow transition:  
• When transmitter is disabled set IO Configuration Register  
2 bit slow_up to 1. Keep this state at least 2 ms to allow  
discharge of VSP_RF.  
• Enable transmitter, its output will ramp slowly.  
• Before sending any command set the bit slow_up back  
to 0.  
Receiver  
The receiver performs demodulation of the transponder  
sub-carrier modulation which is superimposed on the  
13.56MHz carrier frequency. It performs AM and/or PM  
demodulation, amplification, band-pass filtering and  
digitalization of sub-carrier signals. Additionally it performs  
RSSI measurement, automatic gain control (AGC) and Squelch  
function.  
In typical application the Receiver inputs RFI1 and RFI2 are  
outputs of capacitor dividers connected directly to the  
terminals of antenna coil. Such concept assures that the two  
input signals are in phase to the voltage on antenna coil. Care  
has to be taken during design of capacitive divider that the RFI1  
and RFI2 input signal pp value does not exceed the VSP_A  
supply voltage.  
Receiver comprises two complete receive channels for AM  
demodulation and PM demodulation. In case both channels are  
active the selection of channel used for reception framing is  
done automatically by receive framing logic. The receiver is  
switched on when Operation Control Register bit rx_en is set to  
one. Additionally the Operation Control Register contains bits  
rx_chn and rx_man; rx_chn defines whether both, AM and PM,  
demodulation channels will be active or only one of them, while  
bit rx_man defines the channel selection mode in case both  
channels are active (automatic or manual). Operation of the  
Receiver is controlled by four Receiver Configuration registers.  
The operation of the receiver is additionally controlled by the  
signal rx_on which is set high when modulated signal is  
expected on the receiver input. This signal is used to control  
RSSI and AGC and also enables processing of receiver output  
by Framing logic. Signal rx_on is automatically set high after  
Mask Receive timer expires. Signal rx_on can also be directly  
controlled by the controller by sending direct commands Mask  
Receive Data and Unmask Receive Data. Figure 12 illustrates the  
Receiver block diagram.  
Demodulation Stage  
First stage performs demodulation of transponder sub-carrier  
response signal, which is superimposed on HF field carrier. Two  
different blocks are implemented for AM demodulation: Peak  
Detector and AM demodulator mixer. The choice of the  
demodulator, which is used, is made by the Receiver  
Configuration Register 1 bit amd_sel.  
AS3911 – 18  
ams Datasheet, Confidential: 2013-Oct [2-03]  
Application I nform ation  
Peak detector performs AM demodulation using peak follower.  
Both, the positive and negative peaks are tracked to suppress  
common mode signal. It is limited in speed; it can operate for  
sub-carrier frequencies up to fc/8 (1700 kHz). It has  
demodulation gain G = 0.7. Its input is taken from one  
demodulator input only (usually RFI1).  
AM demodulator mixer uses synchronous rectification of both  
receiver inputs (RFI1 and RFI2). Its gain is G = 0.55. Mixer  
demodulator is optimized for VHBR sub-carrier frequencies.  
(fc/8 and higher). For sub-carrier frequency fc/8 (1700 kHz) both  
peak follower and mixer can be used, while for fc/4 and fc/2 are  
supported only by mixer.  
By default the Peak detector is used, for data rates fc/8 and  
higher use of mixer is automatically preset by sending direct  
command Analog Preset.  
PM demodulation is also done by a mixer. The PM demodulator  
mixer has differential outputs with 60mV differential signal for  
1% phase change (16.67 mV per degree). Its operation is  
optimized for sub-carrier frequencies up to fc/8 (1700 kHz).  
In case the demodulation is done externally of the AS3911 it is  
possible to multiplex the LF signals applied to pins RFI1 and  
RFI2 directly to the gain and filtering stage by selecting the  
Receiver Configuration Register 2 bit lf_en.  
Figure 12:  
Receiver Block Diagram  
rec1<7:6>  
rec2<6:5>  
AM  
Demodulator  
Mixer  
rec4<7:4>  
rec3<7:5>  
AGC  
Squelch  
RSSI  
RSSI_AM<3:0>  
M
U
X
digital  
RF_IN1  
Peak Detector  
sub-carrier  
RX_on  
sg_on  
rec4<3:0>  
RF_IN2  
rec3<4:2>  
AGC  
Squelch  
RSSI  
RSSI_PM<3:0>  
PM  
Demodulator  
Mixer  
digital  
sub-carrier  
rec3<2:0>  
rec1<5:3>  
Demodulation  
stage  
AC coupling  
+ 1st gain stage  
Low-pass  
+ 2nd gain stage  
High-pass  
+ 3rd gain stage  
Digitizing  
stage  
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 19  
A p p l i c a t i o n I n fo r m a t i o n  
Filtering and Gain Stages  
The receiver chain has band pass filtering characteristics.  
Filtering is optimized to pass sub-carrier frequencies while  
rejecting carrier frequency and low frequency noise and DC  
component. Filtering and gain is implemented in three stages  
where the first and the last stage have the first order high pass  
characteristics, while the mid stage has second order low pass  
characteristic.  
Gain and filtering characteristics can be optimized for current  
application by writing the Receiver Configuration Register 1  
(filtering), Receiver Configuration Register 3 (gain in first stage)  
and Receiver Configuration Register 4 (gain in second and third  
stage).  
Gain of first stage is about 20dB and can be reduced in six 2.5  
dB steps. There is also a special boost mode available, which  
boosts the maximum gain for additional 5.5 dB. In case of VHBR  
(fc/8 and fc/4) the gain is lower. The first stage gain can only be  
modified by writing Receiver Configuration Register 3. The  
default setting of this register is the minimum gain. Default first  
stage zero is located at 60 kHz, it can also be lowered to 40kHz  
or 12 kHz by writing option bits in the Receiver Configuration  
Register 1. The control of the first and third stage zeros is done  
with common control bits (see Figure 14).  
Gain in the second and third stage is 23 dB and can be reduced  
in six 3 dB steps. Gain of these two stages is included in AGC  
and Squelch loops or can be manually set in Receiver  
Configuration Register 4. Sending of direct command Reset Rx  
Gain is necessary to initialize the AGC, Squelch and RSSI block.  
Sending this command clears the current Squelch setting and  
loads the manual gain reduction from Receiver Configuration  
Register 4. Second stage has a second order low pass filtering  
characteristic, the pass band is adjusted according to  
sub-carrier frequency using the bits lp2 to lp0 of the Receiver  
Configuration Register 1. See Figure 13 for -1dB cut-off  
frequency for different settings.  
Figure 13:  
Low Pass Control  
rec1<5> lp2  
rec1<4> lp1  
rec1<3> lp0  
-1 dB point  
1200 kHz  
600 kHz  
300 kHz  
2 MHz  
0
0
0
1
1
0
0
1
0
0
1
0
1
0
0
7 MHz  
Other  
Not used  
AS3911 – 20  
ams Datasheet, Confidential: 2013-Oct [2-03]  
Application I nform ation  
Figure 14:  
First and Third Stage Zero Setting  
First Stage  
Zero  
Third Stage  
Zero  
rec1<2> h200  
rec1<1> h80  
rec1<0> z12k  
0
1
0
0
0
1
0
0
0
0
1
1
1
60 kHz  
60 kHz  
40 kHz  
12 kHz  
12 kHz  
12 kHz  
400 kHz  
200 kHz  
80 kHz  
0
1
0
1
200 kHz  
80 kHz  
0
200 kHz  
Other  
Not used  
Figure 15 provides information on the recommended filter  
settings. For all supported operation modes and receive bit  
rates there is an automatic preset defined, additionally some  
alternatives are listed. Automatic preset is done by sending  
direct command Analog Preset. There is no automatic preset for  
Steam and Transparent modes. Since selection of filter  
characteristics also modifies gain, the gain range for different  
filter settings is also listed.  
Figure 15:  
Receiver Filter Selection and Gain Range  
Gain [dB]  
Comment  
Automatic preset for ISO14443A fc/128  
and NFC Forum Type 1 Tag  
000  
000  
001  
000  
0
1
1
0
0
0
0
1
0
0
0
0
43.4  
44  
28  
29  
29  
26.4  
27.5  
27  
11  
12  
49.8  
49.7  
Automatic preset for ISO14443B fc/128  
ISO14443 fc/64  
Recommended for 424/484 kHz  
sub-carrier  
44.3  
11.7 49.8  
Alternative choice for ISO14443 fc/32 and  
fc/16  
41.1 25.8 23.6  
8.3  
46.8  
Automatic preset for ISO14443 fc/32 and  
100  
100  
0
0
1
0
0
0
32  
32  
17  
17  
17.2  
17.2  
2
2
37.6 fc/16  
Alternative choice for fc/8 (1.7 kb/s)  
37.6 Alternative choice for fc/8 (1.7 kb/s)  
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 21  
A p p l i c a t i o n I n fo r m a t i o n  
Gain [dB]  
Comment  
Automatic preset FeliCa (fc/64, fc/32)  
46.8 Alternative choice for ISO14443 fc/32 and  
fc/16  
000  
0
1
1
41.1 25.8 23.6  
8.3  
101  
101  
0
1
1
0
0
0
30  
30  
20  
20  
12  
12  
2
2
34  
34  
Alternative choice for fc/8 and fc/4  
Automatic preset for fc/8 and fc/4  
Automatic preset for NFCIP-1 (initiator and  
target)  
000  
1
0
1
36.5 21.5 24.9  
9.9  
41.5  
Digitizing Stage  
Digitizing stage is producing a digital form of sub-carrier signal  
which is output of Receiver and input to Framing Logic. It is a  
window comparator with adjustable digitizing window (five  
possible settings, 3 dB steps, adjustment range from 33 mV to  
120 mV). Adjustment of the digitizing window is included in  
AGC and Squelch loops or can be manually set in Receiver  
Configuration Register 4.  
AGC, Squelch and RSSI  
As mentioned above second and third gain stage gain and the  
Digitizing stage digitizing window are included in AGC and  
Squelch loops. Eleven settings are available, default state  
features minimum digitizer window and maximum gain, first  
four steps increase the digitizer window in 3 dB steps, next six  
nd  
rd  
steps additionally reduce the gain in 2 and 3 gain stage also  
in 3 dB steps. The initial setting with which Squelch and AGC  
start is defined in Receiver Configuration Register 4. The Gain  
Reduction State Register displays the actual state of gain which  
results from Squelch, AGC and initial settings in Receiver  
Configuration Register 4.  
Squelch  
This feature is designed for operation of receiver in noisy  
environment. The noise can come from tags in which  
processing of data sent by the reader is going on and an answer  
is being prepared. Noise can also be generated by noisy  
environment. This noise may be misinterpreted as start of  
transponder response which results in decoding error.  
During execution of the Squelch procedure the output of  
Digitizing comparator is observed. In case there are more than  
two transitions on this output in 50 μs time period, gain is  
reduced for 3 dB and output is observed during next 50 μs. This  
procedure is repeated until number of transitions in 50 μs is  
lower or equal to 2 or until maximum gain reduction is reached.  
This setting is cleared by sending direct command Reset Rx  
AS3911 – 22  
ams Datasheet, Confidential: 2013-Oct [2-03]  
Application I nform ation  
Gain.  
There are two possibilities of performing squelch: automatic  
mode and using direct command Squelch.  
• Automatic mode is started in case bit sqm_dyn in the  
Receiver Configuration Register 2 is set. It is activated  
automatically 18.88 μs after end of Tx and is terminated  
with Mask Receive timer expire. This mode is primarily  
intended to suppress noise generated by tag processing  
during the time when the tag response is not expected  
(covered by Mask Receive timer).  
• Command Squelch is accepted in case it is sent when  
signal rx_on is low. It can be used in case the time window  
in which noise is present is known by the controller.  
AGC  
AGC (automatic gain control) is used to reduce gain to keep  
receiver chain out of saturation. In case gain is properly  
adjusted the demodulation process is also less influenced by  
system noise.  
AGC action starts when signal rx_on is asserted high and is reset  
when it is reset to low. At low to high transitions of the rx_on  
the state of the receiver gain is stored in the Gain Reduction  
State Register, therefore reading this register later gives the  
information of the gain setting used during last reception.  
When AGC is switched on receiver gain is reduced so that the  
input to digitizer stage is not saturated. The AGC system  
comprises a window comparator which has its window 3.5 times  
larger than window of digitalization window comparator. When  
the AGC function is enabled gain is reduced until there are no  
transitions on its output. Such procedure assures that the input  
to digitalization window comparator is less than 3.5 times larger  
than its window.  
AGC operation is controlled by the control bits agc_en, agc_m  
and agc_fast in the Receiver Configuration Register 2. Bit  
agc_en enables the AGC operation; bit agc_m defines the AGC  
mode while bit agc_alg define the AGC algorithm.  
Two AGC modes are available, AGC can operate during  
complete Rx process (as long as signal rx_on is high) or it can  
be enabled only during first eight sub-carrier pulses.  
Two AGC algorithms are available; AGC can either start by  
presetting of code 4 (max digitizer window, max gain) or by  
h
resetting the code to 0 (min digitizer window, max gain).  
h
Algorithm with preset code is faster, therefore it is  
recommended for protocols with short SOF (like ISO14443A  
fc/128).  
Default AGC settings are: AGC is enabled, AGC operates during  
complete Rx process, algorithm with preset is used.  
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 23  
A p p l i c a t i o n I n fo r m a t i o n  
RSSI  
The receiver also performs the RSSI (Received Signal Strength  
Indicator) measurement of both channels. RSSI measurement  
is started after rising edge of rx_on. It stays active while signal  
rx_on is high; while rx_on is low it is frozen. It is a peak hold  
system; the value can only increase from initial zero value. Every  
time the AGC reduces the gain the RSSI measurement is reset  
and starts from zero. Result of RSSI measurements is 4-bit value  
which can be observed by reading the RSSI Display Register.  
The LSB step is 2.8 dB, the maximum code is D (13 ).  
h
d
Since the RSSI measurement is of peak hold type the RSSI  
measurement result does not follow any variations in the signal  
strength (the highest value will be kept). In order to follow RSSI  
variation it is possible to reset RSSI bits and restart the  
measurement by sending direct command Clear RSSI.  
Receiver in NFCIP-1 Active Communication Mode  
There are several features built in receiver to enable reliable  
reception of active NFCIP-1 communication. All these settings  
are automatically preset by sending direct command Analog  
Preset after the NFCIP-1 mode has been configured. In addition  
to filtering options there are two NFC specific configuration bits  
stored in the Receiver Configuration Register 3.  
Bit lim enables clipping circuits which are positioned after first  
and second gain stages. The intention of clipping circuits is to  
limit the signal level for the following filtering stage (in case the  
NFC peer is close the input signal level can be quite high).  
Bit rg_nfc forces gain reduction of second and third filtering  
stage to -6dB while keeping the digitizer comparator window  
at maximum level.  
Capacitive Sensor  
The Capacitive Sensor block provides a possibility of low power  
detection of tag presence.  
The capacitive measurement system comprises two electrodes.  
One is excitation electrode emitting electrical field of a fixed  
frequency in range of few hundred kHz (CSO) and the second  
one is the sensing electrode (CSI). The amount of charge gen-  
erated in sensing electrode represents the capacitance be-  
tween the two electrodes. Capacitive sensor electrodes are tol-  
erant to parasitic capacitance to ground (up to 25 pF) and to  
input leakage (up to 1 MΩ).  
Since the charge on the sensing electrode is generated with the  
frequency of excitation electrode, synchronous rectifier is used  
to detect it. This ensures good rejection of interference and  
high tolerance to parasitic capacitances (to all nodes except the  
excitation electrode).  
Capacitive sensor system depicted on figure below uses a syn-  
chronous rectifier to convert the AC charge generated by the  
excitation signal on the sensing electrode. This yields a DC out-  
AS3911 – 24  
ams Datasheet, Confidential: 2013-Oct [2-03]  
Application I nform ation  
put voltage, which is linearly proportional to the capacitance  
between the excitation and sensing electrode. The output DC  
voltage is converted by an AD converter in absolute mode. Re-  
sult is stored in the A/D Converter Output Register (see also A/D  
Converter).  
Figure 16:  
Capacitive Sensor Block Diagram  
CSO  
Oscillator  
CSI  
A/D  
Synchronous  
Converter  
Rectifier  
Any conductive object (human hand or tag's antenna windings)  
approaching the two electrodes changes the capacitance  
between the excitation and sensing electrode as it 'shortens'  
the distance between the two by providing conductance on the  
part of the path between the two electrodes.  
Capacitance measurement is started by sending direct  
command Measure Capacitance. The AS3911 can also be  
configured to periodically wake-up and perform the  
capacitance measurement. The result is compared to a stored  
reference or to an average of previous measurements and in  
case the difference is greater than a predefined value an IRQ is  
triggered to wake-up the controller (see also Wake-up Mode).  
Capacitor sensor gain can be adjusted by setting in Capacitive  
Sensor Control Register. Default gain is 2.8V/pF typ., maximum  
gain is 6.5V/pF typ. Since LSB of AD converter corresponds to  
approximately 7.8mV, the default gain results in sensitivity of  
2.8 fF/LSB (1.2 fF/LSB maximum).  
Capacitance measurement duration is 200 μs, current  
consumption during measurement is 1.1 mA typ. In case  
capacitive measurement is performed every 100 ms in Wake-up  
mode the resulting typical average consumption is 5.8μA  
(3.6μA is standby consumption in Wake-up mode).  
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 25  
A p p l i c a t i o n I n fo r m a t i o n  
Capacitor Sensor Calibration  
Capacitor sensor comprises calibration unit internally  
compensates the parasitic capacitances between CSI and CSO,  
thus leaving full measurement range for information about  
capacitance variation. 5 bits are used to control the calibration,  
minimum calibration step is 0.1pF, calibration range is 3.1pF.  
Calibration can be done manually by writing Capacitive Sensor  
Control Register or automatically by sending direct command  
Calibrate Capacitive Sensor. The status of Calibrate Capacitive  
Sensor command and resulting calibration value are stored in  
the Capacitive Sensor Display Register.  
In order to avoid interference of Capacitive Sensor with Xtal  
oscillator and reader magnetic field and to assure repetitive  
results it is strongly recommended to perform capacitance  
measurement and calibration in Power-down mode only.  
Wake-up Mode  
Asserting the Operation Control Register bit wu while the other  
bits are set to 0 puts the AS3911 into the Wake-up mode which  
is used to perform low power detection of card presence. The  
AS3911 includes several possibilities of low power detection of  
a card presence (capacitive sensor, phase measurement,  
amplitude measurement). Low power 32kHz RC oscillator and  
register configurable Wake-up timer are used to schedule  
periodic detection.  
Usually the presence of a card is detected by so called polling.  
In this process the reader is periodically turned on and the  
controller activates the protocol to check whether a card is  
present. Such procedure consumes a lot of energy since reader  
field has to be turned on for 5ms before a command can be  
issued.  
Low power detection of card presence is performed by  
detecting a change in reader environment, which is produced  
by presence of a card. When a change is detected, an interrupt  
is sent to the controller. As a result, the controller can activate  
the protocol for tag detection.  
In the Wake-up mode the AS3911 periodically performs the  
configured measurements and sends an IRQ to the controller,  
which is in deep sleep to minimize the current consumption,  
only when a difference to the build in reference is detected.  
Detection of card presence can be done by performing phase,  
amplitude and capacitive sensor measurements.  
Presence of a card close to the reader antenna coil produces  
due to the magnetic coupling of the two coils a change of the  
antenna LC tank signal phase and amplitude. The reader field  
activation time needed to perform the phase or the amplitude  
measurement is extremely short (~20μs) comparing to the  
AS3911 – 26  
ams Datasheet, Confidential: 2013-Oct [2-03]  
Application I nform ation  
activation time needed to send a protocol activation command.  
Additionally the power level during the measurement can be  
lower than the power level during normal operation since the  
card does not have to be powered to produce the coupling  
effect. The emitted power can be reduced by increasing the RFO  
Normal Level Definition Register.  
Capacitance Sensor detects a change of the parasite  
capacitance between the two excitation electrodes which is  
caused by a card antenna and a hand holding it. See “Capacitive  
Sensor” on page 14 for a detailed information on the capacitive  
sensor.  
The registries on locations from 31 to 3D are dedicated to  
h
h
Wake-up configuration and display. The Wake-up Timer Control  
Register is the main Wake-up mode configuration register. The  
timeout period between the successive detections and the  
measurements which are going to be used are selected in this  
register. Timeouts in the range from 10 ms to 800 ms are  
available, 100 ms is the default value. Any combination of  
available measurements can be selected (one, two or all of  
them).  
The following twelve registers (32 to 3D ) are configuring the  
h
h
three possible detection measurements and storing the results,  
four registers are used for each measurement.  
An IRQ is sent when the difference between a measured value  
and reference value is larger than configured threshold value.  
There are two possibilities how to define the reference value:  
• The AS3911 can calculate the reference based on previous  
measurements (auto-averaging)  
• The controller determines the reference and stores it in a  
register  
The first register in the series of four is the Measurement  
Configuration Register (see for e.g. Amplitude Measurement  
Configuration Register). The difference to reference which  
triggers the IRQ, the method of reference value definition and  
the weight of last measurement result in case of auto-averaging  
are defined in this register. The next register is storing the  
reference value in case the reference is defined by the  
controller. The following two registers are display registers. The  
first one stores the auto-averaging reference; the second one  
stores the result of the last measurement.  
Wake-up mode configuration registers have to be configured  
before wake-up mode is actually entered. Any modification of  
Wake-up mode configuration while it is active may result in  
unpredictable behavior.  
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 27  
A p p l i c a t i o n I n fo r m a t i o n  
Auto-averaging  
In case of auto-averaging the reference value is recalculated  
after every measurement. The last measurement value, the old  
reference value and the weight are used in this calculation. The  
following formula is used to calculate the new reference value.  
OldReference – MeasuredValue  
------------------------------------------------------------------------------------  
NewReference = OldReference +  
Weight  
The calculation is done on 10 bits to have sufficient precision.  
The auto-averaging process is initialized when Wake-up mode  
is first time entered after initialization (power-up or using Set  
Default command). The initial value is taken from the  
Measurement Reference Register (for example Amplitude  
Measurement Reference Register) in case content of this  
register is not zero. In case content of this register is zero, the  
result of first measurement is taken as initial value.  
Every Measurement Configuration register contains a bit which  
defines whether the measurement which causes an interrupt is  
taken in account for the average value calculation (for example  
bit am_aam of the Amplitude Measurement Reference Regis-  
ter).  
Quartz Crystal Oscillator  
The quartz crystal oscillator can operate with 13.56 MHz and  
27.12 MHz crystals. The operation of quartz crystal oscillator is  
enabled when the Operation Control Register bit en is set to  
one. An interrupt is sent to inform the microcontroller when the  
oscillator frequency is stable (see Main Interrupt Register).  
The status of oscillator can be observed by observing the  
Auxiliary Display Register bit osc_ok. This bit is set to ‘1’ when  
oscillator frequency is stable.  
The oscillator is based on an inverter stage supplied by  
controlled current source. A feedback loop is controlling the  
bias current in order to regulate amplitude on XTI pin to 1V  
.
pp  
This feedback assures reliable operation even in case of low  
quality crystals with R up to 50 Ω.In order to enable a fast reader  
s
start-up an interrupt is sent when oscillator amplitude exceeds  
750 mV  
.
pp  
Division by two assures that 13.56MHz signal has a duty cycle  
of 50% which is better for the Transmitter performance (no PW  
distortion). Use of 27.12MHz crystal is therefore recommended  
for better performance.  
In case of 13.56 MHz crystal, the bias current of stage which is  
digitizing oscillator signal is increased to assure as low PW  
distortion as possible.  
Please note that in case of VHBR reception (bit rates fc/8 and  
above) it is mandatory to use the 27.12MHz crystal since high  
frequency clock is needed for receive framing.  
AS3911 – 28  
ams Datasheet, Confidential: 2013-Oct [2-03]  
Application I nform ation  
The oscillator output is also used to drive a clock signal output  
pin MCU_CLK), which can be used by the external  
microcontroller. The MCU_CLK pin is configured in the IO  
Configuration Register 2.  
Timers  
The AS3911 contains several timers which eliminate the need  
to run counters in the controller, thus reducing the effort of the  
controller code implementation and improve portability of  
code to different controllers.  
Every timer has one or more associated configuration registers  
in which the timeout duration and different operating modes  
are defined. These configuration registers have to be set while  
the corresponding timer is not running. Any modification of  
timer configuration while the timer is active may result in  
unpredictable behavior.  
All timers except the Wake-up timer are stopped by direct  
command Clear.  
Exception: In case bit nrt_emv in the General Purpose and  
No-response Timer Control Register is set to one, the  
No-response timer is not stopped.  
Mask Receive Timer and No-response Timer  
Mask Receive Timer and No-response Timer are both  
automatically started at the end of transmission (at the end of  
EOF).  
Mask Receive Timer  
The Mask Receive Timer is blocking the Receiver and reception  
process in framing logic by keeping the rx_on signal low after  
the end of Tx during the time the tag reply is not expected.  
While the Mask Receive timer is running, the Squelch is  
automatically turned on (if enabled). Mask receive timer does  
not produce an IRQ.  
The Mask Receive Timer timeout is configured in the Mask  
Receive Timer Register.  
In the NFCIP-1 active communication mode the Mask receive  
timer is started when the peer NFC device (a device with which  
communication is going on) switches on its field.  
The Mask Receive timer has a special use in the low power Initial  
NFC Target Mode. After the initiator field has been detected the  
controller turns on the oscillator, regulator and receiver. Mask  
Receive timer is started by sending direct command Start  
Mask-receive Timer. After the Mask Receive Timer expires the  
receiver output starts to be observed to detect start of the  
initiator message. In this mode the Mask Receive Timer clock is  
additionally divided by eight it (one count is 512/fc) to cover  
range up to ~9.6ms.  
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 29  
A p p l i c a t i o n I n fo r m a t i o n  
No-response Timer  
As its name indicates this timer is intended to observe whether  
a tag response was detected in a configured time started by  
end of transmission. The I_nre flag in the Timer and NFC  
Interrupt Register is signaling interrupt events resulting from  
this timer timeout.  
The No-response Timer is configured by writing two  
No-response Timer setting registers: No-response Timer  
Register 1and No-response Timer Register 2. Operation options  
of the No-response timer are defined by setting bits nrt_emv  
and nrt_step in the General Purpose and No-response Timer  
Control Register.  
Bit nrt_step configures the time step of the No-response Timer.  
Two steps are available, 64/fc (4.72μs), which covers range up  
to 309ms and 4096/fc, which covers range up to 19.8s.  
Bit nrt_emv controls the timer operation mode:  
• When this bit is set to 0 (default mode) the IRQ is produced  
in case the No-response timer expires before a start of a  
tag reply is detected. In the opposite case, when start of  
a tag reply is detected before timeout, the timer is  
stopped, and no IRQ is produced.  
• When this bit is set to 1 the timer unconditionally  
produces an IRQ when it expires, it is also not stopped by  
direct command Clear. This means that IRQ is independent  
of the fact whether or not a tag reply was detected. In case  
at the moment of timeout a tag reply is being processed  
no other action is taken, in the opposite case, when no tag  
response is being processed additionally the signal rx_on  
is forced to low to stop receive process.  
The No-response Timer can also be started using direct  
command Start No-response Timer. The intention of this  
command is to extend the No-response timer timeout beyond  
the range defined in the No-response Timer control registers.  
In case this command is sent while the timer is running, it is  
reset and restarted.  
In the NFCIP-1 active communication mode the No-response  
Timer is automatically started when the transmitter is turned  
off after the message has been sent. In case this timer expires  
before the peer NFC device (a device with which  
communication is going on) switches on its field an interrupt is  
sent.  
General Purpose Timer  
The triggering of the General Purpose Timer is configured by  
setting the General Purpose and No-response Timer Control  
Register. It can be used to survey the duration of reception  
process (triggering by start of reception, after SOF) or to time  
out the PCD to PICC response time (triggered by end of  
reception, after EOF). In the NFCIP-1 active communication  
mode it is used to timeout the field switching off. In all cases an  
IRQ is sent when it expires.  
AS3911 – 30  
ams Datasheet, Confidential: 2013-Oct [2-03]  
Application I nform ation  
The General Purpose Timer can also be started by sending the  
direct command Start General Purpose Timer. In case this  
command is sent while the timer is running, it is reset and  
restarted.  
Wake-up Timer  
Wake timer is primarily used in the Wake-up mode (see  
“Wake-up Mode” on page 26). Additionally it can be used by  
sending a direct command Start Wake-up Timer. This command  
is accepted in any operation mode except Wake-up mode.  
When this command is send the RC oscillator, which is used as  
clock source for wake-up timer is started, timeout is defined by  
setting in the Wake-up Timer Control Register. When the timer  
expires, an IRQ with the I_wt flag in the Error and Wake-up  
Interrupt Register is sent.  
Wake-up timer is useful in the Power-down mode, in which  
other timers cannot be used (in the Power-down mode the  
crystal oscillator, which is clock source for the other timers, is  
not running). Please note that the tolerance of wake-up timer  
timeout is defined by tolerance of the RC oscillator.  
A/D Converter  
The AS3911 contains an 8-bit successive approximation A/D  
converter. Input to A/D converter can be multiplexed from  
different sources to be used in several direct commands and  
adjustment procedures. The result of last A/D conversion is  
stored in the A/D Converter Output Register. Typical conversion  
time is 224/fc (16.5 μs).  
The A/D converter has two operating modes, absolute and  
relative.  
• In absolute mode the low reference is 0V and the high  
reference is 2V. This means that A/D converter input range  
is from 0 to 2V, 00 code means input is 0V or lower, FF  
h
h
means that input is 2V - 1LSB or higher, LSB is 7.8125 mV.  
• In relative mode low reference is 1/6 of VSP_A and high  
reference is 5/6 of VSP_A, so the input range is from 1/6  
VSP_A to 5/6 VSP_A.  
Relative mode is only used in phase measurement (phase  
detector output is proportional to power supply). In all other  
cases absolute mode is used.  
Phase and Amplitude Detector  
This block is used to provide input to A/D Converter to perform  
measurements of amplitude and phase, expected by direct  
commands Measure Amplitude and Measure Phase. Several  
phase and amplitude measurements are also performed by  
direct commands Calibrate Modulation Depth and Calibrate  
Antenna.  
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 31  
A p p l i c a t i o n I n fo r m a t i o n  
Phase Detector  
The phase detector is observing phase difference between the  
transmitter output signals (RFO1 and RFO2) and the receiver  
input signals RFI1 and RFI2, which are proportional to the signal  
on the antenna LC tank. These signals are first passed by  
digitizing comparators. Digitized signals are processed by a  
phase detector with a strong low pass filter characteristics to  
get average phase difference. The Phase Detector output is  
inversely proportional to the phase difference between the two  
inputs. The 90° phase shift results in VSP_A/2 output voltage,  
in case both inputs are in phase output voltage is VSP_A in case  
they are in opposite phase output voltage is zero. During  
execution of direct command Measure Phase this output is  
multiplexed to A/D Converter input (A/D Converter is in relative  
mode during execution of command Measure Phase). Since the  
A/D converter range is from 1/6 VSP_A to 5/6 VSP_A the actual  
phase detector range is from 30º to 150º. Figures below depict  
the two inputs and output of phase detector in case of 90º and  
135º phase shift.  
Figure 17:  
Phase Detector Inputs and Output in case of 90º Phase Shift  
VSP  
VSP  
VSP  
VSP/2  
0
AS3911 – 32  
ams Datasheet, Confidential: 2013-Oct [2-03]  
Application I nform ation  
Figure 18:  
Phase Detector Inputs and Output in case of 135º Phase  
Shift  
VSP  
VSP  
VSP  
VSP/2  
0
Amplitude Detector  
Signals from pins RFI1 and RFI2 are used as inputs to the  
self-mixing stage. Output of this stage is DC voltage  
proportional to amplitude of signal on pins RFI1 and RFI2.  
During execution of direct command Measure Amplitude this  
output is multiplexed to A/D Converter input.  
External field Detector  
The External Field Detector is used to detect the presence of an  
external device generating an RF field. It is automatically  
switched on in NFCIP-1 active communication modes; it can  
also be used in other modes. The External Field Detector  
supports two different detection thresholds, Peer Detection  
Threshold and Collision Avoidance Threshold. The two  
thresholds can be independently set by writing the External  
Field Detector Threshold Register. The actual state of the  
External Field Detector output can be checked by reading the  
Auxiliary Display Register. Input to this block is the signal from  
the RFI1 pin.  
Peer Detection Threshold  
This threshold is used to detect the field emitted by peer NFC  
device with which NFC communication is going on (initiator  
field in case the AS3911 is a target and the opposite, target field  
in case the AS3911 is an initiator). It can be selected in the range  
from 75mV to 800mV . When this threshold is enabled the  
pp  
pp  
External Field Detector is in low power mode. An interrupt is  
generated when an external field is detected and also when it  
is switched off. With such implementation it can also be used  
to detect the moment when the external field disappears. This  
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 33  
A p p l i c a t i o n I n fo r m a t i o n  
is useful to detect the moment when the peer NFC device (it  
can be either an initiator or a target) has stopped emitting an  
RF field.  
The External Field Detector is automatically enabled in the low  
power Peer Detection mode when NFCIP-1 mode (initiator or  
target) is selected in the Bit Rate Definition Register.  
Additionally it can be enabled by setting bit en_fd in the  
Auxiliary Definition Register.  
Collision Avoidance Threshold  
This threshold is used during the RF Collision Avoidance  
sequence which is executed by sending NFC Field ON  
commands (see “NFC Field ON Commands” on page 51). It can  
be selected in the range from 25 mV to 800 mV  
.
pp  
pp  
Power Supply System  
The AS3911 features two positive supply pins, V and V  
.
DD_IO  
DD  
V
is the main power supply pin. It supplies the AS3911 blocks  
DD  
through three regulators (V  
, V  
and V  
). V range  
DD_RF DD  
DD_A DD_D  
from 2.4 to 5.5V is supported.  
is used to define supply level for digital communication  
V
DD_IO  
pins (/SS, MISO, MOSI, SCLK, IRQ, MCU_CLK). Digital  
communication pins interface to the AS3911 logic through level  
shifters, therefore the internal supply voltage can be either  
higher or lower than V  
. V  
range from 1.65V to 5.5V is  
DD_IO DD_IO  
supported.  
Figure 19 shows the building blocks of the AS3911 power  
supply system. It contains three regulators, a power-down  
support block, a block generating analog reference voltage  
(AGD) and a block performing automatic power supply  
adjustment procedure. The three regulators are providing  
supply to analog blocks (VSP_A), logic (VSP_D) and transmitter  
(VSP_RF). The use of VSP_A and VSP_D regulators is mandatory  
at 5V power supply to provide regulated voltage to analog and  
logic blocks which only use 3.3V devices. The use of VSP_A and  
VSP_D regulators at 3V supply and VSP_RF regulator at any  
supply voltage is recommended to improve system PSRR.  
Regulated voltage can be adjusted automatically to have  
maximum possible regulated voltage while still having good  
PSRR. All regulator pins also have corresponding negative  
supply pins which are externally connected to ground potential  
(VSS). The reason for separation is in decoupling of noise  
induced by voltage drops on the internal power supply lines.  
Figure 10 and Figure 11 depict typical AS3911 application  
schematics with all regulators used. All regulator pins and AGD  
voltage are buffered with pairs of ceramic and electrolyte. For  
regulators recommended blocking capacitors values can be  
found in the table below are 2.2μF in parallel with 10nF, for pin  
AGD 1μF in parallel with 10nF is suggested.  
AS3911 – 34  
ams Datasheet, Confidential: 2013-Oct [2-03]  
Application I nform ation  
Figure 19:  
The AS3911 Power Supply System  
VDD  
EN  
sup3V  
VSP_D  
REG  
Power-down  
Support  
VSP_A  
REG  
VSP_RF  
REG  
VSP_RF  
50 ohm  
VSP_A  
VSP_D  
BGR  
&
AGD  
AGC  
RV<3:0>  
AUTOREG  
reg2Ah  
reg2Bh  
adjust  
Regulators have two basic operation modes depending on  
supply voltage, 3.3V supply mode (max 3.6V) and 5V supply  
mode (max 5.5V). The supply mode is set by writing bit sup3V  
in the IO Configuration Register 2. Default setting is 5V so this  
bit has to be set to one after power-up in case of 3.3V supply.  
In 3.3V mode all regulators are set to the same regulated voltage  
in range from 2.4V to 3.4V, while in 5V only the VSP_RF can be  
set in range from 3.9V to 5.1V, while VSP_A and VSP_D are fixed  
to 3.4V.  
Figure 19 depicts signals controlling the power supply system.  
The regulators are operating when signal en is high (en is  
configuration bit in Operation Control Register). When signal  
en is low the AS3911 is in low power Power-down mode. In this  
mode consumption of the power supply system is also  
minimized.  
VSP_RF Regulator  
The intention of this regulator is to improve PSRR of the  
Transmitter (the noise of the Transmitter power supply is  
emitted and fed back to the Receiver). The VSP_RF regulator  
operation is controlled and observed by writing and reading  
two regulator registers:  
Regulator Voltage Control Register controls the regulator  
mode and regulated voltage. Bit reg_s controls regulator  
mode. In case it is set to 0 (default state) the regulated  
voltage is set using direct command Adjust Regulators.  
When bit reg_s is asserted to 1 regulated voltage is defined  
by bits rege_3 to rege_1 of the same register. The regulated  
voltage adjustment range depends on the power supply  
mode. In case of 5V supply mode the adjustment range is  
between 3.9V and 5.1 V in steps of 120 mV, in case of 3.3V  
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 35  
A p p l i c a t i o n I n fo r m a t i o n  
supply mode the adjustment range is from 2.4V to 3.4V  
with steps of 100mV. Default regulated voltage is the  
maximum one (5.1V and 3.4V in case of 5V and 3.3V supply  
mode respectively).  
Regulator and Timer Display Register is a read only register  
which displays actual regulated voltage when regulator is  
operating. It is especially useful in case of automatic mode,  
since the actual regulated voltage, which is result of direct  
command Adjust Regulators, can be observed.  
The VSP_RF regulator also includes a current limiter which limits  
the regulator current to 300mA  
in normal operation (500mA  
rms  
in case of short). In case the Transmitter output current higher  
the 300mA is required VSP_RF regulator cannot be used to  
rms  
supply the Transmitter, VSP_RF has to be externally connected  
to V (connection of VSP_RF to supply voltage higher than V  
DD  
DD  
is not allowed).  
The voltage drop of the Transmitter current is the main source  
of the AS3911 power dissipation. This voltage drop is composed  
of drop in the Transmitter driver and in the drop on VSP_RF  
regulator. Due to this it is recommended to set regulated  
voltage using direct command Adjust Regulators. It results in  
good power supply rejection ration with relatively low  
dissipated power due to regulator voltage drop.  
In Power-down mode the VSP_RF regulator is not operating.  
VSP_RF pin is connected to V through 1 kΩ resistor.  
DD  
Connection through resistors assures smooth power-up of the  
system and a smooth transition from Power-down mode to  
other operating modes.  
VSP_A and VSP_D Regulators  
VSP_A and VSP_D regulators are used to supply the AS3911  
analog and digital blocks respectively. In 3.3 V mode, VSP_A and  
VSP_D regulator are set to the same regulated voltage as the  
VSP_RF regulator, in 5 V mode VSP_A and VSP_D regulated  
voltage is fixed to 3.4 V.  
The use of VSP_A and VSP_D regulators is obligatory in 5 V mode  
since analog and digital blocks supplied with these two pins  
contain low voltage transistors which support maximum supply  
voltage of 3.6 V. In 3.3 supply mode the use of regulators is  
strongly recommended in order to improve PSRR of analog  
processing.  
For low cost applications it is possible to disable the VSP_D  
regulator and to supply digital blocks through external short  
between VSP_A and VSP_D (configuration bit vspd_off in the IO  
Configuration Register 2). In case VSD_D regulator is disabled  
VSP_D can alternatively be supplied from V (in 3.3 V mode  
DD  
only) in case VSP_A is not more than 300mV lower than V  
.
DD  
AS3911 – 36  
ams Datasheet, Confidential: 2013-Oct [2-03]  
Application I nform ation  
Power-down Support Block  
In the Power-down mode the regulators are disabled in order  
to save current. In this mode a low power Power-down Support  
block which maintains the VSP_D and VSP_A in below 3.6V is  
enabled. Typical regulated voltage in this mode is 3.1V at 5V  
supply and 2.2V at 3V supply. When 3.3 V supply mode is set  
the Power-down Support block is disabled, its output is  
connected to V through 1kΩ resistor.  
DD  
Typical consumption of Power-down Support block is 600nA at  
5V supply.  
Measurement of Supply Voltages  
Using direct command Measure Power Supply it is possible to  
measure V and regulated voltages VSP_A, VSP_D, and  
DD  
VSP_RF.  
Communication to External Microcontroller  
The AS3911 is a slave device and the external microcontroller  
initiates all communication. Communication is performed by a  
4-wire Serial Peripheral Interface (SPI). The AS3911 asks  
microcontroller for its attention by sending an interrupt (pin  
IRQ). In addition, the microcontroller can use clock signal  
available on pin MCU_CLK when the oscillator is running.  
Serial Peripheral Interface (SPI)  
While signal /SS is high the SPI interface is in reset, while it is  
low the SPI interface is enabled. It is recommended to keep  
signal /SS high whenever the SPI interface is not in use. MOSI is  
sampled at the falling edge of SCLK. All communication is done  
in blocks of 8 bits (bytes). First two bits of first byte transmitted  
after high to low transition of /SS define SPI operation mode.  
MSB bit is always transmitted first (valid for address and data).  
Read and Write modes support address auto-incrementing,  
which means that in case after the address and first data byte  
some additional data bytes are sent (read), they are written to  
(read from) addresses incremented by ‘1. Figure 22 defines  
possible modes.  
MISO output is usually in tristate, it is only driven when output  
data is available. Due to this the MOSI and the MISO can be  
externally shorted to create a bidirectional signal.  
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 37  
A p p l i c a t i o n I n fo r m a t i o n  
During the time the MISO output is in tristate, it is possible to  
switch on a 10kΩ pull down by activating option bits miso_pd1  
and miso_pd2 in the IO Configuration Register 2.  
Figure 20:  
Serial Data Interface (4-wire interface) Signal Lines  
Name  
/SS  
Signal  
Digital input with pull-up  
Digital input  
Signal Level  
CMOS  
Description  
SPI Enable (active low)  
Serial data input  
MOSI  
CMOS  
Digital output with  
tristate  
MISO  
SCLK  
CMOS  
CMOS  
Serial data output  
Clock for serial  
communication  
Digital input  
Figure 21:  
Signal to Microcontroller  
Separate SPI Input and Output Signals to Microcontroller  
Bidirectional Data IO Signal to Microcontroller  
MOSI  
AS3911  
MISO  
MOSI  
MISO  
MOSI  
MISO  
I/O  
AS3911  
AS3911 – 38  
ams Datasheet, Confidential: 2013-Oct [2-03]  
Application I nform ation  
Figure 22 provides information on the SPI operation modes.  
Reading and writing of registers is possible in any AS3911  
operation mode. FIFO operations are possible in case en (bit 7  
of the Operation Control Register) is set and Xtal oscillator  
frequency is stable.  
Figure 22:  
SPI Operation Modes  
MODE Pattern (communication bits)  
MODE Trailer  
M1 M0 C5 C4 C3 C2 C1 C0  
MODE  
MODE Related Data  
Data byte (or more bytes in case  
of auto-incrementing)  
Register Write  
Register Read  
0
0
0
1
A5  
A5  
A4  
A4  
A3  
A3  
A2  
A2  
A1  
A1  
A0  
A0  
Data byte (or more bytes in case  
of auto-incrementing)  
FIFO Load  
FIFO Read  
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
One or more bytes of FIFO data  
One or more bytes of FIFO data  
Direct Command  
Mode  
1
1
C5  
C4  
C3  
C2  
C1  
C0  
Writing of Data to Addressable Registers (Write  
Mode)  
Following figures show cases of writing a single byte and  
writing multiple bytes with auto-incrementing address. After  
the SPI operation mode bits, the address of register to be  
written is provided. Then one or more data bytes are transferred  
from the SPI, always from the MSB to the LSB. The data byte is  
written in register on falling edge of its last clock. In case the  
communication is terminated by putting /SS high before a  
packet of 8 bits composing one byte is sent, writing of this  
register is not performed. In case the register on the defined  
address does not exist or it is a read only register no write is  
performed.  
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 39  
A p p l i c a t i o n I n fo r m a t i o n  
Figure 23:  
SPI Communication: Writing of Single Byte  
/SS  
SCLK  
A
5
A
4
A
3
A
2
A
1
A
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
X
X
0
0
MOSI  
Two leading  
bits indicate  
Mode  
Data is moved to  
Address  
/SS rising edge  
signals end of  
WRITE Mode  
SCLK falling  
edge Data is  
sampled  
SCLK rising  
edge Data is  
transfered  
from µC  
A5-A0  
Figure 24:  
SPI Communication: Writing of Multiple Bytes  
/SS  
SCLK  
A A A  
A
2
A A D D D D D D D D D D D D D D D D D D  
D D D D D D D D D  
1 0 7 6 5 4 3 2 1  
D
0
X
MOSI  
X
0 0  
5
4
3
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
Two leading  
bits indicate  
Mode  
Data is moved Data is moved to Data is moved to Data is moved to  
/SS rising edge  
signals end of  
WRITE Mode  
to Address  
<A5-A0>  
Address  
<A5-A0> + 1  
Address  
<A5-A0> + (n-1)  
Address  
<A5-A0> + n  
Reading of Data from Addressable Registers (Read  
Mode)  
After the SPI operation mode bits the address of register to be  
read has to be provided from the MSB to the LSB. Then one or  
more data bytes are transferred to MISO output, always from  
the MSB to the LSB. As in case of the write mode also the read  
mode supports auto-incrementing address.  
MOSI is sampled at the falling edge of SCLK (like shown in the  
following diagrams), data to be read from the AS3911 internal  
register is driven to MISO pin on rising edge of SCLK and is  
sampled by the master at the falling edge of SCLK.  
In case the register on defined address does not exist all 0 data  
is sent to MISO.  
Figure 25 provides an example for reading of single byte.  
AS3911 – 40  
ams Datasheet, Confidential: 2013-Oct [2-03]  
Application I nform ation  
Figure 25:  
SPI Communication: Reading of Single Byte  
/S S  
S C LK  
A
5
A
4
A
3
A
2
A
1
A
0
X
X
0
1
M O S I  
M IS O  
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
tristate  
tristate  
Tw o leading  
bits indicate  
M ode  
S C LK falling edge  
D ata is transfered  
to µC  
/S S rising edge  
signals end of R E A D  
M ode  
S C LK rising  
edge D ata is  
transfered  
from µ C  
S C LK rising  
edge D ata is  
m oved from  
A ddress  
S C LK falling  
edge D ata is  
sam pled  
<A5-A0>  
Loading Transmitting Data into FIFO  
Loading the transmitting data into the FIFO is similar to writing  
data into an addressable registers. Difference is that in case of  
loading more bytes all bytes go to the FIFO. SPI operation mode  
bits 10 indicate FIFO operations. In case of loading transmitting  
data into FIFO all bits <C5 – C0> are set to 0. Then a bit-stream,  
the data to be sent (1 to 96 bytes), can be transferred. In case  
the command is terminated by putting /SS high before a packet  
of 8 bits composing one byte is sent, writing of that particular  
byte in FIFO is not performed.  
Figure 26 shows how to load the Transmitting Data into the  
FIFO.  
Figure 26:  
SPI Communication: Loading of FIFO  
/SS  
SCLK  
1 to 32  
bytes  
MOSI  
X
1
0
0
0
0
0
0
0
X
10 pattern  
indicates  
FIFO mode  
Start of payload  
Data  
SCLK falling  
edge Data is  
sampled  
SCLK rising  
edge Data is  
transfered  
from µC  
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 41  
A p p l i c a t i o n I n fo r m a t i o n  
Reading Received Data from FIFO  
Reading received data from the FIFO is similar to reading data  
from an addressable registers. Difference is that in case of  
reading more bytes they all come from the FIFO. SPI operation  
mode bits 10 indicate FIFO operations. In case of reading the  
received data from the FIFO all bits <C5 – C0> are set to 1. On  
the following SCLK rising edges the data from FIFO appears as  
in case of read data from addressable registers. In case the  
command is terminated by putting /SS high before a packet of  
8 bits composing one byte is read that particular byte is  
considered unread and will be the first one read in next FIFO  
read operation.  
Figure 27:  
SPI Communication: Reading of FIFO  
/S S  
S C LK  
X
X
1
0
1
1
1
1
1
1
M O S I  
M IS O  
1 to 32  
bytes  
tristate  
tristate  
10 pattern  
indicates  
FIFO m ode  
S C LK falling  
edge D ata is  
transfered to  
µ C  
S C LK falling  
edge D ata is  
sam pled  
SC LK rising  
edge D ata is  
m oved from  
FIFO  
SC LK rising  
edge D ata is  
transfered  
from µ C  
Direct Command Mode  
Direct Command Mode has no arguments, so a single byte is  
sent. SPI operation mode bits 11 indicate Direct Command  
Mode. The following six bits define command code, sent MSB  
to the LSB. The command is executed on falling edge of last  
clock.  
While execution of some Direct Commands is immediate, there  
are others which start a process of certain duration (calibration,  
measurement…). During execution of such commands it is not  
allowed to start another activity over the SPI interface. After  
execution of such a command is terminated an IRQ is sent.  
AS3911 – 42  
ams Datasheet, Confidential: 2013-Oct [2-03]  
Application I nform ation  
Figure 28:  
SPI Communication: Direct Command  
/SS  
SCLK  
X
MOSI  
X
1
1
C5  
C4  
C3  
C2  
C1  
C0  
SCLK falling  
edge Data is  
sampled  
Two leading  
ONE indicate  
COMMAND  
Mode  
/SS rising edge  
signals start of  
command  
SCLK rising  
edge Data is  
transfered  
from µC  
execution  
Direct Command Chaining  
Direct commands with immediate execution can be followed  
by another SPI mode (Read, Write or FIFO) without deactivating  
/SS signal in between.  
Figure 29:  
Direct Command Chaining  
/SS  
Direct Command  
Read, Write or FIFO Mode  
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 43  
A p p l i c a t i o n I n fo r m a t i o n  
SPI Timing  
Figure 30:  
SPI Timing  
Symbol  
Parameter  
Min  
Typ  
Max  
Unit  
Notes  
General Timing (V = V  
= V  
= 3.3 V, Temperature 25°C)  
DD_D  
DD  
DD_IO  
T
=T  
+T  
use  
SCLK SCLKL SCLKH,  
of shorter SCLK period  
may lead to incorrect  
operation of FIFO  
T
SCLK period  
100  
ns  
SCLK  
T
SCLK low  
SCLK high  
40  
40  
ns  
ns  
ns  
ns  
SCLKL  
T
SCLKH  
T
SPI reset (/SS high)  
/SS falling to SCLK rising  
100  
25  
SSH  
T
First SCLK pulse  
Last SCLK pulse  
NCSL  
25  
(tbd)  
T
SCLK falling to /SS rising  
ns  
NCSH  
T
Data in setup time  
Data in hold time  
10  
ns  
ns  
DIS  
T
10  
DIH  
Read Timing (V = V  
= V  
= 3.3 V, Temperature 25°C, CLOAD 50 pF)  
DD_D  
DD  
DD_IO  
T
Data out delay  
20  
20  
ns  
ns  
DOD  
Data out to high  
impedance delay  
T
DOHZ  
Figure 31:  
SPI General Timing  
/SS  
...  
...  
tNCSL  
tSCLKH  
tSCLKL  
tNCSH  
SCLK  
tDIS  
tDIH  
...  
...  
DATAI  
DATAI  
DATAI  
MOSI  
MISO  
AS3911 – 44  
ams Datasheet, Confidential: 2013-Oct [2-03]  
Application I nform ation  
Figure 32:  
SPI Read Timing  
...  
...  
/S S  
S C L K  
...  
...  
D A T A I  
M O S I  
M IS O  
D A T A O  
D A T A O  
tD O H Z  
tD O D  
Interrupt Interface  
There are three interrupt registers implemented in the AS3911  
(Main Interrupt Register and auxiliary Timer and NFC Interrupt  
Register and Error and Wake-up Interrupt Register). Main  
Interrupt Register contains information about six interrupt  
sources, while two bits reference to interrupt sources detailed  
in Timer and NFC Interrupt Register and Error and Wake-up  
Interrupt Register.  
When an interrupt condition is met the source of interrupt bit  
is set in the Main Interrupt Register and the IRQ pin transitions  
to high.  
The microcontroller then reads the Main Interrupt Register to  
distinguish between different interrupt sources. In case the bits  
pointing to auxiliary Interrupt register are set, additionally  
corresponding auxiliary interrupt register(s) has to be read.  
After a particular Interrupt Register is read, its content is reset  
to 0. Exceptions to this rule are the bits pointing to auxiliary  
registers. These bits are only cleared when corresponding  
auxiliary register is read. IRQ pin transitions to low after the  
interrupt bit(s) which caused its transition to high has been  
read. Please note that there may be more than one interrupt  
bits set in case the microcontroller did not immediately read  
the interrupt registers after the IRQ signal was set and another  
event causing interrupt occurred. In that case the IRQ pin  
transitions to low after the last bit which caused interrupt is  
read.  
In case an interrupt from a certain source is not required it can  
be disabled by setting corresponding bit in the Mask Interrupt  
registers. In case of masking a certain interrupt source the  
interrupt is not produced, but the source of interrupt bit is still  
set in interrupt registers.  
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 45  
A p p l i c a t i o n I n fo r m a t i o n  
Figure 33:  
IRQ Output  
Name  
Signal  
Signal Level  
Description  
IRQ  
Digital output  
CMOS  
Interrupt output pin  
FIFO Water Level and FIFO Status Registers  
The AS3911 contains a 96 byte FIFO. In case of transmitting the  
Control logic shifts the data, which was previously loaded by  
the external microcontroller to the Framing Block and further  
to the Transmitter. During reception, the demodulated data is  
stored in the FIFO and the external microcontroller can  
download received data once reception was terminated.  
Transmit and receive capabilities of the AS3911 are not limited  
by the FIFO size due to a FIFO water level interrupt system.  
During transmission an interrupt is sent (IRQ due to FIFO water  
level in the Main Interrupt Register) when the content of data  
in the FIFO passes from (water level + 1) to water level and the  
complete transmit frame has not been loaded in the FIFO yet.  
The external microcontroller can now add more data in the FIFO.  
The same stands for the reception: when the number of  
received bytes passes from (water level - 1) to water level an  
interrupt is sent to inform the external controller that data has  
to be downloaded from FIFO in order not to lose receive data  
due to FIFO overflow.  
During transmission water level IRQ is additionally set in case  
all transmission bytes have not been written in FIFO yet and if  
number of bytes written into FIFIO is lower than water level. In  
this case an IRQ is sent when number of bytes in FIFO drops  
below 4.  
It is important to note that FIFO IRQ is not produced while SPI  
is active in FIFO load or read mode. Due to this the FIFO  
loading/reading rate has to be higher than Tx/Rx bit rate, once  
FIFO loading/reading is finished the /SS pin has to be pulled to  
V
(logic remains in FIFO load/read mode as long as /SS  
DD  
remains low).  
In case controller knows that the receive data frame is smaller  
than the FIFO size the water level interrupt does not have to be  
served. In such case the water level interrupt can be masked.  
The external controller has to serve the FIFO faster than data is  
transmitted or received. Using SCLK frequency which is at least  
double than the actual receive or transmit bit rate is  
recommended.  
There are two settings of the FIFO water level available for  
receive and transmit in the IO Configuration Register 1.  
After data reception is terminated the external microcontroller  
needs to know how much data is still stored in the FIFO: This  
information is available in the FIFO Status Register 1 and FIFO  
Status Register 2 which displays number of bytes in the FIFO  
AS3911 – 46  
ams Datasheet, Confidential: 2013-Oct [2-03]  
Application I nform ation  
which were not read out. FIFO Status Register 1 can also be read  
while reception and transmission processes are active to get  
info about current number of bytes in FIFO. In that case user  
has to take in account that Rx/Tx process is going on and that  
the number of data bytes in FIFO may have already changed by  
the time the reading of register is finished.  
The FIFO Status Register 2 additionally contains two bits which  
indicate that the FIFO was not correctly ser ved during reception  
or transmission process (FIFO overflow and FIFO underflow).  
FIFO overflow is set when too much data is written in FIFO. In  
case this bit is set during reception the external controller did  
not react on time on water level IRQ and more than 96 bytes  
were written in the FIFO. The received data is of course  
corrupted in such a case. During transmission this means that  
controller has written more data than FIFO size. The data to be  
transmitted was corrupted.  
FIFO underflow is set when data was read from empty FIFO. In  
case this bit is set during reception the external controller read  
more data than was actually received. During transmission this  
means that controller has failed to provide the quantity of data  
defined in number of transmitted bytes registers on time.  
Pin MCU_CLK  
Pin MCU_CLK may be used as clock source for the external  
microcontroller. Depending on the operation mode either a low  
frequency clock (32 kHz) from the RC oscillator or the clock  
signal derived from crystal oscillator is available on pin  
MCU_CLK. The MCU_CLK output pin is controlled by bits out_c1,  
out_cl0 and lf_clk_off in the IO Configuration Register 1. Bits  
out_cl enable the use of pin MCU_CLK as clock source and  
define the division for the case the crystal oscillator is running  
(13.56MHz, 6.78MHz and 3.39MHz are available). Bit lf_clk_off  
controls the use of low frequency clock (32kHz) in case the  
crystal oscillator is not running. By default configuration, which  
is defined at power-up, the 3.39MHz clock is selected and the  
low frequency clock is enabled.  
In case the Transparent mode (see “Stream Mode and  
Transparent Mode” on page 137) is used the use of MCU_CLK is  
mandatory since clock which is synchronous to the field carrier  
frequency is needed to implement receive and transmit framing  
in the external controller. The use of MCU_CLK is recommended  
also for the case where the internal framing is used. Using  
MCU_CLK as the microcontroller clock source generates noise  
which is synchronous to the reader carrier frequency and is  
therefore filtered out by the receiver while using some other  
incoherent clock source may produce noise which perturbs the  
reception. Use of MCU_CLK is also better for EMC compliance.  
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 47  
A p p l i c a t i o n I n fo r m a t i o n  
Direct Commands  
Figure 34:  
List of Direct Commands  
Command  
Interrupt  
after  
Termination  
Operation  
Command  
Chaining  
Code  
(hex)  
Command  
Comments  
(1)  
Mode  
Puts the AS3911 in default  
state  
(same as after power-up)  
C1  
C2, C3  
C4  
Set Default  
Clear  
No  
Yes  
Yes  
No  
No  
No  
all  
en  
Stops all activities and  
clears FIFO  
Starts a transmit sequence  
Transmit With CRC using automatic CRC  
generation  
en, tx_en  
Starts a transmit sequence  
Transmit Without  
without automatic CRC  
CRC  
C5  
Yes  
No  
en, tx_en  
generation  
Transmits REQA command  
Transmit REQA  
C6  
C7  
Yes  
Yes  
No  
No  
en, tx_en  
en, tx_en  
(ISO14443A mode only)  
Transmits WUPA command  
Transmit WUPA  
(ISO14443A mode only)  
Performs Initial RF Collision  
NFC Initial Field  
avoidance and switch on  
ON  
(9)  
C8  
C9  
CA  
CB  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
No  
en  
the field  
Performs Response RF  
NFC Response  
(9)  
Collision avoidance and  
Field ON  
en  
switch on the field  
Performs Response RF  
NFC Response  
(9)  
Collision avoidance with  
Field ON with n=0  
en  
n=0 and switch on the field  
Accepted in NFCIP-1 active  
Go to Normal NFC  
communication bit rate  
Mode  
detection mode  
Presets Rx and Tx  
configuration based on  
CC  
D0  
Analog Preset  
state of Mode Definition  
Register and Bit Rate  
Definition Register  
Yes  
Yes  
No  
No  
all  
Mask Receive  
Data  
Receive after this  
command is ignored  
en, rx_en  
AS3911 – 48  
ams Datasheet, Confidential: 2013-Oct [2-03]  
Application I nform ation  
Command  
Interrupt  
after  
Termination  
Operation  
Command  
Chaining  
Code  
(hex)  
Command  
Comments  
(1)  
Mode  
Receive data following this  
command is normally  
processed (this command  
has priority over internal  
mask receive timer)  
Unmask Receive  
Data  
D1  
D2  
D3  
Yes  
No  
en, rx_en  
(see note 2)  
Not used  
Amplitude of signal  
present on RFI inputs is  
measured, result is stored  
in A/D Converter Output  
Register  
Measure  
Amplitude  
No  
No  
No  
No  
Yes  
No  
No  
Yes  
en  
Performs gain reduction  
based on the current noise  
level  
D4  
D5  
D6  
Squelch  
en, rx_en  
Clears the current Squelch  
setting and loads the  
manual gain reduction  
from Receiver  
(10)  
Reset Rx Gain  
Adjust Regulators  
Calibrate  
en  
Configuration Register 4  
Adjusts supply regulators  
according to the current  
supply voltage level  
(5)  
en  
Starts sequence which  
activates the Tx, measures  
the modulation depth and  
D7  
No  
Yes  
en  
Modulation Depth adapts it to comply with  
the specified modulation  
depth  
Starts the sequence to  
adjust parallel  
capacitances connected to  
TRIMx pins so that the  
antenna LC tank is in  
resonance  
D8  
D9  
Calibrate Antenna  
No  
No  
Yes  
Yes  
en  
en  
Measurement of phase  
difference between the  
signal on RFO and RFI  
Measure Phase  
Clear RSSI  
Clears RSSI bits and  
restarts the measurement  
DA  
DC  
DD  
Yes  
No  
No  
No  
No  
Yes  
en  
en  
Transparent Mode Enter in Transparent mode  
Calibrate  
Capacitive Sensor  
Calibrates capacitive  
sensor  
(see note 6)  
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 49  
A p p l i c a t i o n I n fo r m a t i o n  
Command  
Code  
Interrupt  
after  
Termination  
Operation  
Command  
Chaining  
Command  
Comments  
(1)  
Mode  
(hex)  
Measure  
Capacitance  
Performs Capacitor Sensor  
Measurement  
DE  
DF  
E0  
E1  
E2  
E3  
No  
No  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
No  
No  
No  
No  
(see note 7)  
Measure Power  
Supply  
en  
en  
Start General  
Purpose Timer  
Start Wake-up  
Timer  
all  
except wu  
Start Mask-receive  
Timer  
(see note 8)  
en, rx_en  
Start No-response  
Timer  
Other Fx  
Reserved for test  
Not used  
Other codes  
Note(s) and/or Footnote(s):  
1. The ‘Operation Mode’ column in the above table defines which Operation Control Register bits have to be set in order to accept a  
particular command.  
2. Was AD Convert in the AS3910  
3. Called Measure RF in the AS3910  
4. Called Check Antenna Resonance in the AS3910  
5. This command is not accepted in case the external definition of the regulated voltage is selected in the Regulator Voltage Control  
Register (bit reg_s is set to high)  
6. Accepted in all modes in case cs_mcal=0 (Capacitive Sensor Control Register), it is recommended to execute this command in  
Power-down mode  
7. Accepted in all modes, it is recommended to execute this command in Power-down mode.  
8. Accepted only in the Initial NFC Target Mode  
9. After termination of this command I_cat or I_cac IRQ is sent  
10. Called Clear Squelch in the AS3910  
Set Default  
This direct command puts the AS3911 in the same state as  
power-up initialization. All registers are initialized to the default  
state. The only exception are IO Configuration Register 1, IO  
Configuration Register 2 and Operation Control Register which  
are not affected by Set Default command and are only set to  
default state at power-up. Please note that results of different  
calibration and adjust commands are also lost.  
This direct command is accepted in all operating modes. In case  
this command is sent while en (bit 7 of the Operation Control  
Register) is not set FIFO and FIFO Status Registers are not  
cleared.  
Direct command chaining is not allowed since this command  
clears all registers.  
IRQ due to termination of direct command is not produced.  
AS3911 – 50  
ams Datasheet, Confidential: 2013-Oct [2-03]  
Application I nform ation  
Clear  
This direct command stops all current activities (transmission  
or reception), clears FIFO, clears FIFO Status Registers and stops  
all timers except Wake-up timer (in case bit nrt_emv in the  
General Purpose and No-response Timer Control Register is set  
to one, the No-response timer is not stopped). It also clears  
collision and interrupt registers. This command has to be sent  
first in a sequence preparing a transmission before writing data  
to be transmitted in FIFO (except in case of direct commands  
Transmit REQA and Transmit WUPA).  
This command is accepted in case en (bit 7 of the Operation  
Control Register) is set and Xtal oscillator frequency is stable.  
Direct command chaining is possible.  
IRQ due to termination of direct command is not produced.  
Transmit Commands  
All Transmit commands (Transmit With CRC, Transmit Without  
CRC, Transmit REQA and Transmit WUPA) are only accepted in  
case the Transmitter is enabled (bit tx_en is set).  
Before sending commands Transmit With CRC and Transmit  
Without CRC direct command Clear has to be sent, followed by  
definition of number of transmitted bytes and writing data to  
be transmitted in FIFO.  
Direct commands Transmit REQA and Transmit WUPA are used  
to transmit ISO14443A commands REQA and WUPA  
respectively. Sending command Clear before these two  
commands is not necessary.  
Direct command chaining is possible.  
IRQ due to termination of direct command is not produced.  
NFC Field ON Commands  
These commands are used to perform the RF collision  
avoidance and switch the field on in case no collision was  
detected. The Collision avoidance threshold defined in the  
External Field Detector Threshold Register is used to observe  
the RF_IN inputs and to determine whether there is some other  
device, which is emitting the 13.56 MHz field, present close to  
the AS3911 antenna. In case collision is not detected the reader  
field is switched on automatically (bit tx_en in the Operation  
Control Register is set) and an IRQ with I_cat flag in Timer and  
NFC Interrupt Register is sent after minimum guard time  
defined by the NFCIP-1 standard to inform the controller that  
message transmission using a Transmit command can be  
initiated.  
In case a presence of external field is detected an IRQ with I_cac  
flag is sent. In such case a transmission cannot be performed,  
NFC Field ON command has to be repeated as long as collision  
is not detected any more.  
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 51  
A p p l i c a t i o n I n fo r m a t i o n  
Command NFC Initial Field ON performs Initial Collision  
Avoidance according to NFCIP-1 standard; number n is defined  
by bits nfc_n1 and nfc_n0 in Auxiliary Definition Register.  
Command NFC Response Field ON performs Response Collision  
Avoidance according to NFCIP-1 standard; number n is defined  
by bits nfc_n1 and nfc_n0 in Auxiliary Definition Register.  
Command NFC Response Field ON with n=0, performs  
Response Collision Avoidance where n is 0.  
Implemented active delay time is on lower NFCIP-1  
specification limit, since the actual active delay time will also  
include detection of the field deactivation, controller  
processing delay and sending the NFC Field ON command.  
Figure 35:  
Direct Command NFC Initial Field ON  
RF On  
TRFW  
Start  
TIRFG  
TIDT  
n x TRFW  
Figure 36:  
Direct Command NFC Response Field ON  
RF On  
TRFW  
Start  
TARFG  
TADT  
n x TRFW  
AS3911 – 52  
ams Datasheet, Confidential: 2013-Oct [2-03]  
Application I nform ation  
Figure 37:  
Timing Parameters of NFC Field ON Commands  
Symbol  
Parameter  
Initial delay time  
RF waiting time  
Initial guard time  
Active delay time  
Active guard time  
Value  
4096  
512  
Unit  
/fc  
Note  
T
NFC Initial Field ON  
IDT  
T
T
/fc  
RWF  
IRFG  
>5  
ms  
/fc  
NFC Initial Field ON  
T
768  
NFC Response Field ON  
NFC Response Field ON  
ADT  
T
1024  
/fc  
ARFG  
This command is accepted in case en (bit 7 of the Operation  
Control Register) is set and Xtal oscillator frequency is stable.  
Go to Normal NFC Mode  
This command is used to transition from NFC target bit rate  
detection mode to normal mode. Additionally it copies the  
content of the NFCIP Bit Rate Detection Display Register to the  
Bit Rate Definition Register and correctly sets the bit tr_am in  
the Auxiliary Definition Register.  
Analog Preset  
This command is used to preset Receiver and Transmitter  
configuration based on state of Bit Rate Definition Register and  
Bit Rate Definition Register. Please note that no preset is done  
in case Sub-carrier bits Stream or BPSK bit stream mode is  
selected. The list of configuration bits that are preset is given  
in Figure 38.  
Figure 38:  
Register Preset Bits  
Bit Bit Name  
Function  
Address 02 : Operation Control Register  
h
5
3
rx_chn  
tx_en  
1: one channel enabled NFCIP-1 active communication (both initiator and target)  
0: disable TX operation NFCIP-1 active communication (both initiator and target)  
Note: In case of any target mode or NFCIP-1 initiator mode bit tx_en is set to 0 to disable transmitter in case it  
was enabled. In NFCIP-1 mode the switching on of the transmitter field is controlled by dedicated  
commands.  
Address 05 : ISO14443A and NFC 106kb/s Settings Register  
h
1: Add SB (F0) and LEN byte during Tx and skip SB (F0) byte during TX NFCIP-1 active  
communication (both initiator and target)  
5
nfc_f0  
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 53  
A p p l i c a t i o n I n fo r m a t i o n  
Bit Bit Name  
Function  
Address 09 : Auxiliary Definition Register  
h
Tx Modulation type (depends on mode definition and Tx bit rate)  
0: OOK ISO144443A, NFCIP-1 106 kb/s (both initiator and target), NFC Forum Type 1  
5
4
tr_am  
en_fd  
Tag  
1: AM ISO144443B, FeliCa, NFCIP-1 212 kb/s and 424 kb/s  
Enable External Field Detector with Peer Detection threshold  
0: All modes except NFCIP-1 active communication  
1: NFCIP-1 active communication (both initiator and target)  
Address 0A : Receiver Configuration Register 1  
h
7
6
ch_sel  
0: Enable AM channel NFCIP-1 active communication (both initiator and target)  
AM demodulator select (depend on Rx bit rate)  
0: Peak detector All Rx bit rates equal or below fc/16 (848 kb/s)  
1: Mixer All VHBR Rx bit rates (fc/8 and fc/4)  
amd_sel  
5
4
3
2
1
0
lp2  
lp1  
Low pass control (depends on mode definition and Rx bit rate)  
(see Figure 15)  
lp0  
h200  
h80  
z12k  
First and third stage zero setting (depends on mode definition and Rx bit rate)  
(see Figure 15)  
Address 0C : Receiver Configuration Register 3  
h
st  
nd  
Clip output of 1 and 2 stage  
1
0
lim  
0: All modes except NFCIP-1 active communication  
1: NFCIP-1 active communication (both initiator and target)  
nd  
rd  
Forces gain reduction in 2 and 3 gain stage  
rg_nfc  
0: All modes except NFCIP-1 active communication  
1: NFCIP-1 active communication (both initiator and target)  
Mask Receive Data and Unmask Receive Data  
After the direct command Mask Receive Data the signal rx_on,  
which enables the RSSI and AGC operation of the Receiver (see  
also Receiver) is forced to low, processing of the receiver output  
by the receive data framing block is disabled. This command is  
useful to mask receiver and receive framing from processing  
the data when there is actually no input and only a noise would  
be processed (for example in case where a transponder  
processing time after receiving a command from the reader is  
long). Masking of receive is also possible using Mask Receive  
Timer. Actual masking is a logical or of the two mask receive  
processes.  
AS3911 – 54  
ams Datasheet, Confidential: 2013-Oct [2-03]  
Application I nform ation  
The direct command Unmask Receive Data is enabling normal  
processing of the received data (signal rx_on is set high to  
enable the RSSI and AGC operation), the receive data framing  
block is enabled. A common use of this command is to enable  
again the receiver operation after it was masked by the  
command Mask Receive Data. In case Mask Receive Timer is  
running while command Unmask Receive Data is received,  
reception is enabled, Mask Receive Timer is reset.  
The commands Mask Receive Data and Unmask Receive Data  
are only accepted when the Receiver is enabled (bit rx_en is set).  
Direct command chaining is possible.  
IRQ due to termination of direct command is not produced.  
Measure Amplitude  
This command measures the amplitude on the RFI inputs and  
stores result in the A/D Converter Output Register.  
When this command is executed the Transmitter and Amplitude  
Detector are enabled, the output of the Amplitude Detector is  
multiplexed to the A/D Converter input (the A/D Converter is  
in absolute mode). The Amplitude Detector conversion gain is  
0.6 V  
/ V  
. One LSB of the A/D converter output represents  
INPP OUT  
13.02 mV on the RFI inputs. A 3 V signal, which is maximum  
pp  
pp  
allowed level on each of the two RFI inputs, results in 1.8 V  
output DC voltage and would produce a value of 1110 0110b  
on the A/D converter output.  
Duration time: 25 μs max.  
This command is accepted in case en (bit 7 of the Operation  
Control Register) is set and Xtal oscillator frequency is stable.  
Direct command chaining is not possible.  
IRQ due to termination of direct command is produced after  
command execution is terminated.  
Squelch  
This direct command is intended to avoid demodulation  
problems of transponders which produce a lot of noise during  
data processing. It can also be used in a noisy environment. The  
operation of this command is explained in “Squelch” on  
page 22.  
Duration time: 500 μs max.  
This command is only accepted when the Transmitter and the  
Receiver are operating. Command is actually executed only in  
case signal rx_on is low.  
Direct command chaining is not possible.  
IRQ due to termination of direct command is not produced.  
Reset Rx Gain  
This command initializes the AGC, Squelch and RSSI block.  
Sending this command stops a squelch process in case it is  
going on, clears the current Squelch setting and loads the  
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 55  
A p p l i c a t i o n I n fo r m a t i o n  
manual gain reduction from Receiver Configuration Register 4.  
This command is accepted in case en (bit 7 of the Operation  
Control Register) is set and Xtal oscillator frequency is stable.  
Direct command chaining is possible.  
IRQ due to termination of direct command is not produced.  
Adjust Regulators  
When this command is sent the power supply level of V is  
DD  
measured in maximum load conditions and the regulated  
voltage reference is set 250 mV below this measured level to  
assure maximum possible stable regulated supply (See “Power  
Supply System” on page 34.). Using this command increases the  
system PSSR.  
At the beginning of execution of this command, both the  
receiver and transmitter are switched on to have the maximum  
current consumption, the regulators are set to the maximum  
regulated voltage (5.1 V in case of 5 V supply and 3.4 V in case  
of 3.3 V supply mode). After 300 μs VSP_RF is compared to V  
,
DD  
in case VSP_RF is not at least 250 mV lower the regulator setting  
is reduced for one step (120 mV in case of 5 V supply and 100  
mV in case of 3.3 V supply mode) and measurement is done after  
next 300 μs. Procedure is repeated until VSP_RF drops at least  
250 mV below V or until minimum regulated voltage (3.9 V  
DD  
in case of 5 V supply and 2.4 V in case of 3.3 V supply mode) is  
reached.  
Duration time: 5 ms max.  
This command is accepted in case en (bit 7 of the Operation  
Control Register) is set and Xtal oscillator frequency is stable.  
This command is not accepted in case the external definition  
of the regulated voltage is selected in the Regulator Voltage  
Control Register (bit reg_s is set to H)  
Direct command chaining is not possible.  
IRQ due to termination of direct command is produced after  
command execution is terminated.  
Calibrate Modulation Depth  
Starts a patent pending sequence, which activates the  
transmission, measures the modulation depth and adapts it to  
comply with the modulation depth specified in the AM  
Modulation Depth Control Register. When calibration  
procedure is finished result is displayed in the AM Modulation  
Depth Display Register. Please refer to See “AM Modulation  
Depth: Definition and Calibration” on page 132. for details  
about setting the AM modulation depth and running this  
command.  
Duration time: 275μs max.  
This command is accepted in case en (bit 7 of the Operation  
Control Register) is set and Xtal oscillator frequency is stable.  
Direct command chaining is not possible.  
AS3911 – 56  
ams Datasheet, Confidential: 2013-Oct [2-03]  
Application I nform ation  
IRQ due to termination of direct command is produced after  
command execution is terminated.  
Calibrate Antenna  
Sending this command starts a sequence which adjusts the  
parallel capacitances connected to TRIMx pins so that the  
antenna LC tank is in resonance. See Antenna Tuning for details.  
Duration time: 250 μs max.  
This command is accepted in case en (bit 7 of the Operation  
Control Register) is set and Xtal oscillator frequency is stable.  
Measure Phase  
This command measures the phase difference between the  
signals on the RFO outputs and the signals on the RFI inputs  
and stores the result in the A/D Converter Output Register.  
During execution of the direct command Measure Phase the  
Transmitter and Phase Detector are enabled, the Phase  
Detector output is multiplexed on the input of A/ D converter,  
which is set in relative mode. Since the A/D converter range is  
from 1/6 VSP_A to 5/6 VSP_A the actual phase detector range  
is from 30º to 150º. Values below 30º result in FF while values  
h
above 150º result in 00 . 1 LSB of the A/D conversion output  
h
represents 0.13% of carrier frequency period (0.468°). The result  
of A/D conversion is in case of 90º phase shift in the middle of  
range (1000 0000b or 0111 1111b). Value higher than 1000  
0000b means that phase detector output voltage is higher than  
VSP_A/2, which corresponds to case with phase shift lower than  
90º. In the opposite case, when the phase shift is higher than  
90º, the result of A/D conversion is lower than 0111 1111b. For  
example, the phase difference of 135º depicted in Figure 18  
results in 0.75 VSP_A, result stored in A/D converter is 31 (1F ).  
d
h
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 57  
A p p l i c a t i o n I n fo r m a t i o n  
The phase measurement result can be calculating using the  
following formulas:  
0 φ 30 : result  
30 < φ < 150 : result  
150 φ 180 : result  
[
dec  
dec  
dec  
]
= 255  
1 {(  
= 0  
[
]
=
(
φ
[deg  
]
/180 1/ 6  
* 3 / 2)}* 255  
) ( )  
[
]
Duration time: 25 μs max.  
This command is accepted in case en (bit 7 of the Operation  
Control Register) is set and Xtal oscillator frequency is stable.  
Direct command chaining is not possible.  
IRQ due to termination of direct command is produced after  
command execution is terminated.  
Clear RSSI  
The Receiver automatically clears the RSSI bits in the Receiver  
State Display Register and starts to measure the RSSI of the  
received signal when the signal rx_on is asserted. Since the RSSI  
bits store peak value (peak-hold type) eventual variation of the  
receiver input signal will not be followed (this may happen in  
case of long message or test procedure). The direct command  
Clear RSSI clears the RSSI bits in the Receiver State Display  
Register, the RSSI measurement is restarted (in case of course  
rx_on is still high).  
This command is accepted in case en (bit 7 of the Operation  
Control Register) is set and Xtal oscillator frequency is stable.  
Direct command chaining is possible.  
IRQ due to termination of direct command is not produced.  
Transparent Mode  
Enter in the Transparent mode. The Transparent mode is  
entered on the rising edge of signal /SS and is maintained as  
long as signal /SS is kept high. See “Transparent Mode” on  
page 58 for more details.  
This command is accepted in case en (bit 7 of the Operation  
Control Register) is set and Xtal oscillator frequency is stable.  
Calibrate Capacitive Sensor  
This command calibrates the Capacitive Sensor. See “Capacitive  
Sensor” on page 14 for more details.  
Duration time: 3 ms max.  
This command is executed in case capacitive sensor automatic  
calibration mode is set (all bits cs_mcal in the Capacitive Sensor  
Control Registerare set to 0). In order to avoid interference with  
Xtal oscillator and reader magnetic field it strongly  
recommended to use this command in Power-down mode only.  
Direct command chaining is not possible.  
IRQ due to termination of direct command is produced after  
command execution is terminated.  
AS3911 – 58  
ams Datasheet, Confidential: 2013-Oct [2-03]  
Application I nform ation  
Measure Capacitance  
This command performs the capacitance measurement. See  
“Capacitive Sensor” on page 14 for more details.  
Duration time: 250 μs max.  
In order to avoid interference with Xtal oscillator and reader  
magnetic field it strongly recommended to use this command  
in Power-down mode only.  
Direct command chaining is not possible.  
IRQ due to termination of direct command is produced after  
command execution is terminated.  
Measure Power Supply  
This command performs the power supply measurement.  
Configuration bits mpsv1 and mpsv0 of the Regulator Voltage  
Control Register define which power supply is measured (V  
,
DD  
VSP_A, VSP_D and VSP_RF can be measured). Result of  
measurement is stored in the A/D Converter Output Register.  
During the measurement the selected supply input is  
connected to a 1/3 resistive divider output of which is  
multiplexed to A/D converter in absolute mode. Due to 1/3  
division one LSB represents 23.438 mV.  
Duration time: 25 μs max.  
This command is accepted in case en (bit 7 of the Operation  
Control Register) is set and Xtal oscillator frequency is stable.  
Direct command chaining is not possible.  
IRQ due to termination of direct command is produced after  
command execution is terminated.  
Start Timers  
See “Timers” on page 29.  
Registers  
The 6-bit register addresses below are defined in the  
hexadecimal notation. The possible address range is from 00  
h
to 3F .  
h
There are two types of registers implemented in the AS3911:  
configuration registers and display registers. The configuration  
registers are used to configure the AS3911. They can be written  
and read through the SPI (RW). The display registers are read  
only (RO); they contain information about the AS3911 internal  
state.  
Registries are set to their default state at power-up and after  
sending direct command Set Default. The only exceptions are  
the IO Configuration Register 1 and the IO Configuration  
Register 2 which are only set to default state at power-up.  
Configuration bits of these two registries are related to  
hardware configuration which is in most cases not going to  
change during the operation.  
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 59  
A p p l i c a t i o n I n fo r m a t i o n  
Figure 39:  
Register Description  
Address[hex]  
Content  
Comment  
Type  
IO Configuration Registers  
00  
01  
IO Configuration Register 1  
IO Configuration Register 2  
RW  
RW  
Set to default state only at  
power-up  
Operation Control and Mode Definition Registers  
Set to default state only at  
power-up  
02  
Operation Control Register  
RW  
RW  
RW  
03  
04  
Mode Definition Register  
Bit Rate Definition Register  
Configuration Registers  
ISO14443A and NFC 106kb/s Settings  
Register  
05  
06  
07  
08  
09  
0A  
0B  
0C  
0D  
ISO14443B Settings Register 1  
ISO14443B and FeliCa Settings Register  
Stream Mode Definition Register  
Auxiliary Definition Register  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
Receiver Configuration Register 1  
Receiver Configuration Register 2  
Receiver Configuration Register 3  
Receiver Configuration Register 4  
Timer Definition Registers  
0E  
0F  
10  
Mask Receive Timer Register  
No-response Timer Register 1  
No-response Timer Register 2  
RW  
RW  
RW  
General Purpose and No-response Timer  
Control Register  
11  
RW  
12  
13  
General Purpose Timer Register 1  
General Purpose Timer Register 2  
RW  
RW  
Interrupt and Associated Reporting Registers  
14  
15  
Mask Main Interrupt Register  
RW  
RW  
Mask Timer and NFC Interrupt Register  
AS3911 – 60  
ams Datasheet, Confidential: 2013-Oct [2-03]  
Application I nform ation  
Address[hex]  
Content  
Comment  
Type  
16  
17  
18  
19  
1A  
1B  
1C  
Mask Error and Wake-up Interrupt Register  
Main Interrupt Register  
RW  
R
Timer and NFC Interrupt Register  
Error and Wake-up Interrupt Register  
FIFO Status Register 1  
R
R
R
FIFO Status Register 2  
R
Collision Display Register  
R
Definition of Number of Transmitted Bytes  
1D  
1E  
Number of Transmitted Bytes Register 1  
Number of Transmitted Bytes Register 2  
RW  
RW  
NFCIP Bit Rate Detection Display Register  
1F  
20  
NFCIP Bit Rate Detection Display Register  
A/D Converter Output Register  
R
R
A/D Converter Output Register  
Antenna Calibration Registers  
21  
22  
23  
Antenna Calibration Control Register  
Antenna Calibration Target Register  
Antenna Calibration Display Register  
RW  
RW  
R
AM Modulation Depth and Antenna Driver Registers  
AM Modulation Depth Control Register  
24  
25  
RW  
R
AM Modulation Depth Display Register  
RFO AM Modulated Level Definition  
Register  
26  
27  
RW  
RW  
RFO Normal Level Definition Register  
External Field Detector Threshold Registers  
External Field Detector Threshold Register  
Regulator Registers  
29  
RW  
2A  
2B  
Regulator Voltage Control Register  
Regulator and Timer Display Register  
RW  
R
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 61  
A p p l i c a t i o n I n fo r m a t i o n  
Address[hex]  
Content  
Comment  
Type  
Receiver State Display Registers  
2C  
2D  
RSSI Display Register  
Gain Reduction State Register  
Capacitive Sensor Registers  
R
R
2E  
2F  
Capacitive Sensor Control Register  
Capacitive Sensor Display Register  
RW  
R
Auxiliary Display Register  
Auxiliary Display Register  
30  
R
Wake-up Registers  
31  
32  
Wake-up Timer Control Register  
RW  
RW  
Amplitude Measurement Configuration  
Register  
Amplitude Measurement Reference  
Register  
33  
34  
RW  
R
Amplitude Measurement Auto-averaging  
Display Register  
35  
36  
37  
Amplitude Measurement Display Register  
Phase Measurement Configuration Register  
Phase Measurement Reference Register  
R
RW  
RW  
Phase Measurement Auto-averaging  
Display Register  
38  
39  
3A  
R
R
Phase Measurement Display Register  
Capacitance Measurement Configuration  
Register  
RW  
Capacitance Measurement Reference  
Register  
3B  
RW  
Capacitance Measurement Auto-averaging  
Display Register  
3C  
3D  
R
R
Capacitance Measurement Display Register  
IC Identity Register  
3F  
IC Identity Register  
R
AS3911 – 62  
ams Datasheet, Confidential: 2013-Oct [2-03]  
Application I nform ation  
IO Configuration Register 1  
Figure 40:  
IO Configuration Register 1  
Address 00h: IO Configuration Register 1  
Type: RW  
Bit  
Name  
Default  
Function  
Comments  
1: Only one RFO driver will be  
used  
Choose between single and  
differential driving of antenna  
7
single  
0
Choose which output driver and  
which input will be used in case of  
single driving  
0: RFO1, RFI1  
1: RFO2, RFI2  
6
rfo2  
0
0: 64  
1: 80  
5
4
fifo_lr  
fifo_lt  
0
0
FIFO water level for receive  
FIFO water level for transmit  
0: 32  
1: 16  
Selector for crystal oscillator  
Use of VHBR is only possible with  
27.12 MHz Xtal  
0: 13.56 MHz Xtal  
1: 27.12 MHz Xtal  
3
2
osc  
1
0
out_cl out_cl MCU_CL  
1
0
0
1
1
0
0
1
0
1
K
Selection of clock frequency on  
MCU_CLK output in case Xtal  
oscillator is running. In case of “11”  
MCU_CLK output is permanently  
low.  
out_cl1  
3.39 MHZ  
6.78 MHZ  
13.56 MHZ  
disabled  
1
0
out_cl0  
0
0
By default the 32 kHz LF clock is  
present on MCU_CLK output when  
Xtal oscillator is not running and  
the MCU_CLK output is not  
disabled.  
lf_clk_off  
1: No LF clock on MCU_CLK  
Note: Default setting is set at power-up only.  
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 63  
A p p l i c a t i o n I n fo r m a t i o n  
IO Configuration Register 2  
Figure 41:  
IO Configuration Register 2  
Address 01h: IO Configuration Register 2  
Type: RW  
Bit  
Name  
Default  
Function  
Comments  
5 V supply, range: 4.1 V to 5.5  
0: 5 V supply  
1: 3.3 V supply  
V
7
sup3 V  
0
3.3 V supply, range: 2.4 V to  
3.6 V  
Used for low cost  
applications. When this bit is  
set:  
At 3 V or 5 V supply VSP_D  
and VSP_A shall be shorted  
externally  
At 3.3 V applications VSP_D  
can alternatively be supplied  
6
vspd_off  
0
1: Disable VSP_D regulator  
from V in case VSP_A is not  
DD  
more than 300 mV lower then  
V
DD  
5
4
3
2
Not used  
1: Pull-down on MISO, when /SS is low  
and MISO is not driven by the AS3911  
miso_pd2  
miso_pd1  
io_18  
0
0
0
1: Pull-down on MISO when /SS is high  
1: Increase MISO driving level in case  
of 1.8 V V  
DD_IO  
1
0
Not used  
slow_up  
0
1: Slow ramp at Tx on  
10μs 10% to 90%, for B  
Note: Default setting is set at power-up only.  
AS3911 – 64  
ams Datasheet, Confidential: 2013-Oct [2-03]  
Application I nform ation  
Operation Control Register  
Figure 42:  
Operation Control Register  
Address 02h: Operation Control Register  
Type: RW  
Bit  
7
Name  
en  
Default  
Function  
Comments  
1: Enables oscillator and  
regulator (Ready mode)  
0
0
6
rx_en  
1: Enables Rx operation  
In case only one Rx channel is  
enabled, selection is done by  
the Receiver Configuration  
Register 1 bit ch_sel  
0: Both, AM and PM, channels  
enabled  
1: One channel enabled  
5
4
rx_chn  
0
In case both Rx channels are  
enabled, it chooses the method  
of channel selection, manual  
selection is done by the  
0: Automatic channel selection  
1: Manual channel selection  
rx_man  
0
Receiver Configuration  
Register 1 bit ch_sel  
This bit is automatically set by  
NFC Field ON commands and  
reset in NFC active  
communication modes after  
transmission is finished  
3
2
tx_en  
wu  
0
0
1: Enables Tx operation  
According to settings in  
Wake-up Timer Control  
Register  
1: Enables Wake-up mode  
1
0
Not used  
Note: Default setting is set at power-up only.  
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 65  
A p p l i c a t i o n I n fo r m a t i o n  
Mode Definition Register  
Figure 43:  
Mode Definition Register  
Address 03h: Mode Definition Register  
Type: RW  
Bit  
Name  
Default  
Function  
Comments  
0: Initiator  
1: Target  
7
targ  
0
6
5
4
3
2
1
om3  
om2  
om1  
om0  
0
0
0
1
0
0
Refer to Initiator Operation  
Modes and Target Operation  
Modes  
Selection of operation mode.  
Different for initiator and  
target mode.  
Automatic start of Response  
RF Collision Avoidance  
sequence  
0
nfc_ar  
0
Note: Default setting is set at power-up and after Set Default command.  
Figure 44:  
Initiator Operation Modes  
Initiator Operation Modes  
om3  
om2  
om1  
om0  
Comment  
0
0
0
0
0
1
1
0
0
0
0
1
1
1
0
0
1
1
0
1
1
0
1
0
1
0
0
1
NFCIP-1 active communication  
ISO14443A  
ISO14443B  
FeliCa  
NFC Forum Type 1 Tag (Topaz)  
Sub-carrier stream mode  
BPSK stream mode  
Not used  
Other combinations  
Note: In case an operation mode which is not supported is selected, the Tx/Rx operation is disabled.  
AS3911 – 66  
ams Datasheet, Confidential: 2013-Oct [2-03]  
Application I nform ation  
Figure 45:  
Target Operation Modes  
Target Operation Modes  
om0 Comment  
om3  
om2  
om1  
0
0
0
0
0
0
0
1
NFCIP-1 active communication, bit rate detection mode  
NFCIP-1 active communication, normal mode  
Not used  
Other combinations  
Note: In case an operation mode which is not supported is selected, the Tx/Rx operation is disabled.  
Bit Rate Definition Register  
Figure 46:  
Bit Rate Definition Register  
Address 04h: Bit Rate Definition Register  
Type: RW  
Bit  
7
Name  
tx_rate3  
tx_rate2  
tx_rate1  
tx_rate0  
rx_rate3  
rx_rate2  
rx_rate1  
rx_rate0  
Default  
Function  
Comments  
0
0
0
0
0
0
0
0
6
Selects bit rate for Tx  
5
4
Refer to Bit Rate Coding  
3
Selects bit rate for Rx in case  
selected protocol allows  
different bit rates for Rx and Tx  
2
1
0
Note(s) and/or Footnote(s):  
1. Default setting is set at power-up and after Set Default command.  
2. Automatically loaded by direct command Go to Normal NFC Mode.  
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 67  
A p p l i c a t i o n I n fo r m a t i o n  
Figure 47:  
Bit Rate Coding  
Bit Rate Coding  
rate3  
rate2  
rate1  
rate0 Bit rate [kbit/s]  
Comment  
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
fc/128 (~106)  
fc/64 (~212)  
fc/32 (~424)  
fc/16 (~848)  
fc/8 (~1695)  
fc/4 (~3390)  
fc/2 (~6780)  
VHBR Tx is supported only for ISO14443B  
mode  
VHBR Rx is supported only for fc/8 and fc/4  
Other combinations  
Not used  
Note: In case a bit rate which is not supported is selected, the Tx/Rx operation is disabled.  
ISO14443A and NFC 106kb/s Settings Register  
Figure 48:  
ISO14443A and NFC 106kb/s Settings Register  
Address 05h: ISO14443A and NFC 106kb/s  
Settings Register  
Type: RW  
Bit  
Name  
Default  
Function  
Comments  
1: No parity bit is  
generated during Tx  
Data stream is taken from FIFO, transmit has to be  
done using command Transmit Without CRC  
7
no_tx_par  
0
1: Receive without  
parity and CRC  
When set to 1 received bit stream is put in the  
FIFO, no parity and CRC detection is done  
6
5
no_rx_par  
nfc_f0  
0
0
1: Support of NFCIP-1  
Transport Frame format (F0) byte during Rx  
Add SB (F0) and LEN bytes during Tx and skip SB  
4
3
2
1
p_len3  
p_len2  
p_len1  
p_len0  
0
0
0
0
Refer to ISO14443A  
Modulation Pulse  
Width  
Modulation pulse width; defined in number of  
13.56 MHz clock periods.  
1: ISO14443  
anticollision frame  
Has to be set to 1 when ISO14443A bit oriented  
anticollision frame is sent  
0
antcl  
0
Note: Default setting is set at power-up and after Set Default command.  
AS3911 – 68  
ams Datasheet, Confidential: 2013-Oct [2-03]  
Application I nform ation  
Figure 49:  
ISO14443A Modulation Pulse Width  
ISO14443A Modulation Pulse Width  
Pulse width in number of 1/fc for different bit rates  
p_len3 p_len2 p_len1 p_len0  
fc/128  
42  
fc/64  
fc/32  
fc/16  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
41  
20  
21  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
40  
39  
13  
12  
11  
10  
9
38  
8
7
6
5
4
3
2
37  
36  
35  
34  
8
33  
7
32  
6
31  
5
30  
29  
28  
27  
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 69  
A p p l i c a t i o n I n fo r m a t i o n  
ISO14443B Settings Register 1  
Figure 50:  
ISO14443B Settings Register  
Address 06h: ISO14443B Settings Register 1  
Type: RW  
Bit  
Name  
Default  
Function  
Comments  
Number  
of EGT  
egt2 egt1 egt0  
7
egt2  
0
0
0
0
0
0
1
0
1
EGT time defined in number of  
etu  
6
5
egt1  
egt0  
0
0
.
.
.
.
.
.
.
.
1
1
1
1
0
1
6
6
SOF, number of etu with logic 0  
(10 or 11)  
4
3
2
1
sof_0  
sof_1  
eof  
0
0
0
0 10 etu, 1 11 etu  
0 2 etu, 1 3 etu  
SOF, number of etu with logic 1  
(2 or 3)  
EOF, number of etu with logic 0  
(10 or 11)  
0 10 etu, 1 11 etu  
1: SOF 10.5, 2.5, EOF: 10.5  
Sets SOF and EOF settings in  
middle of specification  
half  
SOF= fixed to 10 low - 2 high,  
EOF not defined, put in FIFO  
0
rx_st_om  
1: Start/stop bit omission for Rx  
(2)  
last full byte  
Note(s) and/or Footnote(s):  
1. Default setting is set at power-up and after Set Default command.  
2. Start/stop bit omission for Tx can be implemented by using Stream mode.  
AS3911 – 70  
ams Datasheet, Confidential: 2013-Oct [2-03]  
Application I nform ation  
ISO14443B and FeliCa Settings Register  
Figure 51:  
ISO14443B and FeliCa Settings Register  
Address 07h: ISO14443B and FeliCa Settings Register  
Type: RW  
Bit  
7
Name  
tr1_1  
Default  
Function  
Comments  
0
0
Refer to Minimum TR1  
Coding  
6
tr1_0  
According to ISO14443-3 chapter  
7.10.3.3  
5
4
3
no_sof  
no_eof  
eof_12  
0
0
0
1: No SOF PICC to PCD  
1: No EOF PICC to PCD  
Support of B’  
According to ISO14443-3 chapter  
7.10.3.3  
0: PICC EOF 10 to 11 etu  
1: PICC EOF 10 to 12 etu  
(2)  
Support of B’  
1: Increased tolerance of  
phase change detection  
2
1
phc_th  
f_p1  
0
0
00: 48  
01: 64  
10: 80  
11: 96  
FeliCa preamble length (valid  
also for NFCIP-1 active  
communication bit rates 242 and  
484 kb/s)  
0
f_p0  
0
Note(s) and/or Footnote(s):  
1. Default setting is set at power-up and after Set Default command.  
2. Detection of EOF requires larger tolerance range for bit rates with only one sub-carrier frequency period per bit (fc/16 and higher).  
Due to this it is not possible to distinguish between EOF with 11 and 12 etu and setting this bit has no impact on EOF detection.  
Figure 52:  
Minimum TR1 Codings  
Minimum TR1 Coding  
Minimum TR1 for a PICC to PCD Bit Rate  
tr1_1  
tr1_0  
fc / 128  
80 / fs  
> fc / 128  
80 / fs  
0
0
1
1
0
1
0
1
64 / fs  
32 / fs  
Not used  
Not used  
Not used  
Not used  
Note: TR1 is defined in number of sub-carrier cycles, therefore at VHBR the absolute time becomes shorter.  
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 71  
A p p l i c a t i o n I n fo r m a t i o n  
Stream Mode Definition Register  
Figure 53:  
Stream Mode Definition Register  
Address 08h: Stream Mode Definition Register  
Type: RW  
Bit  
7
Name  
Default  
Function  
Comments  
0
0
0
6
scf1  
scf0  
Refer to Sub-carrier Frequency  
Definition for Sub-carrier and  
BPSK Stream Mode  
Sub-carrier frequency definition  
for Sub-carrier and BPSK stream  
mode  
5
4
scp1  
0
Number of sub-carrier pulses in  
report period for Sub-carrier and  
BPSK stream mode  
number of  
scp1 scp0  
pulses  
0
0
1
1
0
1
0
1
1 (BPSK only)  
2
4
8
3
scp0  
0
2
1
0
stx2  
stx1  
stx0  
0
0
Refer to Definition of Time  
Period for Stream Mode Tx  
Modulator Control  
Definition of time period for Tx  
modulator control (for  
Sub-carrier and BPSK stream  
mode)  
Note: Default setting is set at power-up and after Set Default command.  
Figure 54:  
Sub-carrier Frequency Definition for Sub-carrier and BPSK Stream Mode  
Sub-carrier Frequency Definition for Sub-carrier and BPSK Stream Mode  
scf1  
scf0  
Sub-carrier Mode  
fc/64 (212 kHz)  
fc/32 (424 kHz)  
fc/16 (848 kHz)  
fc/8 (1695 kHz)  
BPSK Mode  
fc/16 (848 kHz)  
fc/8 (1695 kHz)  
fc/4 (3390 kHz)  
Not used  
0
0
1
1
0
1
0
1
AS3911 – 72  
ams Datasheet, Confidential: 2013-Oct [2-03]  
Application I nform ation  
Figure 55:  
Definition of Time Period for Stream Mode Tx Modulator Control  
Definition of Time Period for Stream Mode Tx Modulator Control  
stx2  
stx1  
stx0  
Time Period  
fc/128 (106 kHz)  
fc/64 (212 kHz)  
fc/32 (424 kHz)  
fc/16 (848 kHz)  
fc/8 (1695 kHz)  
fc/4 (3390 kHz)  
fc/2(6780 kHz)  
not used  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 73  
A p p l i c a t i o n I n fo r m a t i o n  
Auxiliary Definition Register  
Figure 56:  
Auxiliary Definition Register  
Address 09h: Auxiliary Definition Register  
Type: RW  
Bit  
Name  
Default  
Function  
Comments  
Valid for all protocols, for  
ISO14443A REQA, WUPA and  
7
no_crc_rx  
0
1: Receive without CRC  
anticollision receive without CRC  
(2)  
is done automatically  
1: Make CRC check, but put  
CRC bytes in FIFO and add  
them to number of receive  
bytes  
6
5
crc_2_fifo  
tr_am  
0
0
Needed for EMV compliance  
Set automatically by command  
Analog Preset, can be modified  
by register write, has to be  
0: OOK, 1: AM  
defined for transparent and bit  
(3)  
stream mode Tx  
External Field Detector with Peer  
Detection threshold is activated.  
Preset for NFCIP-1 active  
1: Enable External Field  
Detector  
4
3
en_fd  
0
0
communication mode  
1: Puts RFO driver in  
three-state during OOK  
modulation  
Valid for all protocols using OOK  
modulation (also in Transparent  
mode)  
ook_hr  
1: BPSK fc/32: more tolerant  
BPSK decoder for bit rate fc/32,  
ISO14443A fc/128, NFCIP-1  
fc/128: more tolerant  
2
rx_tol  
1
processing of first byte  
1
0
nfc_n1  
nfc_n0  
0
0
Definition on n for direct  
commands NFC Initial Field ON  
and NFC Response Field ON  
Note(s) and/or Footnote(s):  
1. Default setting is set at power-up and after Set Default command.  
2. Receive without CRC is done automatically in case REQA and WUPA commands are sent using direct commands Transmits REQA  
command and Transmits WUPA command, respectively, and in case anticollision is performed by setting bit antcl.  
3. Automatic preset of the tr_am  
4. 0: OOK ® ISO144443A, NFCIP-1 106 kb/s, NFC Forum Type 1 Tag  
5. 1: AM ® ISO144443B, FeliCa, NFCIP-1 212 and 424 kb/s  
AS3911 – 74  
ams Datasheet, Confidential: 2013-Oct [2-03]  
Application I nform ation  
Receiver Configuration Register 1  
Figure 57:  
Receiver Configuration Register 1  
Address 0Ah: Receiver Configuration Register 1 (Filter  
and Demodulator Settings)  
Type: RW  
Bit  
Name  
Default  
Function  
Comments  
In case only one Rx channel is  
enabled in the Operation Control  
Register it defines which channel is  
enabled.  
In case both channels are enabled  
and manual channel selection is  
active, it defines which channel is  
used for receive framing.  
0: Enable AM channel  
1: Enable PM channel  
7
ch_sel  
0
0: Peak detector  
1: Mixer  
AM demodulator type select,  
VHBR automatic preset to mixer  
6
amd_sel  
0
5
4
3
2
1
0
lp2  
lp1  
0
0
0
0
0
0
Low pass control  
(see Figure 13)  
For automatic and other  
recommended filter settings, refer  
to Figure 15.  
lp0  
h200  
h80  
z12k  
First and third stage zero  
setting  
(see Figure 14)  
Note: Default setting is set at power-up and after Set Default command.  
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 75  
A p p l i c a t i o n I n fo r m a t i o n  
Receiver Configuration Register 2  
Figure 58:  
Receiver Configuration Register 2  
Address 0Bh: Receiver Configuration Register 2  
Type: RW  
Bit  
Name  
Default  
Function  
Comments  
7
rx_lp  
0
1: Low power receiver operation  
0: Differential LF operation  
1: LF input split (RFI1 to AM  
channel, RFI2 to PM channel)  
6
lf_op  
0
5
4
lf_en  
0
1
1: LF signal on receiver input  
1: AGC is enabled  
agc_en  
0: AGC operates on first eight  
sub-carrier pulses  
1: AGC operates during  
3
2
agc_m  
1
0
complete receive period  
Algorithm with preset is recommended  
for protocols with short SOF (like  
ISO14443A fc/128)  
0: Algorithm with preset is used  
1: Algorithm with reset is used  
agc_alg  
Activated 18.88 μs after end of Tx,  
terminated with Mask Receive timer  
expire  
1: Automatic squelch activation  
after end of Tx  
1
0
sqm_dyn  
pmix_cl  
1
0
0: RFO  
1: Internal signal  
PM demodulator mixer clock source, in  
single mode internal signal is always used  
Note: Default setting is set at power-up and after Set Default command.  
AS3911 – 76  
ams Datasheet, Confidential: 2013-Oct [2-03]  
Application I nform ation  
Receiver Configuration Register 3  
Figure 59:  
Receiver Configuration Register 3  
Address 0Ch: Receiver Configuration Register 3 (1st stage  
gain settings)  
Type: RW  
Bit  
7
Name  
rg1_am2  
rg1_am1  
rg1_am0  
rg1_pm2  
rg1_pm1  
rg1_pm0  
Default  
Function  
Comments  
1
1
0
1
1
0
0: Full gain  
Gain reduction/boost in first gain 1-6: Gain reduction 2.5 dB per  
stage of AM channel.  
6
step (15 dB total)  
7: Boost +5.5 dB  
5
4
0: Full gain  
Gain reduction/boost in first gain 1-6: Gain reduction 2.5 dB per  
stage of PM channel.  
3
step (15 dB total)  
7: Boost +5.5 dB  
2
Signal clipped to 0.6 V, preset  
for NFCIP-1 active  
communication mode  
st  
nd  
1: Clip output of 1 and 2  
stage  
1
0
lim  
0
0
nd  
1: Forces gain reduction in 2  
and 3 gain stage to -6 dB and  
maximum comparator window  
Preset for NFCIP-1 active  
communication mode  
rd  
rg_nfc  
Note: Default setting is set at power-up and after Set Default command.  
ams Datasheet, Confidential: 2013-Oct [2-03]  
AS3911 – 77  
A p p l i c a t i o n I n fo r m a t i o n  
Receiver Configuration Register 4  
Figure 60:  
Receiver Configuration Register 4  
Address 0Dh: Receiver Configuration Register 4  
(2nd and 3rd stage gain settings)  
Type: RW  
Bit  
7
Name  
Default