AS3932 [AMSCO]
3D Low Frequency Wakeup Receiver; 3D低频唤醒接收器
| 型号： | AS3932 |
| 厂家： | 
AMS(艾迈斯) |
| 描述： | 3D Low Frequency Wakeup Receiver |
| 文件： | 总33页 (文件大小：1055K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
AS3932
3D Low Frequency Wakeup Receiver
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Wakeup sensitivity 100 µVRMS (typ.)
Adjustable sensitivity level
1 General Description
The AS3932 is a 3-channel low power ASK receiver that is able to
generate a wakeup upon detection of a data signal which uses a LF
carrier frequency between 110 - 150 kHz. The integrated correlator
can be used for detection of a programmable 16-bit wakeup pattern.
The device can operate using one, two, or three active channels.
Highly resistant to false wakeups
False wakeup counter
Periodical forced wakeup supported (1s – 2h)
Low power listening modes
The AS3932 provides a digital RSSI value for each active channel, it
supports a programmable data rate and Manchester decoding with
clock recovery. The AS3932 offers a real-time clock (RTC), which is
either derived from a crystal oscillator or the internal RC oscillator.
Current consumption in 3-channel listening mode 1.7 µA (typ.)
Data rate adjustable from 0.5- 4 kbps (Manchester)
Manchester decoding with clock recovery
Digital RSSI values available for each channel
Dynamic range 64dB
The programmable features of AS3932 enable to optimize its
settings for achieving a longer distance while retaining a reliable
wakeup generation. The sensitivity level of AS3932 can be adjusted
in presence of a strong field or in noisy environments.
5 bit RSSI step (2dB per step)
The device is available in 16 pin TSSOP and QFN 4x4 16LD
packages.
RTC based on 32kHz XTAL, RC-OSC, or External Clock
Operating temperature range -40 to +85ºC
Operating supply voltage 2.4 - 3.6V (TA = 25ºC)
Bidirectional serial digital interface (SDI)
Package option 16 pin TSSOP, QFN 4x4 16LD
2 Key Features
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3-channel ASK wakeup receiver
Carrier frequency range 110 - 150 kHz
One, two, or three channel operation
Reliable 1-, 2- or 3-D wakeup pattern detection
Programmable wakeup pattern (16bits)
Doubling of wakeup pattern supported
Wakeup without pattern detection supported
3 Applications
The AS3932 is ideal for Active RFID tags, Real-time location
systems, Operator identification, Access control, and Wireless
sensors.
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AS3932
Data Sheet - Applications
Figure 1. AS3932 Typical Application Diagram with Crystal Oscillator
VCC
VCC
XIN
CS
CL_DAT
DAT
CL
CBAT
XTAL
TRANSMITTER
TX
XOUT
WAKE
SCL
LF1P
LF2P
LF3P
LFN
AS3932
SDO
SDI
GND
VSS
Figure 2. AS3932 Typical Application Diagram with RC Oscillator
VCC
VCC
XIN
CS
CL_DAT
DAT
CBAT
XOUT
LF1P
LF2P
LF3P
LFN
TRANSMITTER
TX
WAKE
SCL
AS3932
SDO
SDI
GND
VSS
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AS3932
Data Sheet - Applications
Figure 3. AS3932 Typical Application Diagram with Clock from External Source
VCC
CBAT
VCC
XIN
CS
CL_DAT
DAT
EXTERNAL CLOCK
R
C
XOUT
TRANSMITTER
WAKE
SCL
LF1P
LF2P
LF3P
LFN
AS3932
TX
SDO
SDI
GND
VSS
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AS3932
Data Sheet - Contents
Contents
1 General Description.................................................................................................................................................................... 1
2 Key Features ............................................................................................................................................................................... 1
3 Applications ................................................................................................................................................................................ 1
4 Pin Assignments......................................................................................................................................................................... 5
4.1 TSSOP Package ......................................................................................................................................................................................5
4.1.1 Pin Descriptions............................................................................................................................................................................5
4.2 QFN Package........................................................................................................................................................................................... 6
4.2.1 Pin Descriptions............................................................................................................................................................................6
5 Absolute Maximum Ratings....................................................................................................................................................... 7
6 Electrical Characteristics........................................................................................................................................................... 8
7 Typical Operating Characteristics........................................................................................................................................... 10
8 Detailed Description ..................................................................................................................................................................11
8.1 Block Diagram ........................................................................................................................................................................................ 11
8.2 Operating Modes.................................................................................................................................................................................... 12
8.2.1 Power Down Mode ..................................................................................................................................................................... 12
8.2.2 Listening Mode ........................................................................................................................................................................... 12
8.2.3 Preamble Detection / Pattern Correlation................................................................................................................................... 13
8.2.4 Data Receiving ........................................................................................................................................................................... 13
8.3 System and Block Specification ............................................................................................................................................................. 13
8.3.1 Register Table ............................................................................................................................................................................ 13
8.3.2 Register Table Description and Default Values.......................................................................................................................... 14
8.3.3 Serial Data Interface (SDI).......................................................................................................................................................... 15
8.4 Channel Amplifier and Frequency Detector............................................................................................................................................ 18
8.4.1 Frequency Detector / AGC ......................................................................................................................................................... 18
8.4.2 Antenna Damper......................................................................................................................................................................... 19
8.5 Channel Selector / Demodulator / Data Slicer........................................................................................................................................ 20
8.6 Correlator................................................................................................................................................................................................ 21
8.7 Wakeup Protocol - Carrier Frequency 125 kHz...................................................................................................................................... 22
8.7.1 Without Pattern Detection (Manchester decoder disabled) ........................................................................................................ 23
8.7.2 Single Pattern Detection (Manchester decoder disabled) .......................................................................................................... 23
8.7.3 Single Pattern Detection (Manchester decoder enabled)........................................................................................................... 25
8.8 False Wakeup Register .......................................................................................................................................................................... 25
8.9 Real Time Clock (RTC)........................................................................................................................................................................... 26
8.9.1 Crystal Oscillator......................................................................................................................................................................... 27
8.9.2 RC-Oscillator ..............................................................................................................................................................................27
8.9.3 External Clock Source ................................................................................................................................................................ 28
8.10 Channel Selection in Scanning Mode and ON/OFF Mode................................................................................................................... 28
9 Package Drawings and Markings............................................................................................................................................ 29
10 Ordering Information.............................................................................................................................................................. 33
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AS3932
Data Sheet - Pin Assignments
4 Pin Assignments
4.1 TSSOP Package
Figure 4. Pin Assignments 16 pin TSSOP Package
1
2
3
CS
16
15
CL_DAT
DAT
SCL
SDI
SDO
VCC
WAKE
14
13
12
4
5
6
7
AS3932
VSS
XOUT
GND
LF3P
LF2P
11
10
9
XIN
LFN
LF1P
8
4.1.1 Pin Descriptions
Table 1. Pin Descriptions 16 pin TSSOP Package
Pin
Number
Pin Name
Pin Type
Description
CS
SCL
1
2
DI
DI
Chip select
SDI interface clock
SDI data input
SDI
3
DI
SDO
VCC
4
DO_T
S
SDI data output (tristate when CS is low)
Positive supply voltage
5
GND
LF3P
LF2P
LF1P
LFN
6
S
Negative supply voltage
Input antenna channel three
Input antenna channel two
Input antenna channel one
Common ground for antenna one, two and three
Crystal oscillator input
7
AIO
AIO
AIO
AIO
AIO
AIO
S
8
9
10
11
12
13
14
15
16
XIN
XOUT
VSS
Crystal oscillator output
Substrate
WAKE
DAT
DO
DO
DO
Wakeup output IRQ
Data output
CL_DAT
Manchester recovered clock
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AS3932
Data Sheet - Pin Assignments
4.2 QFN Package
Figure 5. Pin Assignments QFN 4x4 16LD Package
16
13
15
14
LF3P
1
2
12 SCL
LF2P
LF1P
LFN
CS
11
10
9
AS3932
3
4
CL_DAT
DAT
8
6
5
7
4.2.1 Pin Descriptions
Table 2. Pin Descriptions QFN 4x4 16LD Package
Pin
Pin Name
Pin Type
Description
Number
LF3P
LF2P
LF1P
LFN
1
2
AIO
AIO
AIO
AIO
AIO
AIO
S
Input antenna channel three
Input antenna channel two
Input antenna channel one
3
4
Common ground for antenna one, two and three
Crystal oscillator input
Crystal oscillator output
Substrate
XIN
5
XOUT
VSS
6
7
WAKE
DAT
8
DO
DO
DO
DI
Wakeup output IRQ
9
Data output
CL_DAT
CS
10
11
12
13
14
15
16
Manchester recovered clock
Chip select
SCL
DI
SDI interface clock
SDI
DI
SDI data input
SDO
VCC
DO_T
S
SDI data output (tristate when CS is low)
Positive supply voltage
Negative supply voltage
GND
S
PIN Types:
S: supply pad
AIO: analog I/O
DI: digital input
DO: digital output
DO_T: digital output / tristate
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AS3932
Data Sheet - Absolute Maximum Ratings
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 3 may cause permanent damage to the device. These are stress ratings only. Functional operation of the
device at these or any other conditions beyond those indicated in Section 6 Electrical Characteristics on page 8 is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Table 3. Absolute Maximum Ratings
Parameter
DC supply voltage (VDD)
Min
-0.5
-0.5
-100
±2
Max
5
Units
V
Notes
Input pin voltage (VIN)
5
V
Input current (latch up immunity) (ISOURCE)
Electrostatic discharge (ESD)
100
mA
kV
Norm: Jedec 78
Norm: MIL 883 E method 3015 (HBM)
Total power dissipation
(all supplies and outputs)
(Pt)
0.07
mW
Storage temperature (Tstrg
)
-65
5
150
260
85
ºC
ºC
%
Norm: IPC/JEDEC J-STD-020C1
Package body temperature (Tbody
)
Humidity non-condensing
1. The reflow peak soldering temperature (body temperature) is specified according IPC/JEDEC J-STD-020C “Moisture/Reflow Sensitivity
Classification for Nonhermetic Solid State Surface Mount Devices”.
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AS3932
Data Sheet - Electrical Characteristics
6 Electrical Characteristics
Table 4. Electrical Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Operating Conditions
AVDD
AVSS
Tamb
Positive supply voltage
Negative supply voltage
Ambient temperature
2.4
0
3.6
0
V
V
-40
85
ºC
DC/AC Characteristics for Digital Inputs and Outputs
CMOS Input
0.58 *
0.7 *
0.83 *
VIH
VIL
High level input voltage
V
VDD
VDD
VDD
0.125 *
VDD
0.2 *
VDD
0.3 *
DVDD
Low level input voltage
Input leakage current
V
ILEAK
100
nA
CMOS Output
VDD -
0.4
VOH
High level output voltage
With a load current of 1mA
V
VSS +
VOL
CL
Low level output voltage
Capacitive load
With a load current of 1mA
V
0.4
For a clock frequency of 1 MHz
400
pF
Tristate CMOS Output
VDD -
0.4
VOH
High level output voltage
With a load current of 1mA
V
VSS +
VOL
IOZ
Low level output voltage
Tristate leakage current
With a load current of 1mA
to DVDD and DVSS
V
0.4
100
nA
Table 5. Electrical System Specifications
Symbol
Input Characteristics
Rin
Parameter
Conditions
Min
Typ
Max
Units
Input Impedance
In case no antenna damper is set (R1<4>=0)
2
M Ohm
kHz
Fmin
Minimum Input Frequency
Maximum Input Frequency
110
150
Fmax
kHz
Current Consumption
IPWD
Power Down Mode
400
2.7
800
nA
Current Consumption in
standard listening mode with
one active channel and RC-
oscillator as RTC
I1CHRC
I2CHRC
I3CHRC
µA
Current Consumption in
standard listening mode with
two active channels and RC-
oscillator as RTC
4.2
5.7
µA
µA
Current Consumption in
standard listening mode with
three active channels and RC-
oscillator as RTC
8.3
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AS3932
Data Sheet - Electrical Characteristics
Table 5. Electrical System Specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Current Consumption in
scanning mode with three
active channels and RC-
oscillator as RTC
I3CHSCRC
2.7
µA
Current Consumption in ON/
OFF mode with three active
channels and RC-oscillator as
RTC
11% Duty Cycle
50% Duty Cycle
1.7
I3CHOORC
I3CHXT
IDATA
µA
µA
µA
3.45
Current Consumption in
standard listening mode with
three active channels and
crystal oscillator as RTC
6.5
8.3
8.9
12
Current Consumption in
Preamble detection / Pattern
correlation / Data receiving
mode (RC-oscillator)
With 125 kHz carrier frequency and 1 kbps
data-rate. No load on the output pins.
Input Sensitivity
With 125 kHz carrier frequency, chip in default
mode, 4 half bits burst + 4 symbols preamble
and single preamble detection
Input Sensitivity on all
channels
SENS
100
µVrms
µs
Channel Settling Time
TSAMP
Amplifier settling time
250
Crystal Oscillator
FXTAL
Frequency
Start-up Time
Crystal dependent
Crystal dependent
32.768
kHz
s
TXTAL
1
IXTAL
Current consumption
1
1
µA
External Clock Source
IEXTCL
RC Oscillator
FRCNCAL
Current consumption
µA
Frequency
Frequency
If no calibration is performed
27
31
32.768
32.768
42
kHz
kHz
If calibration with 32.768 kHz reference signal
is performed
FRCCAL32
34.5
Maximum achievable frequency after
calibration
FRCCALMAX
FRCCALMIN
TCALRC
Frequency
Frequency
35
30
kHz
kHz
Minimum achievable frequency after calibration
Periods of
reference
clock
Calibration time
65
IRC
Current consumption
200
nA
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AS3932
Data Sheet - Typical Operating Characteristics
7 Typical Operating Characteristics
Figure 6. Sensitivity over Voltage and Temperature
Figure 7. Sensitivity over RSSI
1000000
120
95 o
C
C
100000
10000
1000
100
100
80
60
40
20
0
27 o
-40 o
C
10
1
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
2.4
3
Supply Voltage [V]
3.6
RSSI [dB]
Figure 8. RC-Osc Frequency over Voltage (calibr.)
Figure 9. RC-Osc Frequency over Temperature (calibr.)
34.5
34.5
34
34
33.5
33
33.5
33
32.5
32
32.5
32
31.5
31
31.5
31
-36 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
2.4
2.6
2.8
3
3.2
3.4
3.6
Operating Temperature [oC]
Supply Voltage [V]
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AS3932
Data Sheet - Detailed Description
8 Detailed Description
The AS3932 is a three-dimensional low power low-frequency wakeup receiver. The AS3932 is capable to detect the presence of an inductive
coupled carrier and extract the envelope of the On-Off-Keying (OOK) modulated carrier. In case the carrier is Manchester coded the clock is
recovered from the transmitted signal and the data can be correlated with a programmed pattern. If the detected pattern corresponds to the
stored one a wake-up signal (IRQ) is risen up. The pattern correlation can be bypassed in case and the wake-up detection is based only on the
frequency detection.
The AS3932 is made up by three independent receiving channels, one envelop detector, one data correlator, one Manchester decoder, 8
programmable registers with the main logic and a real time clock.
The digital logic can be accessed by an SPI. The real time clock can be based on a crystal oscillator or on an internal RC one. In case the
second is used to improve its accuracy a calibration can be performed.
8.1 Block Diagram
Figure 10. Block Diagram
AS3932
IRQ
SCL
Wakeup
Amp Out
Channel
Amplifier 1
Main
Logic
RSSI
SDI
SDI
LF1P
SDO
CS
Amp Out
Channel
Selector
Envelope Detector /
Data Slicer
Correlator
RSSI
Channel
Amplifier 2
LF2P
Manchester
Decoder
DAT
Amp Out
CL_DAT
Channel
Amplifier 3
RSSI
LF3P
LFN
I/V
Bias
RC RTC
Xtal RTC
VCC
GND
XIN
XOUT
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AS3932
Data Sheet - Detailed Description
AS3932 needs the following external components:
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Power supply capacitor - CBAT – 100 nF
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32.768 kHz crystal with its two pulling capacitors – XTAL and CL – (it is possible to omit these components if the internal RC oscillator is
used instead of the crystal oscillator).
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One, two, or three LC resonators according to the number of used channels.
In case the internal RC-oscillator is used (no crystal oscillator is mounted), the pin XIN has to be connected to the supply, while pin XOUT should
stay floating. Application diagrams with and without crystal are shown in Figure 1and Figure 2
8.2 Operating Modes
8.2.1 Power Down Mode
In Power Down Mode AS3932 is completely switched off. The typical current consumption is 400 nA.
8.2.2 Listening Mode
In listening mode only the active channel amplifiers and the RTC are running. In this mode the system detects the presence of a carrier. In case
the carrier is detected the RSSI can be displayed.
If the three dimensional detection is not required it is possible to deactivate one or more channels. In case only two channels are required the
deactivated channel must be the number three, while if only one channel detection is needed the active channel must be the number one.
Inside this mode it is possible to distinguish the following three sub modes:
8.2.2.1 Standard Listening mode
All channels are active at the same time
8.2.2.2 Scanning mode (Low Power mode 1)
All used channels are active, but only one per time slot, where the time slot T is defined as 1ms. If, for example all three channels are used in the
first millisecond the only active channel is the number one, after the first millisecond the channel three will be active for the same period of time
and at the end the channel two will be working for one millisecond, handing over to the channel one again. This channel rotation goes on until the
presence of the carrier is detected by any of the channels; then immediately all three channels will become active at the same time. Now AS3932
can perform a simultaneous multidirectional evaluation (on all three channels) of the field and evaluate which channel has the strongest RSSI.
The channel with the highest RSSI will be put through to the demodulator. In this way it is possible to perform multidirectional monitoring of the
field with a current consumption of a single channel, keeping the sensitivity as good as if all channels are active at the same time.
Figure 11. Scanning Mode
Channel1
Channel2
tim e
Channel3
tim e
Presence
of carrier
tim e
t 0
t 0 + T
t 0 + 2 T
t 0 + 3 T
t 0 + 4 T
t 0 + 5 T
t 1
tim e
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AS3932
Data Sheet - Detailed Description
8.2.2.3 ON/OFF mode (Low Power mode 2)
All active channels are on at the same time but not for the whole time (time slot T is defined as 1ms). An on-off duty-ratio is defined. This duty
ratio is programmable see R4<7:6>.
Figure 12. ON/OFF Mode
Channel1
Channel2
time
Channel3
time
Presence
of carrier
time
time
t0
t0+T
2*t0
2*t0+T
3*t0
For each of these sub modes it is possible to enable a further feature called Artificial Wake-up. The Artificial Wake-up is a counter based on the
used RTC. Three bits define a time window see R8<2:0>. If no activity is seen within this time window the chip will produce an interrupt on the
WAKE pin that lasts 128 µs. With this interrupt the microcontroller (µC) can get feedback on the surrounding environment (e.g. read the false
wakeup register, see Correlator register R13<7:0>) and/or take actions in order to change the setup.
8.2.3 Preamble Detection / Pattern Correlation
The chip can go in to this mode after detecting a LF carrier only if the data correlator function is enabled see R1<1>. The correlator searches
first for preamble frequency (constant frequency of Manchester clock defined according to bit-rate transmission) and then for data pattern.
If the pattern is matched the wake-up interrupt is displayed on the WAKE output and the chip goes in Data receiving mode. If the pattern fails the
internal wake-up (on all active channels) is terminated and no IRQ is produced.
8.2.4 Data Receiving
The user can enable this mode allowing the pattern correlation or just on the base of the frequency detection. In this mode the chip can be
retained a normal OOK receiver. The data is provided on the DAT pin and in case the Manchester decoder is enabled see R1<3>, the recovered
clock is present on the CL_DAT. It is possible to put the chip back to listening mode either with a direct command (CLEAR_WAKE (see Table 12))
or by using the timeout feature. This feature automatically sets the chip back to listening mode after a certain time R7<7:5>.
8.3 System and Block Specification
8.3.1 Register Table
Table 6. Register Table
7
6
5
4
3
2
1
0
R0
R1
R2
R3
R4
R5
R6
R7
n.a.
MUX_123
ATT_ON
EN_A2
EN_A3
EN_PAT2
EN_A1
PWD
ON_OFF
ABS_HY
S_ABSH
HY_20m
AGC_TLIM
AGC_UD
EN_MANCH
Reserved
EN_WPAT
EN_RTC
W_PAT_T<1:0>
HY_POS
S_WU1<1:0>
FS_ENV<2:0>
GR<3:0>
FS_SLC<2:0>
T_OFF<1:0>
R_VAL<1:0>
TS2<7:0>
TS1<7:0>
T_OUT<2:0>
T_HBIT<4:0>
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AS3932
Data Sheet - Detailed Description
Table 6. Register Table
7
6
5
4
3
2
1
0
R8
R9
n.a.
T_AUTO<2:0>
n.a.
Reserved
R10
R11
R12
R13
n.a.
n.a.
n.a.
RSSI1<4:0>
RSSI3<4:0>
RSSI2<4:0>
F_WAKE
8.3.2 Register Table Description and Default Values
Table 7. Default Values of Registers
Default
Register
Name
Type
Description
Value
R0<5>
R0<4>
R0<3>
R0<2>
R0<1>
R0<0>
R1<7>
R1<6>
R1<5>
R1<4>
R1<3>
R1<2>
R1<1>
R1<0>
R2<7>
R2<6:5>
R2<4:2>
R2<1:0>
ON_OFF
MUX_123
EN_A2
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
0
0
On/Off operation mode. (Duty-cycle defined in the register R4<7:6>)
Scan mode enable
1
Channel 2 enable
EN_A3
1
Channel 3 enable
EN_A1
1
Channel 1 enable
PWD
0
Power down
ABS_HY
AGC_TLIM
AGC_UD
ATT_ON
EN_MANCH
EN_PAT2
EN_WPAT
EN_RTC
S_ABSH
W_PAT
0
Data slicer absolute reference
AGC acting only on the first carrier burst
AGC operating in both direction (up-down)
Antenna damper enable
0
1
0
0
Manchester decoder enable
Double wakeup pattern correlation
Data correlation enable
0
1
1
Crystal oscillator enable
0
Data slicer threshold reduction
Pattern correlation tolerance (see Table 19)
Reserved
00
000
00
S_WU1
W
W
Tolerance setting for the stage wakeup (see Table 13)
Data slicer hysteresis
if HY_20m = 0 then comparator hysteresis = 40mV
if HY_20m = 1 then comparator hysteresis = 20mV
R3<7>
R3<6>
HY_20m
0
0
Data slicer hysteresis only on positive edges (HY_POS=0, hysteresis on both
edges, HY_POS=1, hysteresis only on positive edges)
HY_POS
W
R3<5:3>
R3<2:0>
FS_SCL
FS_ENV
W
W
100
000
Data slices time constant (see Table 17)
Envelop detector time constant (see Table 16)
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AS3932
Data Sheet - Detailed Description
Table 7. Default Values of Registers
Default
Value
Register
Name
Type
Description
Off time in ON/OFF operation mode
T_OFF=00
T_OFF=01
T_OFF=10
T_OFF=11
1ms
R4<7:6>
T_OFF
W
00
2ms
4ms
8ms
R4<5:4>
R4<3:0>
D_RES
GR
W
W
01
Antenna damping resistor (see Table 15)
Gain reduction (see Table 14)
0000
2nd Byte of wakeup pattern
R5<7:0>
R6<7:0>
TS2
TS1
W
W
01101001
10010110
1st Byte of wakeup pattern
Automatic time-out (see Table 20)
Bit rate definition (see Table 18)
Artificial wake-up
No artificial wake-up
1 sec
R7<7:5>
R7<4:0>
T_OUT
T_HBIT
W
W
000
01011
T_AUTO=000
T_AUTO=001
T_AUTO=010
T_AUTO=011
T_AUTO=100
T_AUTO=101
T_AUTO=110
T_AUTO=111
5 sec
R8<2:0>
T_AUTO
W
000
20 sec
2 min
15min
1 hour
2 hour
R9<6:0>
R10<4:0>
R11<4:0>
R12<4:0>
R13<7:0>
000000
Reserved
RSSI1
RSSI3
RSSI2
F_WAK
R
R
RSSI channel 1
RSSI channel 3
RSSI channel 2
False wakeup register
R
WR
8.3.3 Serial Data Interface (SDI)
This 4-wires interface is used by the Microcontroller (µC) to program the AS3932. The clock operation frequency of the SDI is 1MHz.
Table 8. Serial Data Interface (SDI) pins
Name
Signal
Signal Level
Description
CS
Digital Input with pull down
CMOS
Chip Select
Serial Data input for writing registers, data to
transmit and/or writing addresses to select
readable register
SDI
Digital Input with pull down
CMOS
Serial Data output for received data or read
value of selected registers
SDO
Digital Output
CMOS
CMOS
SCLK
Digital Input with pull down
Clock for serial data read and write
Note: SDO is set to tristate if CS is low. In this way more than one device can communicate on the same SDO bus.
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Data Sheet - Detailed Description
8.3.3.1 SDI Command Structure
To program the SDI the CS signal has to go high. A SDI command is made up by a two bytes serial command and the data is sampled on the
falling edge of SCLK. The Table 9 shows how the command looks like, from the MSB (B15) to LSB (B0). The command stream has to be sent to
the SDI from the MSB (B15) to the LSB (B0).
Table 9. SDI Command Structure
Mode
B15 B14
Register address / Direct Command
B12 B11 B10 B9
Register Data
B4 B3
B13
B8
B7
B6
B5
B2
B1
B0
The first two bits (B15 and B14) define the operating mode. There are three modes available (write, read, direct command) plus one spare (not
used), as shown in Table 10.
Table 10. SDI Command Structure
B15
0
B14
0
Mode
WRITE
0
1
READ
1
0
NOT ALLOWED
DIRECT COMMAND
1
1
In case a write or read command happens the next 5 bits (B13 to B9) define the register address which has to be written respectively read, as
shown in Table 11.
Table 11. SDI Command Structure
B13
0
B12
0
B11
0
B10
0
B9
0
0
1
1
0
0
1
1
0
0
1
1
0
0
B8
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Read/Write register
R0
R1
0
0
0
0
0
0
0
0
R2
0
0
0
0
R3
0
0
0
1
R4
0
0
0
1
R5
0
0
0
1
R6
0
0
0
1
R7
0
0
1
0
R8
0
0
1
0
R9
0
0
1
0
R10
R11
R12
R13
0
0
1
0
0
0
1
1
0
0
1
1
The last 8 bits are the data that has to be written respectively read. A CS toggle high-low-high terminates the command mode.
If a direct command is sent (B15-B14=11) the bits from B13 to B9 defines the direct command while the last 8 bits are omitted. The Table 12
shows all possible direct commands:
Table 12. List of Direct Commands
COMMAND_MODE
clear_wake
B13
0
B12
0
B11
0
B10
0
B9
0
B8
0
reset_RSSI
0
0
0
0
0
1
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Data Sheet - Detailed Description
Table 12. List of Direct Commands
COMMAND_MODE
B13
0
B12
0
B11
0
B10
0
B9
1
B8
0
trim_osc
clear_false
0
0
0
0
1
1
preset_default
0
0
0
1
0
0
All direct commands are explained below:
- clear_wake: clears the wake state of the chip. In case the chip has woken up (WAKE pin is high) the chip is set back to listening mode
- reset_RSSI: resets the RSSI measurement.
- trim_osc: starts the trimming procedure of the internal RC oscillator (see Figure 22)
- clear_false: resets the false wakeup register (R13=00)
- preset_default: sets all register in the default mode, as shown in Figure 7
8.3.3.2 Writing of Data to Addressable Registers (WRITE Mode)
The SDI is sampled at the falling edge of CLK (as shown in the following diagrams).
A CS toggling high-low-high indicates the end of the WRITE command after register has been written. The following example shows a write
command.
Figure 13. Writing of a Single Byte (falling edge sampling)
CS
SCLK
X
X
0
0
A5
A4
A3
A2
A1
SCLK
falling edge
Data is
A0
D7
D6
D5
D4
D3
D2
D1
D0
SDI
SCLK raising
edge Data is
transfered from
CS falling
edge signals
end of
Two leading
Zeros indicate
WRITE Mode
Data is moved
to Address
A5-A0
µC
WRITE Mode
sampled
Figure 14. Writing of Register Data with Auto-incrementing Address
CS
SCLK
A
5
A
4
A
3
A
2
A
1
A
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
X
X
0 0
SDI
CS falling
edge signals
end of
Two leading
Zeros indicate
WRITE Mode
Data is moved
to Address
<A 5-A0>
Data is moved
to Address
<A5-A0> +1
Data is moved
to Address
<A5-A0 > + (n- 1)
Data is moved
to Address
<A5-A0 >+ n
WRITE Mode
8.3.3.3 Reading of Data from Addressable Registers (READ Mode)
Once the address has been sent through SDI, the data can be fed through the SDO pin out to the microcontroller.
A CS LOW toggling high-low-high has to be performed after finishing the read mode session, in order to indicate the end of the READ command
and prepare the Interface to the next command control Byte.
To transfer bytes from consecutive addresses, SDI master has to keep the CS signal high and the SCLK clock has to be active as long as data
need to be read.
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AS3932
Data Sheet - Detailed Description
Figure 15. Reading of Single Register Byte
CS
SCLK
X
X
0
1
A5
A4
A3
A2
A1
A0
SDI
SDO
X
X
D7
D6
D5
D4
D3
D2
D1
D0
SCLK rais ing
edge Data is
mov ed from
Address
SCLK raising
edge Data is
transfered from
SCLK
falling edge
Data is
sampled
SCLK falling
edge Data is
transfered to
CS falling
edge signals
end of READ
Mode
01 pattern
indicates
READ Mode
<A5-A0>
µC
µC
Figure 16. Send Direct COMMAND byte
8.4 Channel Amplifier and Frequency Detector
Each of the 3 channels consists of a variable gain amplifier, an automatic gain control and a frequency detector. The latter detects the presence
of a carrier. As soon as the carrier is detected the AGC is enabled, the gain of the VGA is reduced and set to the right value and the RSSI can be
displayed.
It is possible to enable/disable individual channels, in case not all three channels are needed. This enables to reduce the current consumption by
1.5 µA (typ.) per channel.
8.4.1 Frequency Detector / AGC
The frequency detection uses the RTC as time base. In case the internal RC oscillator is used as RTC, it must be calibrated, but the calibration
is guaranteed for a 32.768 kHz crystal oscillator only. The frequency detection criteria can be tighter or more relaxed according to the setup
described in R2<1:0>(see Table 13).
Table 13. Tolerance Settings for Wakeup
R2<1>
R2<0>
Tolerance
relaxed
0
0
1
1
0
1
0
1
tighter (medium)
stringent
Reserved
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Data Sheet - Detailed Description
The AGC can operate in two modes:
ꢀ
AGC down only (R1<5>=0)
ꢀ
AGC up and down (R1<5>=1)
As soon as the AGC starts to operate, the gain in the VGA is set to maximum. If the AGC down only mode is selected, the AGC can only
decrease the gain. Since the RSSI is directly derived from the VGA gain, the system holds the RSSI peak.
When the AGC up and down mode is selected, the RSSI can follow the input signal strength variation in both directions.
Regardless which AGC operation mode is used, the AGC needs maximum 35 carrier periods to settle.
The RSSI is available for all 3 channels at the same time and it is stored in 3 registers (R10<4:0>, R11<4:0>, R12<4:0>)
Both AGC modes (only down or down and up) can also operate with time limitation. This option allows AGC operation only in time slot of 256µs
following the internal wake-up. Then the AGC (RSSI) is frozen till the wake-up or RSSI reset occurs.
The RSSI is reset either with the direct command 'clear_wakeup' or 'reset_RSSI'. The 'reset_RSSI' command resets only the AGC setting but
does not terminate wake-up condition. This means that if the signal is still present the new AGC setting (RSSI) will appear not later than 300µs
(35 LF carrier periods) after the command was received. The AGC setting is reset if for duration of 3 Manchester half symbols no carrier is
detected. If the wake-up IRQ is cleared the chip will go back to listening mode.
In case the maximum amplification at the beginning is a drawback (e.g. in noisy environment) it is possible to set a smaller starting gain on the
amplifier, according to the Table 14. In this way it is possible to reduce the false frequency detection.
Table 14. Bit Setting of Gain Reduction
R4<3>
R4<2>
R4<1>
R4<0>
0
Gain reduction
no gain reduction
n.a.
0
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
n.a.
-4dB
-8dB
-12dB
-16dB
-20dB
-24dB
8.4.2 Antenna Damper
The antenna damper allows the chip to deal with higher field strength, it is enabled by register R1<4>. It consists of shunt resistors which
degrade the quality factor of the resonator by reducing the signal at the input of the amplifier. In this way the resonator sees a smaller parallel
resistance (in the band of interest) which degrades its quality factor in order to increase the linear range of the channel amplifier (the amplifier
doesn't saturate in presence of bigger signals). Table 15 shows the bit setup.
Table 15. Antenna Damper Bit Setup
R4<5>
R4<4>
Shunt resistor (parallel to the resonator at 125 kHz)
0
0
1
1
0
1
0
1
1 kΩ
3 kΩ
9 kΩ
27 kΩ
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AS3932
Data Sheet - Detailed Description
8.5 Channel Selector / Demodulator / Data Slicer
When at least one of three gain channel enters initial wake-up state the channel selector makes a decision which gain channel to connect to the
envelope detector. If only one channel is in wake-up state the selection is obvious. If more than one channel enters wake-up state in 256µs
following the first active channel the channel with highest RSSI value is selected. The output signal (amplified LF carrier) of selected channel is
connected to the input of the demodulator.
The performance of the demodulator can be optimized according to bit rate and preamble length as described in Table 16 and Table 17.
Table 16. Bit Setup for the Envelop Detector for Different Symbol Rates
R3<2>
R3<1>
R3<0>
Symbol rate [Manchester symbols/s]
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4096
2184
1490
1130
910
762
655
512
If the bit rate gets higher the time constant in the envelop detector must be set to a smaller value, this means that higher noise is injected
because of the wider band. The next table is a rough indication of how the envelop detector looks like for different bit rates. By using proper data
slicer settings it is possible to improve the noise immunity paying the penalty of a longer preamble. In fact if the data slicer has a bigger time
constant it is possible to reject more noise, but every time a transmission occurs, the data slicer need time to settle. This settling time will
influence the length of the preamble. Table 17 gives a correlation between data slicer setup and minimum required preamble length.
Table 17. Bit Setup for the Data Slicer for Different Preamble Length
R3<5>
R3<4>
R3<3>
Minimum preamble length [ms]
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0.8
1.15
1.55
1.9
2.3
2.65
3
3.5
Note: These times are minimum required, but it is recommended to prolong the preamble.
The comparator of the data slicer can work only with positive or with symmetrical threshold (R3<6>). In addition the threshold can be 20 or 40 mV
(R3<7>)
In case the length of the preamble is an issue the data slicer can also work with an absolute threshold (R1<7>). In this case the bits R3<2:0>
would not influence the performance. It is even possible to reduce the absolute threshold in case the environment is not particularly noisy
(R2<7>).
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Data Sheet - Detailed Description
8.6 Correlator
After frequency detection the data correlation is only performed if the correlator is enabled (R1<1>=1).
The data correlation consists of checking the presence of a preamble (ON/OFF modulated carrier) followed by a certain pattern.
After the frequency detection the correlator waits 16 bits (see bit rate definition in Table 18) and if no preamble is detected the chip is set back to
listening mode and the false-wakeup register (R13<7:0>) is incremented by one.
To get started with the pattern correlation the correlator needs to detect at least 4 bits of the preamble (ON/OFF modulated carrier).
The bit duration is defined in the register R7<4:0> according to the Table 18 as function of the Real Time Clock (RTC) periods.
Table 18. Bit Rate Setup
Bit duration in RTC
clock periods
Symbol rate (Manchester
symbols/s)
R7<4>
R7<3>
R7<2>
R7<1>
R7<0>
Bit rate (bits/s)
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
4
8192
6552
5460
4680
4096
3640
3276
2978
2730
2520
2340
2184
2048
1926
1820
1724
1638
1560
1488
1424
1364
1310
1260
1212
1170
1128
1092
1056
1024
4096
3276
2730
2340
2048
1820
1638
1489
1365
1260
1170
1092
1024
963
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
910
862
819
780
744
712
682
655
630
606
585
564
546
528
512
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Data Sheet - Detailed Description
If the preamble is detected correctly the correlator keeps searching for a data pattern. The duration of the preamble plus the pattern should not
be longer than 40 bits (see bit rate definition in Table 18). The data pattern can be defined by the user and consists of two bytes which are stored
in the registers R5<7:0> and R6<7:0>. The two bytes define the pattern consisting of 16 half bit periods. This means the pattern and the bit
period can be selected by the user. The only limitation is that the pattern (in combination with preamble) must obey Manchester coding and
timing. It must be noted that according to Manchester coding a down-to-up bit transition represents a symbol "0", while a transition up-to-down
represents a symbol "1". If the default code is used (96 [hex]) the binary code is (10 01 01 10 01 10 10 01). MSB has to be transmitted first.
The user can also select (R1<2>) if single or double data pattern is used for wake-up. In case double pattern detection is set, the same pattern
has to be repeated 2 times.
Additionally it is possible to set the number of allowed missing zero bits (not symbols) in the received bitstream (R2<6:5>), as shown in the Table
19.
Table 19. Allowed Pattern Detection Errors
R2<6>
R2<5>
Maximum allowed error in the pattern detection
No error allowed
0
0
1
1
0
1
0
1
1 missed zero
2 missed zeros
3 missed zeros
If the pattern is matched the wake-up interrupt is displayed on the WAKE output. In case the Manchester decoder is enabled (R1<3>) the data
coming out from the DAT pin are decoded and the clock is recovered on the pin DAT_CL.
The data coming out from the DAT pin are stable (and therefore can be acquired) on the rising edge of the CL_DAT clock, as shown in Figure 17.
Figure 17. Synchronization of Data with Recovered Manchester Clock
CL_DAT
DAT
If the pattern detection fails the internal wake-up (on all active channels) is terminated with no signal sent to MCU and the false wakeup register
will be incremented (R13<7:0>).
8.7 Wakeup Protocol - Carrier Frequency 125 kHz
The wake-up state is terminated with the direct command ‘clear_wake’ Table 12. This command terminates the MCU activity. The termination
can also be automatic in case there is no response from MCU. The time out for automatic termination is set in a register R7<7:5>, as shown in
the Table 20.
Table 20. Timeout Setup
R7<7>
R7<6>
R7<5>
Time out
0 sec
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
50 msec
100 msec
150 msec
200 msec
250 msec
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Data Sheet - Detailed Description
Table 20. Timeout Setup
R7<7>
R7<6>
R7<5>
Time out
300 msec
350 msec
1
1
1
1
0
1
8.7.1 Without Pattern Detection (Manchester decoder disabled)
Figure 18. Wakeup Protocol Overview without Pattern Detection (only carrier frequency detection, Manchester decoder disabled)
In case the data correlation is disabled (R1<1>=0) the AS3932 wakes up upon detection of the carrier frequency only as shown in Figure 18. In
order to ensure that AS3932 wakes up the carrier burst has to last longer than 550 µs. To set AS3932 back to listening mode there are two
possibilities: either the microcontroller sends the direct command clear_wake via SDI or the time out option is used (R7<7:5>). In case the latter
is chosen, AS3932 is automatically set to listening mode after the time defined in T_OUT (R7<7:5>), counting starts at the low-to-high WAKE
edge on the WAKE pin.
8.7.2 Single Pattern Detection (Manchester decoder disabled)
The Figure 19 shows the wakeup protocol in case the pattern correlation is enabled (R1<1>=1) for a 125 kHz carrier frequency. The initial carrier
burst has to be longer than 550 µs and can last maximum 16 bits (see bit rate definition in Table 18). If the ON/OFF mode is used (R1<5>=1), the
minimum value of the maximum carrier burst duration is limited to 10 ms. This is summarized in Table 21. In case the carrier burst is too long the
internal wakeup will be set back to low and the false wakeup counter (R13<7:0>) will be incremented by one. The carrier burst must be followed
by a preamble (0101... modulated carrier with a bit duration defined in Table 18) and the wakeup pattern stored in the registers R5<7:0> and
R6<7:0>. The preamble must have at least 4 bits and the preamble duration together with the pattern should not be longer than 40 bits. If the
wakeup pattern is correct the signal on the WAKE pin is set to high and the data transmission can get started. To set the chip back to listening
mode the direct command clear_false, as well as the time out option (R7<7:5>) can be used.
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Data Sheet - Detailed Description
Figure 19. Wakeup Protocol Overview with Single Pattern Detection (Manchester decoder disabled)
Table 21. Preamble Requirements in Standard Mode, Scanning Mode and ON/OFF Mode
Maximum duration of the carrier burst in Standard Maximum duration of the carrier burst in ON/OFF Mode
Bit rate (bit/s)
Mode and Scanning Mode (ms)
(ms)
8192
6552
5460
4680
4096
3640
3276
2978
2730
2520
2340
2184
2048
1926
1820
1724
1638
1560
1488
1424
1364
1310
1260
1.95
2.44
2.93
3.41
3.90
4.39
4.88
5.37
5.86
6.34
6.83
7.32
7.81
8.30
8.79
9.28
9.76
10.25
10.75
11.23
11.73
12.21
12.69
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10.25
10.75
11.23
11.73
12.21
12.69
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Data Sheet - Detailed Description
Table 21. Preamble Requirements in Standard Mode, Scanning Mode and ON/OFF Mode
Maximum duration of the carrier burst in Standard Maximum duration of the carrier burst in ON/OFF Mode
Bit rate (bit/s)
Mode and Scanning Mode (ms)
(ms)
13.20
13.67
14.18
14.65
15.15
15.62
1212
1170
1128
1092
1056
1024
13.20
13.67
14.18
14.65
15.15
15.62
8.7.3 Single Pattern Detection (Manchester decoder enabled)
The Figure shows the wakeup protocol in case both the pattern correlation and the Manchester decoder are enabled (R1<1>=1 and R1<3>=1)
for a 125 kHz carrier frequency. The initial carrier burst has to be at least 42 Manchester symbols long and has to be followed by a separation bit
(one bit of no-carrier). The carrier burst must be followed by a minimum 4 Manchester symbol preamble (10101010) and the pattern stored in the
R5<7:0> and R6<7:0>. The preamble can only be made up by integer Manchester symbol and the preamble duration together with the pattern
should not be longer than 40 bits. If the pattern is correct the signal on the WAKE pin is set to high, the data are internally decoded and the
Manchester clock is recovered. To set the AS3932 back to listening mode the direct command clear_false or the time out option (R7<7:5>) can
be used.
In case the On/OFF mode is enabled the Manchester decoder can not be used.
Figure 20. Wakeup Protocol Overview with Single Pattern Detection (Manchester decoder enabled)
8.8 False Wakeup Register
The wakeup strategy in the AS3932 is based on 2 steps:
1. Frequency Detection: in this phase the frequency of the received signal is checked.
2. Pattern Correlation: here the pattern is demodulated and checked whether it corresponds to the valid one.
If there is a disturber or noise capable to overcome the first step (frequency detection) without producing a valid pattern, then a false wakeup call
happens.Each time this event is recognized a counter is incremented by one and the respective counter value is stored in a memory cell (false
wakeup register). Thus, the microcontroller can periodically look at the false wakeup register, to get a feeling how noisy the surrounding
environment is and can then react accordingly (e.g. reducing the gain of the LNA during frequency detection, set the AS3932 temporarily to
power down etc.), as shown in the Figure 21. The false wakeup counter is a useful tool to quickly adapt the system to any changes in the noise
environment and thus avoid false wakeup events.
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AS3932
Data Sheet - Detailed Description
Most wakeup receivers have to deal with environments that can rapidly change. By periodically monitoring the number of false wakeup events it
is possible to adapt the system setup to the actual characteristics of the environment and enables a better use of the full flexibility of AS3932.
Note: If the Manchester decoder is enabled, the false wakeup register is not able anymore to store the false wakeup events.
Figure 21. Concept of the False Wakeup Register together with the system
Wakeup
Level2
Wakeup
Level1
WAKE
Frequency Detector
Pattern Correlator
Unsuccessful
pattern
correlation
False wakeup
register
Register Setup
READ FALSE WAKEUP REGISTER
Microcontroller
8.9 Real Time Clock (RTC)
The RTC can be based on a crystal oscillator (R1<0>=1), the internal RC-oscillator (R1<0>=0), or an external clock source (R1<0>=1). The
crystal oscillator has higher precision of the frequency with higher current consumption and needs three external components (crystal plus two
capacitors). The RC-oscillator is completely integrated and can be calibrated if a reference signal is available for a very short time to improve the
frequency accuracy. The calibration gets started with the trim_osc direct command. Since no non-volatile memory is available on the chip, the
calibration must be done every time after battery replacement. Since the RTC defines the time base of the frequency detection, the selected
frequency (frequency of the crystal oscillator or the reference frequency used for calibration of the RC oscillator) should be about one forth of the
carrier frequency:
FRTC ~ FCAR * 0.25
Where: FCAR is the carrier frequency and FRTC is the RTC frequency
The third option for the RTC is the use of an external clock source, which must be applied directly to the XIN pin (XOUT floating).
(EQ 1)
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AS3932
Data Sheet - Detailed Description
8.9.1 Crystal Oscillator
Table 22. Characteristics of XTAL
Symbol
Parameter
Conditions
Min
Typ
Max
±120
60
Units
Crystal accuracy
(initial)
Overall accuracy
p.p.m.
Crystal motional resistance
Frequency
KΩ
32.768
±5
kHz
Contribution of the oscillator to the
frequency error
p.p.m
Start-up Time
Duty cycle
Crystal dependent
1
50
1
s
45
55
%
Current consumption
µA
8.9.2 RC-Oscillator
Table 23. Characteristics of RCO
Symbol
Parameter
Conditions
Min
Typ
Max
Units
If no calibration is performed
If calibration is performed
Periods of reference clock
27
31
32.768
32.768
42
34.5
65
kHz
kHz
Frequency
Calibration time
cycles
nA
Current consumption
200
To trim the RC-Oscillator, set the chip select (CS) to high before sending the direct command trim_osc over SDI. Then 65 digital clock cycles of
the reference clock (e.g. 32.768 kHz) have to be sent on the clock bus (SCL), as shown in Figure 22. After that the signal on the chip select (CS)
has to be pulled down.
The calibration is effective after the 65th reference clock edge and it will be stored in a volatile memory. In case the RC-oscillator is switched off
or a power-on-reset happens (e.g. battery change) the calibration has to be repeated.
Figure 22. RC-Oscillator Calibration via SDI
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AS3932
Data Sheet - Detailed Description
8.9.3 External Clock Source
To clock the AS3932 with an external signal the crystal oscillator has to be enabled (R1<1>=1). As shown in the Figure 3 the clock must be
applied on the pin XIN while the pin XOUT must stay floating. The RC time constant has to be 100μs with a tolerance of ±10% (e.g. R=680 kΩ
and C=22pF). In the Table 24 the clock characteristics are summarized.
Table 24. Characteristics of External Clock
Symbol
Parameter
Conditions
Min
Typ
Max
Units
0.1 *
VDD
VI
Low level
0
V
0.9 *
VDD
Vh
High level
VDD
V
Tr
Tf
Rise-time
Fall-time
3
3
µs
µs
µs
T=1/2πRC
RC Time constant
90
100
110
Note: In power down mode the external clock has to be set to VDD.
8.10 Channel Selection in Scanning Mode and ON/OFF Mode
In case only 2 channels are active and one of the Low Power modes is enabled, then the channels 1 and 3 have to be active. If the chip works in
On-Off mode and only one channel is active then the active channel has to be the channel 1.
Both Low Power modes are not allowed to be enabled at the same time.
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AS3932
Data Sheet - Package Drawings and Markings
9 Package Drawings and Markings
Figure 23. Package Diagram 16 pin TSSOP
Table 25. Package Dimensions 16 pin TSSOP
Symbol
A
Min
Typ
Max
1.10
0.15
0.95
Symbol
Min
Typ
Max
E
6.40 BSC
A1
A2
aaa
b
0.05
0.85
L
a
0.50
0º
0.60
4º
0.70
8º
0.90
0.076
N, P, P1
See Variations
0.19
0.19
-
0.22
0.30
0.25
Variations:
b1
D
P
1.59
3.1
3.0
4.2
P1
3.2
3.0
3.0
3.0
3.2
3.0
N
8
AA/AAT
AB-1/ABT-1
AB/ABT
AC/ACT
2.90
4.90
4.90
6.40
7.70
9.60
3.00
5.00
5.00
6.50
7.80
9.70
3.10
5.10
5.10
6.60
7.90
9.80
bbb
C
0.10
14
16
20
24
28
0.09
0.09
-
0.20
0.16
C1
D
0.127
See Variations
4.40
AD/ADT
5.5
E1
e
4.30
4.50
AE/AET
5.5
0.65 BSC
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AS3932
Data Sheet - Package Drawings and Markings
Note:
1. Die thickness allowable is 0.279 ± 0.0127.
2. Dimensioning and tolerances conform to ASME Y14.5M-1994.
3. Datum plane H located at mold parting line and coincident with lead, where lead exits plastic body at bottom of parting line.
4. Datum A-B and D to BE determined where center line between leads exits plastic body at datum plane H.
5. D & E1 are reference datum and do not include mold flash or protrusions, and are measured at the bottom parting line. Mold lash or pro-
trusions shall not exceed 0.15mm on D and 0.25mm on E per side.
6. Dimension is the length of terminal for soldering to a substrate.
7. Terminal positions are shown for reference only.
8. Formed leads shall be planar with respect to one another within 0.076mm at seating plane.
9. The lead width dimension does not include dambar protrusion. Allowable dambar protrusion shall be 0.07mm total in excess of the lead
width dimension at maximum material condition. Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusions and an adjacent lead should be 0.07mm for 0.65mm pitch.
10. Section B-B to be determined at 0.10mm to 0.25mm from the lead tip.
11. Dimensions P and P1 are thermally enhanced variations. Values shown are maximum size of exposed pad within lead count and body
size. End user should verify available size of exposed pad for specific device application.
12. All dimensions are in millimeters, angle is in degrees.
13. N is the total number of terminals.
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AS3932
Data Sheet - Package Drawings and Markings
Figure 24. Package Diagram QFN 4x4 16LD
5
6
7
8
4
3
9
1 0
2
1 1
1 2
# 1
1 6
1 5
1 4
1 3
Table 26. Package Dimensions QFN 4x4 16LD
Symbol
Min
Typ
0.85
Max
Symbol
Min
Typ
0.65 BSC
0.50
Max
A
A1
b
0.75
0.95
e
L
0.203 REF
0.30
0.40
0.60
0.10
0.25
0.35
L1
P
D
4.00 BSC
4.00 BSC
2.40
45º BSC
0.15
E
aaa
ccc
D2
E2
2.30
2.30
2.50
2.50
0.10
2.40
Note:
1. Die thickness allowable is 0.279 ± 0.0127.
2. Dimensioning and tolerances conform to ASME Y14.5M-1994.
3. Dimension b applies to metallized terminal and is measured between 0.25mm and 0.30mm from terminal tip. Dimension L1 represents
terminal full back from package edge up to 0.1mm is acceptable.
4. Coplanarity applies to the exposed heat slug as well as the terminal.
5. Radius on terminal is optional
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AS3932
Data Sheet - Revision History
Revision History
Table 27. Revision History
Revision
1.0
Date
Owner
esn
Description
Feb 12, 2009
Feb 24, 2009
1.0a
esn
Table 28 (Ordering information), -Z removed from part numbers
New figure inserted Figure 2 on page 2, all subsequent chapters and page numbers are
therefore incremented by one
1.1
Apr 2, 2009
esn
Default Values of RegistersTable 7, default value of R4<3:0> corrected
Bit Setting of Gain ReductionTable 14, stepsize of gain reduction increased to -4dBm
Description of external components on page 12 updated
1.11
1.12
Apr 22, 2009
May 25, 2009
esn
esn
Update of Section 10 Ordering Information on page 33
Updated Wakeup Protocol - Carrier Frequency 125 kHz 8.7 and description of Section
8.9.2 RC-Oscillator on page 27
1.13
July 13, 2009
esn
Updated Key Features for External Clock
Added Figure 3 AS3932 Typical Application Diagram with Clock from External Source
Added External Clock Source in Electrical System SpecificationsTable 5
1.2
Oct 13, 2009
mrh
Deleted table Minimum duration of carrier burst in ON/OFF mode (Manchester decoder
enabled)
Updated Real Time Clock (RTC) 8.9 with External Clock
Added External Clock Source 8.9.3
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AS3932
Data Sheet - Ordering Information
10 Ordering Information
Table 28. Ordering Information
Delivery Form1
Ordering Code
Type
Marking
Description
AS3932-BTST
AS3932-BQFT
16 pin TSSOP
QFN 4x4 16LD
AS3932
AS3932
Tape&Reel (AS3932 TSSOP)
Tape&Reel (AS3932 QFN)
Tape&Reel (1000 pcs)
Tape&Reel (1000 pcs)
1. Dry Pack Sensitivity Level =3 according to IPC/JEDEC J-STD-033A for full reels.
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