AS5050 [AMSCO]
Low Power 10-Bit Magnetic Rotary Encoder; 低功耗10位磁旋转编码器
| 型号： | AS5050 |
| 厂家： | 
AMS(艾迈斯) |
| 描述： | Low Power 10-Bit Magnetic Rotary Encoder |
| 文件： | 总22页 (文件大小：583K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet
AS5050
Low Power 10-Bit Magnetic Rotary Encoder
1 General Description
The AS5050 is a single-chip magnetic rotary encoder IC with low
voltage and low power features.
2 Key Features
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
10-bit resolution
Standard SPI interface, 3 or 4 wire
3.0 to 3.6 V core voltage, 1.8 to 3.6 V peripheral supply voltage
Automatic wakeup over SPI interface
Interrupt output for conversion complete indication
Low power mode:
It includes 4 integrated Hall elements, a high resolution ADC and a
smart power management controller.
The angle position, alarm bits and magnetic field information are
transmitted over a standard 3-wire or 4-wire SPI interface to the host
processor.
The AS5050 is available in a small QFN 16-pin 4x4x0.85mm
package and specified over an operating temperature of -40ºC to
80ºC.
- < 8mA (avg) @ 620µs readout interval
- < 5mA (avg) @ 1ms readout interval
- < 500µA (avg) @ 10ms readout interval
- < 53µA (avg) @ 100ms readout interval
Small size 16-pin QFN (4x4x0.85mm)
ꢀ
3 Applications
The device is ideal for Servo motor control, Input device for battery
operated portable devices, and Robotics.
Figure 1. AS5050 Block Diagram
AS5050
EN_INT/
INT/
ADC
Cordic
Hall Sensors
SPI Interface
VDDp
Power Management
VDD
VSS
Wire
MISO
MOSI SCK SS/
mode
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Revision 1.12
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AS5050
Datasheet - Contents
Contents
1 General Description ..................................................................................................................................................................
2 Key Features.............................................................................................................................................................................
3 Applications...............................................................................................................................................................................
4 Pin Assignments .......................................................................................................................................................................
4.1 Pin Descriptions....................................................................................................................................................................................
5 Absolute Maximum Ratings ......................................................................................................................................................
6 Electrical Characteristics...........................................................................................................................................................
1
1
1
3
3
4
5
6.1 Operating Conditions............................................................................................................................................................................
6.2 System Parameters..............................................................................................................................................................................
6.3 DC/AC Characteristics..........................................................................................................................................................................
7 Detailed Description..................................................................................................................................................................
7.1 Operating Modes..................................................................................................................................................................................
5
5
5
6
6
7.1.1 Power Supply Filter...................................................................................................................................................................... 6
7.1.2 Reading an Angle ........................................................................................................................................................................ 7
7.1.3 Low Power Mode......................................................................................................................................................................... 7
7.1.4 Interrupt Chaining ........................................................................................................................................................................ 7
7.2 SPI Communication..............................................................................................................................................................................
8
7.2.1 Command Package ..................................................................................................................................................................... 8
7.2.2 Read Package (Value Read from AS5050)................................................................................................................................. 8
7.2.3 Write Data Package (Value Written to AS5050).......................................................................................................................... 9
7.2.4 Register Block.............................................................................................................................................................................. 9
7.2.5 SPI Interface Commands........................................................................................................................................................... 10
8 Application Information ........................................................................................................................................................... 14
8.1 SPI Interface....................................................................................................................................................................................... 14
8.1.1 SPI Interface Signals (4-Wire Mode, Wire_mode = 1)............................................................................................................... 14
8.1.2 SPI Timing ................................................................................................................................................................................. 15
8.1.3 SPI Connection to the Host µC ................................................................................................................................................. 16
8.2 Placement of the Magnet.................................................................................................................................................................... 17
9 Package Drawings and Markings ........................................................................................................................................... 19
10 Ordering Information............................................................................................................................................................. 21
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AS5050
Datasheet - Pin Assignments
4 Pin Assignments
Figure 2. Pin Assignments (Top View)
16
15
14
13
1
2
3
4
12
11
10
9
MOSI
MISO
SCK
SS/
VDD
VDDp
Epad
En_INT/
Test_coil
5
6
7
8
4.1 Pin Descriptions
Table 1. Pin Descriptions
Pin Number
Pin Name
MOSI
MISO
SCK
Pin Type
Description
SPI bus data input
1
2
Digital input
SPI bus data output
SPI Clock Schmitt trigger
Digital output, tri-state buffer
Digital input Schmitt trigger
Digital input
3
SPI Slave Select, active LOW
4
SS/
5
tb0
6
tb1
Test pin, leave unconnected
Analog I/O
7
tb2
8
tb3
Test pin, connect to VSS
9
Test coil
En_INT/
VDDp
VDD
Supply
Enable / disable Interrupt
10
11
12
13
Digital input
Peripheral power supply, 1.8V ~ VDD
Analog and digital power supply, 3.0 ~ 3.6 V
Supply ground
Supply
VSS
0: 3-wire mode
1: 4-wire mode
14
Wire_mode
Digital I/O
Interrupt output. Active LOW, when conversion is finished
Test pin, leave unconnected
15
16
INT/
Test
-
Digital output, tri-state buffer
Digital I/O
-
Center pad not connected
Epad
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AS5050
Datasheet - Absolute Maximum Ratings
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of
the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 5 is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Units
Comments
Electrical Parameters
Value of these process dependent parameters
are according to Process Parameter document,
current version
VDD
DC supply voltage
-0.3
5.0
V
VDDp
Vin
Peripheral supply voltage
Input pin voltage
-0.3
-0.3
-100
VDD+0.3
5.0
V
V
Iscr
Input current (latchup immunity)
100
mA
Norm: Jedec 78
Electrostatic Discharge
ESD
Electrostatic discharge
Package thermal resistance
±1
-
-
kV
Norm: MIL 883 E method 3015
Velocity=0, Multi Layer PCB;
Jedec Standard Testboard
Theta_JA
33.5
°C/W
Continuous Power Dissipation
Pt
Temperature Ranges and Storage Conditions
Total power dissipation
36
mW
°C
Tstrg
Storage temperature
-55
125
The reflow peak soldering temperature (body
temperature) specified is in accordance with
IPC/JEDEC J-STD-020 “Moisture/Reflow
Sensitivity Classification for Non-Hermetic Solid
State Surface Mount Devices”.
Tbody
Package body temperature
260
85
°C
%
The lead finish for Pb-free leaded packages is
matte tin (100% Sn).
Humidity non-condensing
Moisture Sensitive Level
5
MSL
3
Represents a maximum floor life time of 168h
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AS5050
Datasheet - Electrical Characteristics
6 Electrical Characteristics
6.1 Operating Conditions
Table 3. Operating Conditions
Parameter
Conditions
Min
Typ
Max
Units
DC supply voltage
VDD
3.0
3.6
V
Peripheral supply voltage1
Input pin voltage
VDDp
Vin
1.8
VDD
V
-0.3
-40
2.2
15
VDDp +0.3
V
Ambient operating temperature
80
4.7
33
°C
µF
Ω
Power supply filter, pin VDD
(refer to Power Supply Filter on page 6)
External component
Ceramic capacitor, pin VDDp to VSS
100
nF
1. VDDp must not exceed VDD (protection diode between VDDp and VDD)
6.2 System Parameters
Table 4. System Parameters
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Average current @ 10 ms readout rate1
Average current @ 100 ms readout rate
Maximum readout rate
I_10
Operating current
0.5
mA
I_100
I_max
Operating current
Operating current
53
µA
mA
8.5
Time between READ ANGLE command and
INTERRUPT
Readout rate
320
430
µs
Power down current
Lateral displacement range
Magnetic field strength
Serial interface
Power down current
3
µA
mm
mT
Rd
BZ
Centre of the magnet to the centre of the die
-
± 0.5
80
30
-
SPI mode 0 (CPOL = 0 / CPHA =0)
10
Resolution; angle
bit
Best-fit line - over supply, displacement and
temperature – but without quantization
INL
-1.41
1.41
degree
IC package
QFN 4x4x0.85
1. Without the time for the SPI interface
6.3 DC/AC Characteristics
Digital pads: MISO, MOSI, SCK, SS/, EN_INT/, INT/, Wire_mode
Table 5. DC/AC Characteristics
Symbol
VIH
Parameter
Conditions
Min
Typ
Max
Units
V
High level input voltage
Low level input voltage
Low level input voltage
Input leakage current
High level output voltage
Low level output voltage
Capacitive load
0.7 * VDDp
VIL
VDDp > 2.7V
VDDp < 2.7V
0.3 * VDDp
0.25 * VDDp
1
V
VIL
V
ILEAK
VOH
VOL
CL
µA
V
VDDp - 0.5
VSS + 0.4
35
V
pF
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AS5050
Datasheet - Detailed Description
7 Detailed Description
User Programming.
The AS5050 does not require any programming by the user. A dedicated on-chip zero position programming is not implemented. If a zero
position programming is required, it is recommended to store the zero position offset in the host controller.
7.1 Operating Modes
Typical Application.
The AS5050 requires only a few external components in order to operate immediately when connected to the host microcontroller. Only 6 wires
are needed for a simple application using a single power supply: two wires for power and four wires for the SPI communication. A seventh
connection can be added in order to send an interrupt to the host CPU to inform that a new valid angle can be read.
Figure 3. Typical Application Using SPI 4-Wire Mode and INT/ Output
4µ7
DC 3. 0 ~3.6V
15ohm
VDD
AS5050
Supply: peripherals
Interrupt
INT/
ADC
Cordic
EN_INT/
VDDp
Hall Sensors
DC1.8~3.6V
µC
SPI Interface
Power Management
VDDp
100n
SS/
VSS
MOSI MISO
SCK
Test_coil
Wire
mode
SPI
Interface
VDDp
Upon power-up, the AS5050 performs a full power-up sequence including one angle measurement. The completion of this cycle is indicated at
the INT/ output pin and the angle value is stored in an internal register. Once this output is set, the AS5050 suspends to sleep mode.
7.1.1 Power Supply Filter
Due to the sequential internal sampling of the Hall sensors, fluctuations on the analog power supply (pin#12: VDD) may cause additional jitter of
the measured angle. This jitter can be avoided by providing a stable VDD supply.
The easiest way to achieve that is to add a RC filter: 15Ω + 4.7µF in the power supply line as shown in Figure 3.
Alternatively, a filter: 33Ω + 2.2µF may be used. However with this configuration, the minimum supply voltage is 3.15V.
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AS5050
Datasheet - Detailed Description
7.1.2 Reading an Angle
The external microcontroller can respond to the INT request by reading the angle value from the AS5050 over the SPI interface. Once the angle
value is read, the INT output is cleared again.
Sending a “read angle” command by the SPI interface also automatically powers up the chip and starts another angle measurement. As soon ad
the microcontroller has completed reading of the angle value, the INT output is cleared and a new result is stored in the angle register. The
completion of the angle measurement is again indicated by setting the INT output and a corresponding flag in the status register.
Reducing the Angle Jitter. Due to the measurement principle of the chip, only a single angle measurement is performed in very short time
(~600µs) after each power-up sequence. As soon as the measurement of one angle is completed, the chip suspends to power-down state. An
on-chip filtering of the angle value by digital averaging is not implemented, as this would require more than one angle measurement and
consequently, a longer power- up time which is not desired in low-power applications.
The angle jitter can be reduced by averaging of several angle samples in the external microcontroller. For example, an averaging of 4 samples
reduces the jitter by 6dB (50%).
7.1.3 Low Power Mode
After completing the readout of an angle value, the device is in very low power condition. The AS5050 remains in sleep mode until it receives
another angle reading request over the SPI interface. The average power consumption therefore depends on the interval, at which the external
controller reads an angle over the SPI Interface. The timing ratio between active and sleep phase:
(EQ 1)
ton ∗ Ion + toff ∗ Ioff
Iavg
=
ton + toff
Where:
ton = Minimum on-time for power-up and angle measurement
off = Pause interval between measurements, determined by the polling rate of the external microcontroller
Ion = Current consumption in active mode
off = Current consumption in sleep mode
600µs
t
8mA avg.
3µA
I
Examples:
3000 measurements per second (continuous mode)
1000 measurements per second
100 measurements per second
10 measurements per second
I = 8mA
Iavg = 5mA
Iavg = 500µA
Iavg = 53µA
Note: Even in low power mode, the power supply must be capable of supporting the active current at least for the time Ton, until the AS5050
is suspended to sleep mode.
7.1.4 Interrupt Chaining
Every chip contains a configurable gate to combine its own internally generated interrupt signal with a signal applied externally over the XENINT-
pin. The INT-mode register is preset via an OTP register can be overwritten by the SPI interface.
Case A.
Device A is set to mode 0
Device B is set to mode 0
The micro controller recognizes an interrupt if both devices signalize that the computation is finished.
Case B.
Device A is set to mode 0
Device B is set to mode 1
The micro controller recognizes an interrupt if one of the two devices signalize that the computation is finished.
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AS5050
Datasheet - Detailed Description
Figure 4. Interrupt Chaining
XINT
XINT
XINT
XENINT
XENINT
=1
&
=1
&
0
1
0
1
INT
mode
INT
mode
Micro
controller
AS5050 (Device A)
AS5050 (Device B)
7.2 SPI Communication
The transmitted data consists of 14-bit data, an Error-Flag and a Parity bit. When writing data to the chip, the Error-Flag is not applicable. The
Parity is generated from the upper 15-bit and forms an even parity over the whole frame. The Error-Flag indicates that a failure occurred in a
previous transmission.
7.2.1 Command Package
Every command sent to the AS5050 is represented with the following layout.
Table 6. Command Package
Bit
MSB
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
RWn
Address <13:0>
PAR
Bit
Description
RWn
Indicates read or write command
14-bit address code
Address
PAR
Parity bit (EVEN)
7.2.2 Read Package (Value Read from AS5050)
The read frame always contains two alarm bits, the error and parity flags and the addressed data of the previous read command.
Table 7. Read Package
Bit
MSB
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
Data <13:0>
EF
PAR
Bit
Description
14-bit addressed data
Data
Error flag indicating a transmission error in a previous host
transmission
EF
PAR
Parity bit (EVEN)
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AS5050
Datasheet - Detailed Description
7.2.3 Write Data Package (Value Written to AS5050)
The write frame is compatible to the read frame and contains two additional bits, the don’t care and parity flag.
If the previous command was a write command a second package has to be transmitted.
Table 8. Write Package
Bit
MSB
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
Data <13:0>
Don’t care PAR
Bit
Description
Data
PAR
14-bit data to write to former selected address
Parity bit (EVEN)
7.2.4 Register Block
Table 9. Register Block
Register
Bit
Mode
Reset Value
Bit
Description
Power ON Reset (POR) Register - [0x3F22]
The POR cell is deactivated when the value 0x5A is
written to this register (30µA reduction of current
consumption)
POR_OFF
8
R/W
0x00
<7:0>
Software Reset Register - [0x3C00]
software_reset 14
Clear Error Flag Register - [0x3380]
clr_error_flag 14
No Operation Register - [0x0000]
NOP 14
Refer to SOFTWARE RESET Command on page 12
Refer to CLEAR ERROR FLAG Command on page 11
Refer to NOP Command on page 13
W
R
0x0
0x0
0x0
<13:0>
<13:0>
<13:0>
w
Automatic Gain Control (AGC) Register - [0x03FF8]
Automatic gain control:
low values = strong magnetic field
high values = weak magnetic field
AGC
6
R/W
0x20
<5:0>
Angular Data - [0x3FFF]
Measured angular value, 10-bit
Angle Value
10
1
R
R
0x000
0
<9:0>
<12>
Alarm bit indicating a too low magnetic field, active
HIGH1
Alarm LO
Alarm bit indicating a too high magnetic field, active
HIGH1
Alarm HI
1
1
R
0
0
<13>
<1>
Breaks the offset compensation loop to use the offset
registers in a static mode
break_offset_loop
R/W
Interrupt gate mode
0 = mode 0
interrupt_mode
1
R/W
0
<0>
1 = mode1
1. Both bits High: Alarm LO = Alarm Hi = 1 indicate a major system error (DAC overflow, CORDIC overflow or Hall current error).
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AS5050
Datasheet - Detailed Description
7.2.5 SPI Interface Commands
READ Command. For a single READ command two transmission sequences are necessary. The first package written to the AS5050 contains
the READ command (MSB high) and the address the chip has to access, the second package transmitted to the AS5050 device can be any
command the chip has to process next. The content of the desired register is available in the MISO register of the master device at the end of the
second transmission cycle.
Figure 5. READ Command
T COM
MSB
LSB
MSB
LSB
MOSI
MISO
READ
Next command
Response on
READ command
Response - 1
MSB
LSB
MSB
LSB
Transmission N
Transmission N +1
WRITE Command. A single WRITE command takes two transmission cycles. With a NOP command after the WRITE command you can
verify the sent data with three transmission cycles because the data will be send back during the NOP command.
Figure 6. WRITE Command
T
COM
MSB
LSB
MSB
LSB
MSB
LSB
MOSI
MISO
WRITE
command
DATA
Next command
Old register
content
New register
content
Response-1
MSB
LSB
MSB
LSB
MSB
LSB
Transmission N
Transmission N +1
Transmission N +2
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AS5050
Datasheet - Detailed Description
CLEAR ERROR FLAG Command. The CLEAR ERROR FLAG command is implemented as READ command. This command clears the
ERROR FLAG which is contained in every READ frame. The READ data are 0x0000, which indicates a successful clear command.
Figure 7. CLEAR ERROR FLAG Command
TCOM
MSB
LSB
MSB
LSB
MOSI
MISO
CLEAR ERROR
FLAG
Next command
Response-1
0x 0000
MSB
LSB
MSB
LSB
Transmission N
Transmission N +1
The package necessary to perform a CLEAR ERROR FLAG is built up as follows.
Table 10. CLEAR ERROR FLAG Command
Bit
MSB
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
PAR
PAR
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
CLEAR ERROR FLAG command
Possible conditions which force the ERROR FLAG to be set:
ꢀ
ꢀ
ꢀ
Wrong parity
Wrong command
Wrong number of clocks (no full transmission cycle or too many clocks)
Note: If the error flag is set to high because of a communication problem the flag remains set until it will be cleared by an external command.
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AS5050
Datasheet - Detailed Description
SOFTWARE RESET Command. The SOFTWARE RESET command is implemented as WRITE command. The bit ‘RES SPI’ of the DATA
package indicates if the SPI registers should be reset as well. The soft reset resets the digital part (‘RES SPI’ is set to one) as well as the
PPTRIM. A new PPTRIM auto-load is initiated and the reset values stored in the PPTRIM are loaded into the configuration registers. The
command following the SOFTWARE RESET command can be any of the commands specified in this chapter.
After the data package is sent, the soft reset is generated. The fuses of the PPTRIM are loaded into the registers and a new conversion cycle will
be started. If the device is in sleep mode the oscillator will be started first.
Figure 8. SOFTWARE RESET Command
T
COM
MSB
LSB
MSB
LSB
MSB
LSB
SOFTWARE
RESET
command
MOSI
MISO
DATA
Next command
Response-1
0x 0000
0x 0000
MSB
LSB
MSB
LSB
MSB
LSB
Transmission N
Transmission N +1
Transmission N +2
In order to invoke a software reset on the AS5050 the following bit pattern has to be sent.
Table 11. SOFTWARE RESET Command
Bit
MSB
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
PAR
PAR
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
SOFTWARE RESET command
Table 12. Data Package
Bit MSB 14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
Don’t care
RES SPI Don’t care PAR
Bit
Description
If set to one, SPI registers are reset as well1
Parity bit (EVEN)
RES SPI
PAR
1. After a power on reset, the OTP will be read and hence OTP related
registers are changed independent on the RES SPI flag.
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AS5050
Datasheet - Detailed Description
NOP Command. The NOP command represents a dummy write to the AS5050.
Figure 9. NOP Command
T
COM
MSB
LSB
MSB
LSB
MSB
LSB
MOSI
MISO
NOP
NOP
Next command
Response-1
0x0000
0x0000
MSB
LSB
MSB
LSB
MSB
LSB
Transmission N
Transmission N +1
Transmission N +2
The NOP command frame looks like follows.
Table 13. NOP Command
Bit
MSB
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NOP command (0x0000)
The chip’s response on this command is 0x0000 – if no error happens.
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AS5050
Datasheet - Application Information
8 Application Information
The benefits of the AS5050 device are as follows:
ꢀ
ꢀ
ꢀ
ꢀ
Complete system-on-chip
Low power consumption
Low operating voltage
Easy to use SPI interface
8.1 SPI Interface
The 16-bit SPI Interface enables read / write access to the register blocks and is compatible to a standard micro controller interface. The SPI
module is active as soon as /SS pin is pulled low. The AS5050 then reads the digital value on the MOSI (master out slave in) input with every
falling edge of SCK and writes on its MISO (master in slave out) output with the rising edge. After 16 clock cycles /SS has to be set back to a high
status in order to reset some parts of the interface core.
The SPI Interface can be set into two different modes - 3-wire mode or 4-wire mode.
Note: The wire mode selection is read during the POWER-UP state and can be changed with a power on reset or a software reset command.
The SPI Interface can be set into two different modes: 3-wire mode or 4-wire mode.
Table 14. Wire Mode Selection
Wire Mode Selection (pad 14)
wire_mode = LO
wire_mode = HI
3-wire mode
4-wire mode
8.1.1 SPI Interface Signals (4-Wire Mode, Wire_mode = 1)
The AS5050 only supports slave operation mode. Therefore SCK for the communication as well as the /SS signal has to be provided by the test
equipment. The following picture shows a basic interconnection diagram with one master and an AS5050 device and a principle schematic of the
interface core.
Figure 10. SPI Interface Connection
SCK
SPI_CLK
SS/
SPI_SSN
MOSI
MOSI
Interface Core
RXSR
RXSPI
Master Device
(Tester)
TXSPI
TXSR
MISO
MISO
AS5050
Because the interface has to decode the sent command before it can react and provide data the response of the chip to a specific command
applied at a time T can be accessed in the next transmission cycle ending at T + TCOM.
The data are sent and read with MSB first. Every time the chip is accessed it is sending and receiving data.
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AS5050
Datasheet - Application Information
Figure 11. SPI Command / Response Data Flow
T
COM
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MOSI
MISO
Command 1
0x00
Command 2
Response 1
Command N - 1
Response 2
Command N
Response N - 1
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
Transmission 1
Transmission 2
Transmission N - 1
Transmission N
8.1.2 SPI Timing
Figure 12. SPI Timing Diagram
t XSSH
SS/
( Input )
tL
tsck
t sckL
t sckH
tH
SCK
( Input )
t MISO
tOZ
MISO
data[ 15]
data[ 14]
data[0]
( Output )
tOZ
t MOSI
MOSI
data[ 15]
data[ 14]
data[0]
( Input )
Table 15. SPI Timing Characteristics
Parameter
Description
Min
Max
Unit
101
tL
Time between SS/ falling edge and SCK rising edge
ns
3502
100
50
tL
Time between SS/ falling edge and SCK rising edge
Serial clock period
ns
ns
ns
ns
ns
tSCK
tSCKL
tSCKH
tH
Low period of serial clock
High period of serial clock
50
t
SCK / 2
Time between last falling edge of SCK and rising edge of SS/
101
tXSSH
High time of SS/ between two transmissions
High time of SS/ between two transmissions
ns
ns
3502
20
tXSSH
tMOSI
tMISO
Data input valid to clock edge
SCK edge to data output valid
ns
ns
20
1. No synchronization needed because the internal clock is inactive
2. Synchronization with the internal clock → 2 * tCLK_SYS + 10 ns (e.g. at 8 MHz → 253 ns)
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Revision 1.12
15 - 22
AS5050
Datasheet - Application Information
8.1.3 SPI Connection to the Host µC
Single Slave Mode.
Figure 13. Single Slave Mode
0xFFFF
Write CMD
0xFFFF
Write CMD
0xFFFF
Write CMD
0xFFFF
Write CMD
0xFFFF
Write CMD
0xFFFF
Write CMD
Write CMD
MOSI
MISO
SS/
...
Read angle1 Read angle2 Read angle 3 Read angle4 Read angle5 Read angle6
NOP
MOSI
MISO
SCK
SS/
MOSI
MISO
SCK
SS/
Angle1
Angle2
Angle3
Angle4
Angle5
Angle6
UC
UC
UC
AS5050
Wire_Mode
1
1
4-wire mode
MOSI
MISO
MISO
SS/
...
Angle 1
Angle 2
Angle3
Angle4
Angle5
Angle6
Angle7
MISO
SCK
SS/
AS5050
SCK
SS/
Wire_Mode
1
3-wire mode(Read only )
0xFFFF
0xFFFF
0xFFFF
0xFFFF
Write CMD
Write CMD
Write CMD
Write CMD
SISO
MISO
MOSI
SISO
SS/
Angle 1
Angle 2
Angle 3
Angle 4
Read angle1
Read angle2
Read angle3
Read angle 4
AS5050
SCK
SS/
SCK
SS/
3-wire mode(Bi- dir)
Wire_Mode
0
Note: 3-Wire Mode (read only): If the ERROR FLAG is set the device must be externally reset.
Multiple Slave, n+3 Wire (Separate ChipSelect).
Figure 14. Multiple Slave, n+3 Wire (Separate ChipSelect)
0xFFFF
0xFFFF
0xFFFF
0xFFFF
xx
Write CMD
Write CMD
Write CMD
Write CMD
Write CMD
UC MOSI
xx
xx
MOSI
MISO
SW reset
Read angle1
Read angle2
Read angle3
NOP
MOSI
MISO
SCK
AS5050
I
UC MISO
SS1/
...
Angle 1
Angle 2
Angle 3
SCK
SS/
UC
SS1/
SS2/
SS3/
Wire_Mode
1
SS2/
SS2/
MOSI
MISO
AS5050
II
SCK
SS/
Wire_Mode
1
MOSI
MISO
AS5050
III
SCK
SS /
Wire_Mode
1
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Revision 1.12
16 - 22
AS5050
Datasheet - Application Information
Daisy Chain, 4 Wire.
Figure 15. Daisy Chain, 4-Wire
Write CMD
Write CMD
Write CMD
UC MOSI
MOSI
MISO
SW reset
SW reset
SW reset
MOSI
MISO
SCK
SS/
AS5050
I
...
UC MISO
SS/
SCK
SS/
UC
Wire_Mode
1
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
Read angle3 Read angle2 Read angle1 Read angle3 Read angle2 Read angle1
...
...
...
UC MOSI
MOSI
MISO
Angle3
Angle2
Angle1
Angle3
Angle2
Angle1
UC MISO
SS/
AS5050
II
SCK
SS/
Wire_Mode
1
MOSI
MISO
AS5050
III
SCK
SS/
Wire_Mode
1
8.2 Placement of the Magnet
Non-Linearity Error over Displacement.
As shown in Figure 17, the recommended horizontal position of the magnet axis is over the diagonal center of the IC.
Figure 16 shows a typical error curve at a vertical magnet distance of 1.0mm, measured with a NdFeB N35H magnet with 6mm diameter and
2.5mm height.
The X- and Y- axis of the graph indicate the lateral displacement of the magnet center with respect to the IC center.
At X = Y = 0, the magnet is perfectly centered over the IC. The total displacement plotted on the graph is for ±1mm in both directions.
The Z-axis displays the worst case INL error over a full turn at each given X-and Y- displacement. The error includes the quantization error of ±½
LSB. At the sample shown in Figure 16, the accuracy for a centered magnet is better than 0.5°. Within a radius of 0.5mm, the accuracy is about
1.0° (spec = 1.41° over temperature).
www.austriamicrosystems.com
Revision 1.12
17 - 22
AS5050
Datasheet - Application Information
Figure 16. Integral Non-linearity Over Displacement of the Magnet
Non-Linearity @ z=1mm
4
3.5
3
2.5
3.5-4
3-3.5
2.5-3
2-2.5
1.5-2
1-1.5
0.5-1
0-0.5
2
0.8
1.5
INL [°]
0.5
0.2
1
0.5
0
-0.1
Y-displacement [mm]
-0.4
-0.7
-1.0
X-displacement [mm]
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Revision 1.12
18 - 22
AS5050
Datasheet - Package Drawings and Markings
9 Package Drawings and Markings
The device is available in a 16-pin QFN (4x4x0.85mm) package.
Figure 17. Package Drawing and Hall Sensor Location
D
A 1 /2
A1
Dx
Dz
TOP
VIEW
YYWWXZZ
AS5050
center of die
Hall sensor
array
D1
A
Pin 1
indicator
13
16
12
9
1
4
L
BOTTOM
VIEW
L1
e
8
b
L
e
Symbol Min
Nom
Max
0.90
0.05
0.35
Symbol Min
Nom
Max Notes
A
A1
b
0.80
0.00
0.25
0.85
e
L
-
0.65 BSC
0.45
-
Notes:
0.40
0.50
0.10
1. Center of die to package edge
0.30
4.00 BSC
4.00 BSC
2.60
L1
Dx
Dy
Dz
r
2. Center of die to package edge
3. Surface of die to package surface
4. Radius of Hall array
D
1.85
1.85
2.00
2.00
2.15
2.15
1
2
3
4
E
D1
E1
2.50
2.50
2.70
2.70
0.323
0.383
1.00
0.443
2.60
Marking: YYWWXZZ.
YY
WW
Week
X
ZZ
Year (i.e. 04 for 2004)
Assembly plant identifier
Assembly traceability code
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Revision 1.12
19 - 22
AS5050
Datasheet - Revision History
Revision History
Revision
Date
17 Feb, 2011
Owner
Description
1.12
mub
Latest draft
Note: Typos may not be explicitly mentioned under revision history.
www.austriamicrosystems.com
Revision 1.12
20 - 22
AS5050
Datasheet - Ordering Information
10 Ordering Information
The devices are available as the standard products shown in Table 16.
Table 16. Ordering Information
Ordering Code
Description
Delivery Form
Package
AS5050-EQFT
10-bit low power magnetic rotary encoder
Tape & Reel
16-pin QFN (4x4x0.85mm)
Note: All products are RoHS compliant and Pb-free.
Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect
Technical Support is available at http://www.austriamicrosystems.com/Technical-Support
For further information and requests, please contact us mailto: sales@austriamicrosystems.com
or find your local distributor at http://www.austriamicrosystems.com/distributor
www.austriamicrosystems.com
Revision 1.12
21 - 22
AS5050
Datasheet - Copyrights
Copyrights
Copyright © 1997-2011, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®.
All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of
the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale.
austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding
the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at
any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for
current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range,
unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are
specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100
parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location.
The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not
be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use,
interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing,
performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of
austriamicrosystems AG rendering of technical or other services.
Contact Information
Headquarters
austriamicrosystems AG
Tobelbaderstrasse 30
A-8141 Unterpremstaetten, Austria
Tel: +43 (0) 3136 500 0
Fax: +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit:
http://www.austriamicrosystems.com/contact
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Revision 1.12
22 - 22
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