AS5055_技术文档

AS5055

Low Power 12-Bit Magnetic Rotary Encoder

1 General Description

The AS5055 is a single-chip magnetic rotary encoder IC with low

voltage and low power features.

2 Key Features

12-bit resolution

Standard SPI interface, 3 or 4 wire

It includes 4 integrated Hall elements, a high resolution ADC and a

smart power management controller.

3.0V to 3.6V core voltage, 1.8V to 3.6V peripheral supply

voltage

The angle position, alarm bits and magnetic field information are

transmitted over a standard 3-wire or 4-wire SPI interface to the host

processor.

Automatic wake-up over SPI interface

Interrupt output for conversion complete indication

Low power mode:

The AS5055 is available in a small QFN 16-pin 4x4x0.85 mm

package and specified over an operating temperature of -40ºC to

+85ºC.

- < 5mA (avg) @ 1ms readout interval

- < 500µA (avg) @ 10ms readout interval

- < 53µA (avg) @ 100ms readout interval

Small size 16-pin QFN (4x4x0.85 mm)

3 Applications

The device is ideal for Servo motor control, Input device for battery

operated portable devices, and Robotics.

Figure 1. AS5055 Block Diagram

EN_INT/

AS5055

INT/

ADC

Cordic

Hall Sensors

SPI Interface

VDDp

Power Management

Wire

mode

VSS

VDD

MOSI MISO SCK

SS/

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AS5055

Datasheet - Contents

Contents

1 General Description ..................................................................................................................................................................

2 Key Features.............................................................................................................................................................................

3 Applications...............................................................................................................................................................................

4 Pin Assignments .......................................................................................................................................................................

4.1 Pin Descriptions....................................................................................................................................................................................

5 Absolute Maximum Ratings ......................................................................................................................................................

6 Electrical Characteristics...........................................................................................................................................................

6.1 Operating Conditions............................................................................................................................................................................

6.2 System Parameters..............................................................................................................................................................................

6.3 DC/AC Characteristics..........................................................................................................................................................................

7 Detailed Description..................................................................................................................................................................

1

3

4

5

6

7

7.1 Operating Modes..................................................................................................................................................................................

7

7.1.1 Power Supply Filter...................................................................................................................................................................... 7

7.1.2 Reading an Angle ........................................................................................................................................................................ 8

7.1.3 Low Power Mode......................................................................................................................................................................... 8

7.1.4 Interrupt Chaining ........................................................................................................................................................................ 8

7.2 SPI Communication..............................................................................................................................................................................

9

7.2.1 Command Package ..................................................................................................................................................................... 9

7.2.2 Read Package (Value Read from AS5055)................................................................................................................................. 9

7.2.3 Write Data Package (Value Written to AS5055)........................................................................................................................ 10

7.2.4 Register Block............................................................................................................................................................................ 10

7.2.5 SPI Interface Commands........................................................................................................................................................... 11

7.2.6 Error Monitoring.......................................................................................................................................................................... 14

8 Application Information ........................................................................................................................................................... 16

8.1 SPI Interface....................................................................................................................................................................................... 16

8.1.1 SPI Interface Signals (4-Wire Mode, Wire_mode = 1)............................................................................................................... 16

8.1.2 SPI Timing ................................................................................................................................................................................. 17

8.1.3 SPI Connection to the Host µC ................................................................................................................................................. 18

8.1.4 SPI Over Long Distances .......................................................................................................................................................... 20

8.2 Placement of the Magnet.................................................................................................................................................................... 21

9 Package Drawings and Markings ........................................................................................................................................... 22

10 Ordering Information............................................................................................................................................................. 25

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AS5055

Datasheet - Pin Assignments

4 Pin Assignments

Figure 2. Pin Assignments (Top View)

16

15

14

13

1

2

3

4

12

11

10

9

MOSI

MISO

SCK

SS/

VDD

VDDp

Epad

En_INT/

Test_coil

5

6

7

8

4.1 Pin Descriptions

Table 1. Pin Descriptions

Pin Number

Pin Name

MOSI

MISO

SCK

Pin Type

Description

SPI bus data input

1

2

Digital input

SPI bus data output

SPI Clock Schmitt trigger

Digital output, tri-state buffer

Digital input Schmitt trigger

Digital input

3

SPI Slave Select, active LOW

4

SS/

5

NC

6

NC

Leave unconnected

-

7

NC

8

NC

Test pin, connect to VSS

9

Test coil

En_INT/

VDDp

VDD

Supply

Enable / disable Interrupt

10

11

12

13

Digital input

Peripheral power supply, 1.8V ~ VDD

Analog and digital power supply, 3.0 ~ 3.6V

Supply ground

Supply

VSS

0: 3-wire mode

1: 4-wire mode

14

Wire_mode

Digital I/O

Interrupt output. Active LOW, when conversion is finished

Leave unconnected

15

16

INT/

NC

-

Digital output, tri-state buffer

-

Center pad not connected

Epad

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AS5055

Datasheet - Absolute Maximum Ratings

5 Absolute Maximum Ratings

Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of

the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 5 is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

Table 2. Absolute Maximum Ratings

Symbol

Parameter

Min

Max

Units

Comments

Electrical Parameters

Value of these process dependent parameters

to be taken from according Process Parameter

document, current version

VDD

DC supply voltage

-0.3

5.0

V

VDDp

Peripheral supply voltage

Input pin voltage

-0.3

-100

VDD+0.3

5.0

V

VIN

I_scr

Input current (latchup immunity)

100

mA

Norm: Jedec 78

Electrostatic Discharge

ESD

Electrostatic discharge

±1

-

kV

Norm: MIL 883 E method 3015

Velocity=0, Multi Layer PCB;

Jedec Standard Testboard

Θ_JA

Package thermal resistance

33.5

°C/W

Continuous Power Dissipation

P_t

Temperature Ranges and Storage Conditions

Total power dissipation

36

mW

°C

T_strg

Storage temperature

-55

125

The reflow peak soldering temperature (body

temperature) specified is in accordance with

IPC/JEDEC J-STD-020 “Moisture/Reflow

Sensitivity Classification for Non-Hermetic Solid

State Surface Mount Devices”.

TBODY

Package body temperature

260

85

°C

%

The lead finish for Pb-free leaded packages is

matte tin (100% Sn).

Humidity non-condensing

Moisture Sensitive Level

5

MSL

3

Represents a maximum floor life time of 168h

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AS5055

Datasheet - Electrical Characteristics

6 Electrical Characteristics

6.1 Operating Conditions

Table 3. Operating Conditions

Parameter

Conditions

Min

Typ

Max

Units

DC supply voltage

VDD

3.0

3.6

V

Peripheral supply voltage¹

Input pin voltage

VDDp

1.8

VDD

V

VIN

-0.3

-40

2.2

15

VDDp +0.3

V

Ambient operating temperature

85

4.7

33

°C

µF

Ω

Power supply filter, pin VDD

(refer to Power Supply Filter on page 7)

External component

Ceramic capacitor, pin VDDp to VSS

100

nF

1. VDDp must not exceed VDD (protection diode between VDDp and VDD)

6.2 System Parameters

Table 4. System Parameters

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Average current @ 10 ms readout rate¹

Average current @ 100 ms readout rate

Maximum readout rate

I_10

Operating current

0.4

mA

I_100

I_max

Operating current

40

µA

mA

8.5

Time between READ ANGLE command and

INTERRUPT

Readout rate

320

430

µs

Power down current

Lateral displacement range

Magnetic field strength

Serial interface

Power down current

3

µA

mm

mT

Rd

B_Z

Centre of the magnet to the centre of the die

-

± 0.5

80

30

-

SPI mode 1 (CPOL = 0 / CPHA =1)

12

Resolution; magnetic field

measurement

bit

Resolution; angle

INL

12

Best-fit line - over supply, displacement and

temperature – but without quantization

-1.41

1.41

degree

IC package

QFN 4x4x0.85

1. Without the time for the SPI interface

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AS5055

Datasheet - Electrical Characteristics

6.3 DC/AC Characteristics

Digital pads: MISO, MOSI, SCK, SS/, EN_INT/, INT/, Wire_mode

Table 5. DC/AC Characteristics

Symbol

V_IH

Parameter

Conditions

Min

Typ

Max

Units

V

High level input voltage

Low level input voltage

Input leakage current

High level output voltage

Low level output voltage

Capacitive load

0.7 * VDDp

V_IL

VDDp > 2.7V

VDDp < 2.7V

0.3 * VDDp

0.25 * VDDp

1

V

V_IL

V

I_LEAK

V_OH

V_OL

C_L

µA

V

VDDp - 0.5

VSS + 0.4

35

V

pF

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AS5055

Datasheet - Detailed Description

7 Detailed Description

User Programming.

The AS5055 does not require any programming by the user. A dedicated on-chip zero position programming is not implemented. If a zero

position programming is required, it is recommended to store the zero position offset in the host controller.

7.1 Operating Modes

Typical Application.

The AS5055 requires only a few external components in order to operate immediately when connected to the host microcontroller. Only 6 wires

are needed for a simple application using a single power supply: two wires for power and four wires for the SPI communication. A seventh

connection can be added in order to send an interrupt to the host CPU to inform that a new valid angle can be read. For additional information on

the layout and filtering of the SPI, please refer to Section 8.1.4 SPI Over Long Distances.

Figure 3. Typical Application Using SPI 4-Wire Mode and INT/ Output

15 ohm

VDD

4µ7

DC 3.0V ~ 3.6V

VDD

AS5055

Supply: peripherals

Interrupt

INT/

EN_INT/

ADC

Cordic

Hall Sensors

µC

SPI Interface

VDDp

Power Management

VDDp

100n

SS/

VSS

Test_coil

Wire

mode

SPI

Interface

VDDp

Upon power-up, the AS5055 performs a full power-up sequence including one angle measurement. The completion of this cycle is indicated at

the INT/ output pin and the angle value is stored in an internal register. Once this output is low active, the AS5055 suspends to sleep mode.

7.1.1 Power Supply Filter

Due to the sequential internal sampling of the Hall sensors, fluctuations on the analog power supply (pin#12: VDD) may cause additional jitter of

the measured angle. This jitter can be avoided by providing a stable VDD supply.

The easiest way to achieve that is to add a RC filter: 15Ω + 4.7µF in the power supply line as shown in Figure 3.

Alternatively, a filter: 33Ω + 2.2µF may be used. However with this configuration, the minimum supply voltage is 3.15V.

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AS5055

Datasheet - Detailed Description

7.1.2 Reading an Angle

The external microcontroller can respond to the INT request by reading the angle value from the AS5055 over the SPI interface. Once the angle

value is read, the INT output is cleared again.

Sending a “read angle” command by the SPI interface also automatically powers up the chip and starts another angle measurement. As soon as

the microcontroller has completed reading of the angle value, the INT output is cleared and a new result is stored in the angle register. The

completion of the angle measurement is again indicated by setting the INT output and a corresponding flag in the status register.

Reducing the Angle Jitter. Due to the measurement principle of the chip, only a single angle measurement is performed in very short time

after each power-up sequence. As soon as the measurement of one angle is completed, the chip suspends to power-down state. An on-chip

filtering of the angle value by digital averaging is not implemented, as this would require more than one angle measurement and consequently, a

longer power- up time which is not desired in low-power applications.

The angle jitter can be reduced by averaging of several angle samples in the external microcontroller. For example, an averaging of 4 samples

reduces the noise related jitter by 6dB (50%).

7.1.3 Low Power Mode

After completing the readout of an angle value, the device is in very low power condition. The AS5055 remains in sleep mode until it receives

another angle reading request over the SPI interface. The average power consumption therefore depends on the interval, at which the external

controller reads an angle over the SPI Interface. The timing ratio between active and sleep phase:

(EQ 1)

t_on∗ I_on+ t_off∗ I_off

I_avg

=

t_on+ t_off

Where:

t_on= Minimum on-time for power-up and angle measurement

t_off= Pause interval between measurements, determined by the polling rate of the external microcontroller

_on= Current consumption in active mode

430µs

I

8.5mA (maximum)

3µA

I_off= Current consumption in sleep mode

Examples:

3000 measurements per second (continuous mode)

1000 measurements per second

100 measurements per second

10 measurements per second

I = 8.5mA

Iavg = 3.7mA

Iavg = 370µA

Iavg = 40µA

Note: Even in low power mode, the power supply must be capable of supporting the active current at least for the time T_on, until the AS5055

is suspended to sleep mode.

7.1.4 Interrupt Chaining

Every chip contains a configurable gate to combine its own internally generated interrupt signal with a signal applied externally over the XENINT-

pin. The INT-mode register is preset via an OTP register and can be overwritten by the SPI interface.

Case A.

Device A is set to mode 0

Device B is set to mode 0

The micro controller recognizes an interrupt if both devices signalize that the computation is finished.

Case B.

Device A is set to mode 0

Device B is set to mode 1

The micro controller recognizes an interrupt if one of the two devices signalize that the computation is finished.

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AS5055

Datasheet - Detailed Description

Figure 4. Interrupt Chaining

XINT

XENINT

=1

&

=1

&

0

1

0

1

INT

mode

INT

mode

Micro

controller

AS5055 (Device A)

AS5055 (Device B)

7.2 SPI Communication

The transmitted data consists of 14-bit data, an Error-Flag and a Parity bit. When writing data to the chip, the Error-Flag is not applicable. The

Parity is generated from the upper 15 bits and forms an even parity over the whole frame. The Error-Flag indicates that a failure occurred in a

previous transmission.

7.2.1 Command Package

Every command sent to the AS5055 is represented with the following layout.

Table 6. Command Package

Bit

MSB

14

13

12

11

10

9

8

7

6

5

4

3

2

1

LSB

RWn

Address <13:0>

PAR

Bit

Description

RWn

Indicates read or write command

14-bit address code

Address

PAR

Parity bit (EVEN)

7.2.2 Read Package (Value Read from AS5055)

The read frame always contains two alarm bits, the error and parity flags and the addressed data of the previous read command.

Table 7. Read Package

Bit

MSB

14

13

12

11

10

9

8

7

6

5

4

3

2

1

LSB

Data <13:0>

EF

PAR

Bit

Description

14-bit addressed data

Data

Error flag indicating a transmission error in a previous host

transmission

EF

PAR

Parity bit (EVEN)

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AS5055

Datasheet - Detailed Description

7.2.3 Write Data Package (Value Written to AS5055)

The write frame is compatible to the read frame and contains two additional bits, the don’t care and parity flag.

If the previous command was a write command a second package has to be transmitted.

Table 8. Write Package

Bit

MSB

14

13

12

11

10

9

8

7

6

5

4

3

2

1

LSB

Data <13:0>

Don’t care PAR

Bit

Description

Data

PAR

14-bit data to write to former selected address

Parity bit (EVEN)

7.2.4 Register Block

Table 9. Register Block

Register

Bit

Mode

Reset Value

Bit

Description

Power ON Reset (POR) Register - [0x3F22]

The POR cell is deactivated when the value 0x5A is written

to this register (30µA reduction of current consumption)

POR_OFF

8

R/W

0x00

<7:0>

Software Reset Register - [0x3C00]

software_reset 14

Master Reset Register - [0x33A5]

master_reset 14

Clear Error Flag Register - [0x3380]

clr_error_flag 14

No Operation Register - [0x0000]

NOP 14

Refer to SOFTWARE RESET Command on page 13

Inject a power on reset cycle

W

R

0x000

<13:0>

Refer to CLEAR ERROR FLAG Command on page 12

Refer to NOP Command on page 14

w

Automatic Gain Control (AGC) Register - [0x03FF8]

Automatic gain control:

low values = strong magnetic field

high values = weak magnetic field

AGC

6

R/W

0x20

<5:0>

Angular Data - [0x3FFF]

Measured angular value, 12-bit

Angle Value

12

1

R

0x000

0

<11:0>

<12>

Alarm bit indicating a too high magnetic field, active HIGH.

Refer to Error Monitoring on page 14

Alarm LO

Alarm HI

Alarm bit indicating a too low magnetic field, active HIGH.

Refer to Error Monitoring on page 14

1

R

0

<13>

System Configuration Register 1 - [0x3F20]

‘00’ indicates 12-bit resolution

Silicon version 001

resolution

chip ID

2

3

R

‘00’

<13:12>

<11:9>

‘001’

Error Status Register - [0x335A]

Refer to Error Status Command on page 15

error_status

14

R

0x000

<13:0>

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AS5055

Datasheet - Detailed Description

7.2.5 SPI Interface Commands

READ Command. For a single READ command two transmission sequences are necessary. The first package written to the AS5055 contains

the READ command (MSB high) and the address the chip has to access, the second package transmitted to the AS5055 device can be any

command the chip has to process next. The content of the desired register is available in the MISO register of the master device at the end of the

second transmission cycle.

Figure 5. READ Command

T _COM

MSB

LSB

MSB

LSB

MOSI

MISO

READ

Next command

Response on

READ command

Response - 1

MSB

LSB

MSB

LSB

Transmission N

Transmission N +1

WRITE Command. A single WRITE command takes two transmission cycles. The WRITE command can be verified by sending a NOP

command after the WRITE command. The Data will be send back during NOP command.

Figure 6. WRITE Command

T

COM

MSB

LSB

MSB

LSB

MSB

LSB

MOSI

MISO

WRITE

command

DATA

Next command

Old register

content

New register

content

Response-1

MSB

LSB

MSB

LSB

MSB

LSB

Transmission N

Transmission N +1

Transmission N +2

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AS5055

Datasheet - Detailed Description

CLEAR ERROR FLAG Command. The CLEAR ERROR FLAG command is implemented as READ command. This command clears the

ERROR FLAG which is contained in every READ frame. The READ data are 0x0000, which indicates a successful clear command.

Figure 7. CLEAR ERROR FLAG Command

T_COM

MSB

LSB

MSB

LSB

MOSI

MISO

CLEAR ERROR

FLAG

Next command

Response-1

0x 0000

MSB

LSB

MSB

LSB

Transmission N

Transmission N +1

The package necessary to perform a CLEAR ERROR FLAG is built up as follows.

Table 10. CLEAR ERROR FLAG Command

Bit

MSB

14

13

12

11

10

9

8

7

6

5

4

3

2

1

LSB

PAR

1

0

1

0

CLEAR ERROR FLAG command

Possible conditions which force the ERROR FLAG to be set:

Wrong parity

Wrong command

Wrong number of clocks (no full transmission cycle or too many clocks)

Note: If the error flag is set to ‘high’ because of a communication problem the flag remains set until it will be cleared by an external command.

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AS5055

Datasheet - Detailed Description

SOFTWARE RESET Command. The SOFTWARE RESET command is implemented as WRITE command. The bit ‘RES SPI’ of the DATA

package indicates if the SPI registers should be reset as well. The soft reset resets the digital part (‘RES SPI’ is set to one) as well as the OTP

memory. A new OTP memory auto-load is initiated and the reset values stored in the OTP memory are loaded into the configuration registers.

The command following the SOFTWARE RESET command can be any of the commands specified in this chapter.

After the data package is sent, the soft reset is generated. The fuses of the OTP memory are loaded into the registers and a new conversion

cycle will be started. If the device is in sleep mode the oscillator will be started first.

Figure 8. SOFTWARE RESET Command

T

COM

MSB

LSB

MSB

LSB

MSB

LSB

SOFTWARE

RESET

command

MOSI

MISO

DATA

Next command

Response-1

0x 0000

MSB

LSB

MSB

LSB

MSB

LSB

Transmission N

Transmission N +1

Transmission N +2

In order to invoke a software reset on the AS5055 the following bit pattern has to be sent.

Table 11. SOFTWARE RESET Command

Bit

MSB

14

13

12

11

10

9

8

7

6

5

4

3

2

1

LSB

PAR

0

1

0

SOFTWARE RESET command

Table 12. Data Package

Bit MSB 14

13

12

11

10

9

8

7

6

5

4

3

2

1

LSB

Don’t care

RES SPI Don’t care PAR

Bit

Description

If set to one, SPI registers are reset as well¹

Parity bit (EVEN)

RES SPI

PAR

1. After a power on reset, the OTP will be read and hence OTP related

registers are changed independent on the RES SPI flag.

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AS5055

Datasheet - Detailed Description

NOP Command. The NOP command represents a dummy write to the AS5055.

Figure 9. NOP Command

T

COM

MSB

LSB

MSB

LSB

MSB

LSB

MOSI

MISO

NOP

Next command

Response-1

0x0000

MSB

LSB

MSB

LSB

MSB

LSB

Transmission N

Transmission N +1

Transmission N +2

The NOP command frame looks like follows.

Table 13. NOP Command

Bit

MSB

14

13

12

11

10

9

8

7

6

5

4

3

2

1

LSB

0

NOP command (0x0000)

The chip’s response on this command is 0x0000 – if no error happens.

7.2.6 Error Monitoring

The correct operation and communication of the AS5055 is ensured by several particular error flags. Every read access is supported by an error

flag (EF) to indicate a transmission error. In addition a dedicated error status register is accessible. See Table 14 on page 15.

Alarm HI

Alarm LO

Mode Description

AGC level is higher than the minimum value and lower than the maximum value

AGC level is equal or even lower than the minimum level

AGC level is equal or even higher than the maximum level

0

1

0

1

0

Indicates if any error flag has occurred. For detailed information, refer to Error

Status Command on page 15.

1

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AS5055

Datasheet - Detailed Description

Error Status Command.

Table 14. Error Status Command

Description

Error Status DSP

11 10

reserved DSPAHI DSPALO RANERR DSPOV DACOV reserved MODE WOW reserved ADDMON CLKMON PARITY

Error Status System

Error Status SPI

Bit

13

12

9

8

7

6

5

4

3

2

1

0

Type

PARITY: Indicates when the transmitted parity bit does not match to calculated parity bit

CLKMON: Clock monitoring indicates when the amount of clock cycles is not correct

ADDMON: Address monitoring appears when the address does not exist

WOW: This is a handshake mechanism to check system integrity. By sending a READ ANGLE command the internal flag (WOW) is set to high.

At the end of measurement the WOW is set to low again. In failure case (internal dead lock situation) the WOW flag remains high.

MODE: During sleep mode, the flag is 0. When the IC is busy (measuring), the flag is 1.

DACOV: The DACOV bit occurs if the magnetic input field strengths is too large for at least one Hall element. This can be the case if the magnet

is displaced.

DSPOV: CORDIC overflow occurs when the input signals of CORDIC are too large

RANERR: Range error appears when the voltage drop over the internal current source decreases which is caused by increased temperature.

The accuracy is getting worse.

DSPALO: DSP Alarm LO; AGC level is equal or even lower than the minimum level.

DSPAHI: DSP Alarm HI; AGC level is equal or even higher than the maximum level.

For additional information on Error Status, please refer to the application note AN5000_Error Monitoring.

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AS5055

Datasheet - Application Information

8 Application Information

The benefits of the AS5055 device are as follows:

Complete system-on-chip

Low power consumption

Low operating voltage

Easy to use SPI interface

8.1 SPI Interface

The 16-bit SPI Interface enables read / write access to the register blocks and is compatible to a standard micro controller interface. The SPI

module is active as soon as /SS pin is pulled low. The AS5055 then reads the digital value on the MOSI (master out slave in) input with every

falling edge of SCK and writes on its MISO (master in slave out) output with the rising edge. After 16 clock cycles /SS has to be set back to a high

status in order to reset some parts of the interface core. The SPI Interface can be set in two different modes: 3-wire mode or 4-wire mode.

Notes:

1. The wire mode selection is read during the POWER-UP state and can be changed with a power on reset or a software reset command.

2. For more stability on the SPI Interface, it is very important to place filters. The filter must be placed close to the driving outputs. For

further information, please refer to the application note AN5000_SPI_Interface.

Table 15. Wire Mode Selection

Wire Mode Selection (pad 14)

wire_mode = LO

wire_mode = HI

3-wire mode

4-wire mode

8.1.1 SPI Interface Signals (4-Wire Mode, Wire_mode = 1)

The AS5055 only supports slave operation mode. Therefore SCK for the communication as well as the /SS signal has to be provided by the test

equipment. The following picture shows a basic interconnection diagram with one master and an AS5055 device and a principle schematic of the

interface core.

Figure 10. SPI Interface Connection

SCK

SPI_CLK

SS/

SPI_SS^N

MOSI

Interface Core

RXSR

RXSPI

Master Device

(Tester)

TXSPI

TXSR

MISO

AS5055

Because the interface has to decode the sent command before it can react and provide data the response of the chip to a specific command

applied at a time T can be accessed in the next transmission cycle ending at T + TCOM.

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Revision 1.16

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AS5055

Datasheet - Application Information

The data are sent and read with MSB first. Every time the chip is accessed it is sending and receiving data.

Figure 11. SPI Command / Response Data Flow

T

COM

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MOSI

MISO

Command 1

0x00

Command 2

Response 1

Command N - 1

Response 2

Command N

Response N - 1

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

Transmission 1

Transmission 2

Transmission N - 1

Transmission N

8.1.2 SPI Timing

Figure 12. SPI Timing Diagram

t _XSSH

SS/

( Input )

t_L

t_sck

t _sckL

t _sckH

t_H

SCK

( Input )

t _MISO

t_OZ

MISO

data[ 15]

data[ 14]

data[0]

( Output )

t_OZ

t _MOSI

MOSI

data[ 15]

data[ 14]

data[0]

( Input )

Table 16. SPI Timing Characteristics

Parameter

Description

Min

Max

Unit

ns

t_OZ

t_L

Time between positive edge of SS/ to output high impedance

Time between SS/ falling edge and SCK rising edge

Serial clock period

50

10

100

50

ns

t_SCK

t_SCKL

t_SCKH

t_H

ns

Low period of serial clock

ns

High period of serial clock

50

ns

t

_SCK/ 2

Time between last falling edge of SCK and rising edge of SS/

ns

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Revision 1.16

17 - 26

AS5055

Datasheet - Application Information

Table 16. SPI Timing Characteristics

Parameter

t_XSSH

Description

Min

50

Max

Unit

ns

High time of SS/ between two transmissions

Data input valid to clock edge

t_MOSI

20

ns

t_MISO

SCK edge to data output valid

20

ns

8.1.3 SPI Connection to the Host µC

Single Slave Mode.

Figure 13. Single Slave Mode

0xFFFF

Write CMD

0xFFFF

Write CMD

0xFFFF

Write CMD

0xFFFF

Write CMD

0xFFFF

Write CMD

0xFFFF

Write CMD

MOSI

MISO

SS/

...

Read angle1 Read angle2 Read angle 3 Read angle4 Read angle5 Read angle6

NOP

MOSI

MISO

SCK

SS/

MOSI

MISO

SCK

SS/

Angle1

Angle2

Angle3

Angle4

Angle5

Angle6

UC

AS5055

Wire_Mode

1

4wire mode

1

MOSI

MISO

SS/

...

Angle 1

Angle 2

Angle3

Angle4

Angle5

Angle6

Angle7

MISO

SCK

SS/

AS5055

SCK

SS/

Wire_Mode

1

3 wire mode(Read only )

0xFFFF

Write CMD

SISO

MISO

MOSI

SISO

SS/

Angle 1

Angle 2

Angle 3

Angle 4

Read angle1

Read angle2

Read angle3

Read angle4

AS5055

SCK

SS/

SCK

SS/

3wire mode(Bi- dir)

Wire_Mode

0

Note: 3 Wire Mode (read only): If the ERROR FLAG is set the device must be externally reset.

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Revision 1.16

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AS5055

Datasheet - Application Information

Multiple Slave, n+3 Wire (Separate ChipSelect).

Figure 14. Multiple Slave, n+3 Wire (Separate ChipSelect)

0xFFFF

xx

Write CMD

UC MOSI

xx

MOSI

MISO

SW reset

Read angle1

Read angle2

Read angle3

MOSI

MISO

SCK

NOP

AS5055

I

UC MISO

SS1/

...

Angle 1

Angle 2

Angle 3

SCK

SS/

UC

SS1/

SS2/

SS3/

Wire_Mode

1

SS2/

MOSI

MISO

AS5055

II

SCK

SS/

Wire_Mode

1

MOSI

MISO

AS5055

III

SCK

SS /

Wire_Mode

1

Daisy Chain, 4 Wire.

Figure 15. Daisy Chain, 4-Wire

Write CMD

UC MOSI

MOSI

SW reset

MISO

SCK

SS/

AS5055

I

...

UC MISO

SS/

SCK

SS/

UC

Wire_Mode

1

0xFFFF

Read angle3 Read angle2 Read angle1 Read angle3 Read angle2 Read angle1

...

UC MOSI

MOSI

MISO

Angle3

Angle2

Angle1

Angle3

Angle2

Angle1

UC MISO

SS/

AS5055

II

SCK

SS/

Wire_Mode

1

MOSI

MISO

AS5055

III

SCK

SS/

Wire_Mode

1

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Revision 1.16

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AS5055

Datasheet - Application Information

8.1.4 SPI Over Long Distances

Over long cable distances you will have coupling capacitance between signals. Therefore consider some aspects.

The circuitry of the connection is shown in Figure 16.

Figure 16. Circuitry of SPI Over Long Distances

SPI Interface

µC

SPI Interface

AS5055

R

MOSI

MISO

MOSI

C

R

MISO

C

VSS

SCK

VSS

SCK

R

C

SS/

C

One aspect is that between MISO and SCK must be separated with VSS. Additionally filter circuitry, reduces the disturbance to a minimum.

Resistors close to the output pins reduce communication noise and increase EMC.

Required resistors on the output pins are between 100 Ohm and 1000 Ohm. Required capacitance is 100pF.

Place the resistors and capacitors as near as possible to the pins.

For additional information on this issue, please refer to the application note AS5055_SPI_APPNote.

www.ams.com/AS5055

Revision 1.16

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AS5055

Datasheet - Application Information

8.2 Placement of the Magnet

Non-Linearity Error over Displacement.

As shown in Figure 18, the recommended horizontal position of the magnet axis is over the diagonal center of the IC.

Figure 17 shows a typical error curve at a vertical magnet distance of 1.0mm, measured with a NdFeB N35H magnet with 6mm diameter and

2.5mm height.

The X- and Y- axis of the graph indicate the lateral displacement of the magnet center with respect to the IC center.

At X = Y = 0, the magnet is perfectly centered over the IC. The total displacement plotted on the graph is for ±1mm in both directions.

The Z-axis displays the worst case INL error over a full turn at each given X-and Y- displacement. The error includes the quantization error of ±½

LSB. At the sample shown in Figure 17, the accuracy for a centered magnet is better than 0.5°. Within a radius of 0.5mm, the accuracy is about

1.0° (spec = 1.41° over temperature).

Figure 17. Integral Non-linearity Over Displacement of the Magnet

Non-Linearity @ z=1mm

4

3,5

3

2,5

3,5-4

2

3-3,5

2,5-3

2-2,5

1,5-2

1-1,5

0,5-1

0-0,5

0,8

0,5

0,2

-0,1

-0,4

-0,7

-1,0

INL [°] 1,5

1

0,5

0

Y-displacement [mm]

X-displacement [mm]

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Revision 1.16

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AS5055

Datasheet - Package Drawings and Markings

9 Package Drawings and Markings

The device is available in a 16-pin QFN (4x4x0.85 mm) package.

Figure 18. Drawings and Dimensions

YYWWXZZ

AS5055 @

Symbol

A

Min

0.80

0

Nom

0.90

Max

1.00

0.05

A1

A3

L

0.02

0.20 REF

0.50

0.45

0

0.55

0.15

0.35

L1

b

-

0.25

0.30

D

4.00 BSC

0.65 BSC

2.40

E

e

D2

E2

aaa

bbb

ccc

ddd

eee

fff

2.30

2.50

Notes:

2.30

2.40

2.50

1. Dimensions and tolerancing conform to ASME Y14.5M-1994.

-

0.15

-

2. All dimensions are in millimeters. Angles are in degrees.

0.10

3. Dimension b applies to metallized terminal and is measured between 0.25mm

and 0.30mm from terminal tip. Dimension L1 represents terminal full back from

package edge up to 0.15mm is acceptable.

0.10

0.05

0.08

4. Coplanarity applies to the exposed heat slug as well as the terminal.

5. Radius on terminal is optional.

0.10

N

16

6. N is the total number of terminals.

Marking: YYWWXZZ.

YY

WW

X

ZZ

Assembly traceability code

@

Year (i.e. 04 for 2004)

www.ams.com/AS5055

Week

Assembly plant identifier

Revision 1.16

Sublot identifier

22 - 26

AS5055

Datasheet - Package Drawings and Markings

Figure 19. Vertical Cross Section of 16-pin QFN (4x4x0.85 mm)

Notes:

1. All dimensions in mm.

2. Die thickness 0.254 ± 0.013

3. Adhesive thickness 0.010 ± 10, +0.01, -0.0025

4. Lead frame thickness 0.203 typ.

www.ams.com/AS5055

Revision 1.16

23 - 26

AS5055

Datasheet - Revision History

Revision History

Revision

Date

Owner

Description

Initial revision of public release version

1.0

1.1

23 Mar, 2010

8 Jun, 2010

jja

Updated Pin Descriptions (pin 16), Typical Application, SPI Connection to the

Host µC, Figure 3, Figure 13, Figure 14, Figure 15.

jlu

Updated Absolute Maximum Ratings, System Parameters, Pin Descriptions,

Power Supply Filter, Table 9, SPI Connection to the Host µC, Package

Drawings and Markings.

1.11

3 Nov, 2010

agt

Updated operating temperature range.

Updated Figure 3, Table 9 and package drawings.

Updated Alarm LO / HI info in Table 9.

1.12

1.13

1.14

3 Nov, 2011

28 Dec, 2011

11 Jul, 2012

mub

rei

Updated Figure 1, Section 4, Section 7.2.4, Table 16; Added Error Status

Command, Figure 19, Section 8.1.4

1.15

1.16

16 Oct, 2012

ekno

Correction of error status register and alarm bits, updated marking.

Updated Table 4, Table 14, Table 16

05 Feb, 2013

21 Feb, 2013

Note: Typos may not be explicitly mentioned under revision history.

www.ams.com/AS5055

Revision 1.16

24 - 26

AS5055

Datasheet - Ordering Information

10 Ordering Information

The devices are available as the standard products shown in Table 17.

Table 17. Ordering Information

Ordering Code

Description

Delivery Form

Package

AS5055 EQFT

12-bit low power magnetic rotary encoder

Tape & Reel

16-pin QFN (4x4x0.85 mm)

Note: All products are RoHS compliant and ams green.

Buy our products or get free samples online at www.ams.com/ICdirect

Technical Support is available at www.ams.com/Technical-Support

For further information and requests, email us at sales@ams.com

(or) find your local distributor at www.ams.com/distributor

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Revision 1.16

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AS5055

Datasheet - Copyrights

Copyrights

reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the

copyright owner.

All products and companies mentioned are trademarks or registered trademarks of their respective companies.

Disclaimer

Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. ams AG makes no

warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described

devices from patent infringement. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior

to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in normal

commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability

applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing

by ams AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard

production flow, such as test flow or test location.

The information furnished here by ams AG is believed to be correct and accurate. However, ams AG shall not be liable to recipient or any third

party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or

indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the

technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other

services.

Contact Information

Headquarters

ams AG

Tobelbaderstrasse 30

A-8141 Unterpremstaetten, Austria

Tel : +43 (0) 3136 500 0

Fax : +43 (0) 3136 525 01

For Sales Offices, Distributors and Representatives, please visit:

http://www.ams.com/contact

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Revision 1.16

26 - 26


型号：	AS5055
厂家：	AMS(艾迈斯)
描述：	Low Power 12-Bit Magnetic Rotary Encoder 低功耗的12位磁旋转编码器编码器
文件：	总26页 (文件大小：1023K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AS5055 [AMSCO]

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