AS5115A-HSSP [AMSCO]
Programmable 360 Magnetic Angle Encoder with Buffered SINE COSINE Output Signals; 可编程360磁性角度编码器与缓冲正余弦输出信号
| 型号： | AS5115A-HSSP |
| 厂家： | 
AMS(艾迈斯) |
| 描述： | Programmable 360 Magnetic Angle Encoder with Buffered SINE COSINE Output Signals |
| 文件： | 总21页 (文件大小：1197K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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is now
ams AG
The technical content of this austriamicrosystems datasheet is still valid.
Contact information:
Headquarters:
ams AG
Tobelbaderstrasse 30
8141 Unterpremstaetten, Austria
Tel: +43 (0) 3136 500 0
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Please visit our website at www.ams.com
Datasheet
AS5115
Programmable 360º Magnetic Angle Encoder with Buffered SINE &
COSINE Output Signals
1 General Description
The AS5115 is a contactless rotary encoder sensor for accurate
angular measurement over a full turn of 360º and over an extended
ambient temperature range of -40ºC to +150ºC.
2 Key Features
Contactless angular position encoding
High precision analog output
Buffered Sine and Cosine signals
SSI Interface
Based on an integrated Hall element array, the angular position of a
simple two-pole magnet is translated into analog output voltages.
The angle information is provided by means of buffered sine and
cosine voltages. This approach gives maximum flexibility in system
design, as it can be directly integrated into existing architectures and
optimized for various applications in terms of speed and accuracy.
Low power mode
Two programmable output modes: Differential or Single nded
Wide magnetic field input range: 20 – 0 mT
Wide temperature range: -40ºC to +150ºC
Fully automotive qualified to AE100, rade 0
SSOP-1package
An SSI Interface is implemented for signal path configuration as well
as a one time programmable register block (OTP), which allows the
customer to adjust the signal path gain to adjust for different
mechanical constraints and magnetic field.
3 Applications
The AS5115 is ideal fseveral automotive and industrial
applications.
Figure 1. AS5115 Block Diagram
OTP Register
Digital Part
PROG
AS5115
CS
DCLK
DIO
VDD
VSS
Power
Management
SSI Interfce
Buffer Stage
Buffer Stage
SINP/SINN
SINN/SINP/CM_SIN
COSP/COSN
Hall Array
&
Frontend
Amplifier
COSN/COSP/CM_COS
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AS5115
Datasheet - Contents
Contents
1 General Description ..................................................................................................................................................................
2 Key Features.............................................................................................................................................................................
3 Applications...............................................................................................................................................................................
4 Pin Assignments .......................................................................................................................................................................
4.1 Pin Descriptions....................................................................................................................................................................................
5 Absolute Maximum Ratings ......................................................................................................................................................
6 Electrical Characteristics...........................................................................................................................................................
6.1 Timing Characteristics.........................................................................................................................................................................
7 Detailed Description................................................................................................................................................................
1
1
1
3
3
4
5
7.1 Sleep Mode .......................................................................................................................................................................................
7.2 SSI Interface.......................................................................................................................................................................................
7.3 Device Communication / Programming............................................................................................................................................
7
7
8
7.4 Waveform – Digital Interface at Normal Operation Mode............................................................................................................... 10
7.5 Waveform – Digital Interface at Extended Mode ......................................................................................................................... 10
7.6 Waveform – Digital Interface at Analog Readback of the Zener Diod........................................................................................ 11
7.7 EasyZapp OTP Content ................................................................................................................................................................ 11
7.8 Analog Sin/Cos Outputs with External Interpolator .............................................................................................................. 12
7.9 OTP Programming and Verification............................................................................................................................................. 13
7.10 Pre-programmed Version .............................................................................................................................................................. 15
8 Application Information .................................................................................................................................................. 16
9 Package Drawings and Markings ................................................................................................................................. 17
10 Ordering Information........................................................................................................................................................ 19
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AS5115
Datasheet - Pin Assignments
4 Pin Assignments
Figure 2. Pin Assignments (Top View)
16
1
2
3
4
5
6
7
8
VDD
DCLK
TB0
CS
15
14
13
DIO
TB1
TC
TB2
AS5115
A_TST
TB3
12
11
10
PROG
VSS
COSN/COSP/CM_COS
COSP/COSN
INN/SINP/CM_SIN
SINP/SINN
4.1 Pin Descriptions
Table 1. Pin Descriptions
Pin Name
DCLK
CS
Pin Number
Pin Type
Description
Clock input for digital interface
Clock input for digital interface, Scan enable
Data I/O for digital interface, Scan input
Test coil
1
2
3
4
Digital input with Sc
triger
DIO
igital input/output
Analoinput/output
TC
log output/Digital
output
Analog test pin, Scan output
A_TST
5
OTP Programming Pad
PROG
6
7
Supply pad
Also used as VSS of test coil + EasyZapp (double bond)
VSS
SINP/SINN
8
SINN/SINP/CM_S
9
Buffered analog output
Analog output
COSP/COSN
10
11
12
13
14
15
16
COSN/COSP/CM_COS
B3
TB2
TB1
TB0
VDD
Test bus, analog output
Analog output/Digital
input
Test bus, analog output; external clock sync. prod. test
Test bus, analog output
Analog output
Supply pad
Digital + analog supply
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AS5115
Datasheet - Absolute Maximum Ratings
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of
the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 5 is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Table 2. Absolute Maximum Ratings
Parameter
Electrical Parameters
Min
Max
Units
Comments
Supply voltage (VDD)
Input pin voltage (V_in)
-0.3
-0.3
-100
7
V
V
VDD+0.3
100
Input current (latchup immunity), I_scr
Electrostatic Discharge
mA
Norm: EIA/JESD78 Class II Level A
Norm: JESD22-A114E
Electrostatic discharge (ESD)
Continuous Power Dissipation
±2
kV
Total power dissipation (Ptot
)
275
27
mW
Package thermal resistance (_JA)
Temperature Ranges and Storage Conditions
Storage temperature (T_strg)
ºC/W
Velocity =0; Multi Layer PCJedec Standard Testboard
-65
150
260
85
ºC
ºC
%
rm: IPC/JEDEC J-STD-020.
The reflow peak sldering temperature (body temperature)
specified is n accordance with IPC/JEDEC J-STD-020
“Moure/Reflow Sensitivity Classification for Non-
Heretic Solid State Surface Mount Devices”.
lead finish for Pb-free leaded packages is matte tin
(100% Sn).
Package body temperature (T_body)
Humidity non-condensing
5
Moisture Sensitive Level (MSL)
3
Represents a maximum floor time of 168h
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AS5115
Datasheet - Electrical Characteristics
6 Electrical Characteristics
Unless otherwise noted in this specification, all defined tolerances of parameters are assured over the whole operation conditions range and also
over lifetime.
Table 3. Operating Conditions
Symbol
VDD
Parameter
Condition
Min
4.5
0.0
-40
Typ
Max
5.5
Unit
V
Positive Supply Voltage
Negative Supply Voltage
Ambient temperature
VSS
0.0
V
T_amb
150
ºC
Table 4. DC/AC Characteristics for Digital Inputs and Outputs
Symbol
CMOS Input
V_IH
Parameter
Condition
Min
Typ
Max
Unit
High level input voltage
Low level input voltage
Input Leakage Current
0.7 * VDD
VDD
.3 * VDD
1
V
V
V_IL
0
I_LEAK
CMOS Output
V_OH
µA
High level output voltage
Low level output voltage
Capacitive Load
4mA
A
VDD - 0.5
VDD
VSS + 0.4
35
V
V
V_OL
0
C_L
pF
CMOS Output Tristate
I_OZ
Tristate Leakage Current
1
µA
Table 5. Magnetic Input Specification
Symbol
Parameter
Conition
Min
Typ
Max
Unit
Peak at the radius
(=1the hall array
BZpp
Magnetic input field amplitude
32
160
mT
B_offset
frot
Magnetic field offset
Rotational speed
Wiin the linear range of the magnet
Maximum 30,000 RPM
-10
0
+10
500
mT
Hz
Table 6. Electrical System Specifications
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Maximum value derived at maximum I_H
(Hall Bias Current)
IDD
Current Consumptio
28
mA
tpower_on
tprop
Poweup tme
1.275
30
ms
µs
Proagatin delay
-40ºC to 150ºC
Version: AS5115
Version: AS5115A
18
10
22
60
M
Manetic Sensitivity
mV / mT
V
20.72
28
35.28
Analog output voltage amplitude
(peak to peak)
VPP
1.38
1.94
2.5
Aemp
AM
AM tracking accuracy over temperature
Sin / Cos Amplitude mismatch
-40ºC to 150ºC
25ºC
-1
-2
+1
+2
%
%
Voffset1
Voffset2
DCoffdrift
1.47
2.45
-50
1.5
2.5
1.53
2.55
+50
At no input signal; programmable OTP
setting (see page 8)
Output DC offset voltage
DC Offset Drift
V
-40ºC to 150ºC
µV/ºC
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AS5115
Datasheet - Electrical Characteristics
Table 6. Electrical System Specifications
Symbol
VOUT
Parameter
Analog output range
Output Current
Condition
Min
VSS + 0.25
-1
Typ
Max
VDD - 0.5
1
Unit
V
IOUT
mA
pF
CLOAD
Capacitive Load
1000
6.1 Timing Characteristics
Table 7. Timing Characteristics
Symbol
t1_3
Parameter
Condition
Min
30
0
Typ
Max
Unit
ns
Chip select to positive edge of DCLK
Chip select to drive bus externally
-
-
t2_3
ns
Setup time command bit
Data valid to positive edge of DCLK
t3
t4
30
15
-
ns
ns
Hold time command bit
Data valid after positive edge of DCLK
Float time
t5
t6
Positive edge of DCLK for last
command bit to bus float
ns
ns
Bus driving time
Positive edge of DCLK for last
command bit to bus drive
-
Data valid time
Positive edge of DCLK to bus valid
t7
t8
ns
ns
see Fgure 5 and
Figure 6
Hold time data bit
Data valid after positive edge of DLK
-
-
Hold time chip select
Positive edge DCLK to negative edge
of chip select
t9_3
ns
ns
Bus floating time
t10_3 Negative edge of chip select to float
bus
-
30
Setup time data bit at write access
t11
30
15
-
-
ns
ns
Data valid to positive edge oDCLK
Hold time data bit at writaccss
t12
Data valid after positve edgof DCLK
Bus floating time
t13_3 Negative edge of chiselect to float
bus
-
30
ns
Remark: The dial inrface will be reset during the low phase of the CS signal.
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AS5115
Datasheet - Detailed Description
7 Detailed Description
The benefits of AS5115 are as follows:
Complete system-on-chip, no angle calibration required
Ideal for applications in harsh environments due to magnetic sensing principle
High reliability due to non-contact sensing
Robust system, tolerant to horizontal misalignment, temperature variations and external magnetic fields
7.1 Sleep Mode
The target is to provide the possibility to reduce the total current consumption. No output signal will be provided when the IC is in sleep mode
Enabling or disabling sleep mode is done by sending the SLEEP or WAKEUP commands via. the SSI interface. Analog blocks are powered
down with respect to fast wake up time.
7.2 SSI Interface
The setup for the device is handled by the digital interface. Each communication starts with the rising edge of the chip sect sinal. The
synchronization between the internal free running analog clock oscillator and the external used digital clock source for the dital interface is
done in a way that the digital clock frequency can vary in a wide range.
Table 8. SSI Interface Pin Description
Port
Chip select
Symbol
CS
Function
Indicates the f a new access cycle the device
CS = LO ret of the digital interface
Clock source for the communicatioover the digital interface
DCLK
DCLK
DIO
Commanand data informaver one single line
Te first bit of the comnd fines a read or write access
Bidirectional data input output
Table 9. SSI Interface Parameter Description
Symbol
Parameter
Noes
Min
Typ
Max
Unit
f_DCLK
Clock frequency at normal operation
no limit
5
6
MHz
The nominal vafor the clock frequency can
be drived from a 10MHz oscillator source.
Clock frequency at easy zap read
write access
f_EZ_RW
no limit
200
5
-
6
kHz
kHz
Correct access to the programmable zener
iode block needs a strict timing – the zap
pulse is exact one period.
Clock frequency at easy zap aces
program OTP
f_EZ_PROG
650
The nominal value for the clock frequency can
be derived from a 10MHz oscillator source.
20pF external load allowed.
Clock frequency at asy zap analog
radback
f_EZ_ARB
no limit
156.3
162.5
kHz
The nominal value for the clock frequency can
be derived from a 10MHz oscillator source.
Parameter
Notes
Interface Generaat normal mode
Protocol: ommand bit + 16 data input output
Comand
5-bit command: cmd<4:0> bit<21:16>
16-bit data: data<15:0> bit<15:0>
Data
Interface General at extended mode
Protocol: 5 command bit + 46 data input output
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AS5115
Datasheet - Detailed Description
Parameter
Command
Notes
5-bit command: cmd<4:0> bit<50:46>
Data
34-bit data: data<45:0> bit<45:0>
Interface Modes
Normal read operation mode
Extended read operation mode
Normal write operation mode
Extended write operation mode
cmd<4:0> = <00xxx> 1 DCLK per data bit
cmd<4:0> = <01xxx> 4 DCLK per data bit
cmd<4:0> = <10xxx> 1 DCLK per data bit
cmd<4:0> = <11xxx> 4 DCLK per data bit
7.3 Device Communication / Programming
Table 10. Digital Interface at Normal Mode
#
command
WRITE_CONFIG
EN_PROG
bin
mode
write
write
15
go2sleep
1
14
gen_rst
0
13 12 11 10
9
analog_sig
0
8
7
6
5
4
3
2
0
23
16
10111
10000
OB_bypassed
0
0
0
1
1
1
0
1
1
1
1
0
Name
Fnctionality
Enter/leave low power mode (no outpsignls)
Generates global reset
go2sleep
gen_rst
Switches the channels to the tbus after the PGA
Disable and bypass output buffer for testing purpo
analog_sig
OB_bypassed
Table 11. Digital Interface at Extended Mode
Factory Settings
User Settings
#
command
bin
mode
<
26
<45:44>
<25:3> <22:20> <19:18> 17:14> <13> <12>
<11>
<10>
<9>
<8:7>
<6>
<5:0>
invert_
dc_
hall_
bias
31
25
WRITE_OTP
PROG_OTP
11111 xt write
11001 xt write
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
cm_sin
cm_sin
cm_sin
cm_cos
cm_cos
cm_cos
gain
gain
gain
channel
offset
invert_
channel
dc_
offset
hall_
bias
invert_
channel
dc_
offset
hall_
bias
15
9
RD_OTP
01111 xt read
01001 xt read
RD_OTP_ANA
Note: “r” stands for reserved bits. Themust not be modified, unless otherwise noted.
Remark:
1. Send EN PROG (comman16) in normal mode before accessing the OTP in extended mode.
2. OTP assignment will bdefined/updated.
Name
invert_hannInverts
cm_sin
Functionality
SIN and COS channel before the PGA for inverted output function (0 SIN/COS, 1 SINN/COSN)
Common mode voltage output enabled at SINN / CM pin (0 differential, 1 common)
Common mode voltage output enabled at COSN / CM pin (0 differential, 1 common)
PGA gain setting (influences overall magnetic sensitivity), 2-bit
cm_cos
gain
Output DC bias offset (0 Voffset1=1.5V, 1 Voffset2=2.5V)
dc_offset
Hall bias setting (influences overall magnetic sensitivity), 6-bit
Hall_b
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AS5115
Datasheet - Detailed Description
Figure 3. Sensitivity Gain Settings - Relative Sensitivity in %
Magnetic Sensitivity vs. OTP Hall Current & PGA Gain Setting
600
550
500
450
400
350
300
250
200
150
100
M_PGA_00
M_PGA_01
M_PGA_1
M_PGA_11
0
10
20
30
40
50
60
Hall Current OTP s(6 bits)
The amplitude of the output signal is programmable via sensitivity (6bit) and/or gain (2bit) setngs (se Figure 3).
Figure 4. Sensitivity Gain Settings - Sensitivity [mV/mT]
Magnetic Snsitity vs. OTP Hall Current PGA Gain Setting
70
60
50
40
30
20
0
M_PGA_00
M_PGA_01
M_PGA_10
M_PGA_11
0
10
20
30
40
50
60
Hall Current OTP setting (6 bits)
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AS5115
Datasheet - Detailed Description
7.4 Waveform – Digital Interface at Normal Operation Mode
Figure 5. Digital Interface at Normal Operation Mode
CMD_PHASE
DATA_PHASE
DCLK
CS
t9_3
t1_3
t5
t6
t2_3
DIO
DIO
CD
CMD4
t3
CMD3
CMD2
CMD1
CMD0
t7
t10_3
D0
t8
D14
t4
READ
D15
D13
t11
t13_3
t12
D14
DIO
WRITE
D15
D13
7.5 Waveform – Digital Interface at Extended Mode
In the extended mode, the digital interface needs four clocks for one data bit due to thrnal structure. During this time, the device is able to
handle internal signals for special access (e.g. the easzap nterface).
Figure 6. Digital Interface at Extended Mode
CMD_PHASE
DATA_PHASE
DCLK
t1_3
t9_3
CS
t7
t5
t2_3
DIO
CMD4
CMD0
CMD3
CMD2
CMD
CMD
t10_3
t13_3
t8
t3
t6
t4
DIO
DIO
READ
D45
D44
D0
t11
t12
WRITE
D45
D44
D0
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AS5115
Datasheet - Detailed Description
7.6 Waveform – Digital Interface at Analog Readback of the Zener Diodes
To be sure that all Zener-Diodes are correctly burned, an analog readback mechanism is defined. Perform the ‘READ OTP ANA’ sequence
according to the command table and measure the value of the diode at the end of each phase.
Figure 7. Digital Interface at Analog Readback of Zener Diodes
CMD_PHASE
DATA_PHASE_EXTENDED
EXT D1
EXT D0
EXT D44
EXT D45
DCLK
CS
DIO
CMD4 CMD3 CMD2 CMD1 CMD0
OTP D45
OTD43
OTP D0
OTP D44
PROG
perform analog mements at PROG
Table 12. Serial Bit Sequence (16-bit read / write)
Write Command
Rad / Write Data
C4 C3 C2 C1 C0 D15 D14 13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
7.7 One Time Programming Content
The AS5115 die has an integrated 46-bit OTP ROM (Easyzap) for imming and configuration purposes. The PROM can be programmed via.
the serial interface. For irreversible programming, an external programming voltage at PROG pin is needed. For security reasons, the factory
trim bits can be locked by a lock bit.
As shown in the table below, the OTP holds 46 itsnumber 44 and 45 are used for OTP testing purposes and ESD protection of the
remaining cells.
Name
Hall_b
dc_offset
gain
Bit Count OTP tart OTP End
Access
Comments
Sets overall sensitivity
6
1
2
1
0
6
5
6
user
user
Output DC offset setting
Output Buffer Gain setting
Set in production test
7
8
user
Lock
13
13
austriamicrosystems
Inverts SIN and COS channel before the PGA for
inverted output function
invert_nel
cm_sin
1
1
1
11
10
9
11
10
9
user
user
user
Common mode voltage output enabled at SINN /
CM pin
Common mode voltage output enabled at COSN /
CM pin
cm_cos
Remark: OTP assignment will be defined/updated.
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AS5115
Datasheet - Detailed Description
7.8 Analog Sin/Cos Outputs with External Interpolator
Figure 8. Sine and Cosine Outputs for External Angle Calculation
+5V
VDD
100k
VDD PROG
SINN/SINP/CM_SIN
SINP/SINN
VDD
D
D
A
A
Micro
AS5115
Controller
10n
COSOSP/CM_COS
OSCOSN
VSS
VSS
VSS
Notes:
1. We recommend to use a 100k pull-up resistance.
2. Default conditions for unused pins are: DCLK, S, D, TC, A_TST, TBO, TB1, TB2, TB3 connect to VSS
The AS5115 provides analog Sine and osine outputs (SINP, COSP) of the Hall array front-end for test purposes. These outputs allow the user
to perform the angle calculation by aexternal ADC + µC, e.g. to compute the angle with a high resolution. The signal lines must be kept as
short as possible. In the case oonger lines, they must be shielded in order to achieve best noise performance.
Through the programig of ne bit, you have the possibility to choose between the analog Sine and Cosine outputs (SINP, COSP) and their
inverted signals (SINN, COSN). Furthermore, by programming the bits <9:10> you can enable the common mode output signals of SIN and
COS.
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AS5115
Datasheet - Detailed Description
7.9 OTP Programming and Verification
Figure 9. OTP Programming Connection
+5V
VDD
VDD
VDD
Output
CS
Output
DCLK
100n
I/O
DIO
Micro
Controller
8.0 - 8.5V
+
PROG
10µF 100n
VSS
VSS
VSS
Special Ca
Standard Case
maximum
parasitic cable
inductance
SUPPLY
VSUPPLY
L<50nH
L<50nH
VDD
VDD
Vzapp
Vprog
Vprog
PROG
GND
PROG
GND
C2
10µF
C1
100nF
C2
10µF
C1
PROM Cell
PROM Cell
100nF
Remove for normal operation
Note: The maximum capcitive load at PROG in normal operation should be less than 20pF. However, during programming the capacitors
C1+C2 are neded to buffer the programming voltage during current spikes, but they must be removed for normal operation. To
overcome this cotradiction, the recommendation is to add a diode (4148 or similar) between PROG and VDD as shown in Figure 9
(speciacase etup), if the capacitors can not be removed at final assembly.
to D1, the capacitors C1+C2 are loaded with VDD - 0.7V at startup, hence not influencing the readout of the internal OTP registers.
Duing programming the OTP, the diode ensures that no current is flowing from PROG (8V - 8.5V) to VDD (5V).
In the standard case (see Figure 9), the verification of a correct OTP readout can be done by analog readback of the OTP register.
As long as the PROG pin is accessible it is recommended to use standard setup. In case the PROG pin is not accessible at final
assembly, the special setup is recommended.
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AS5115
Datasheet - Detailed Description
For programming of the OTP, an additional voltage has to be applied to the pin PROG. It has to be buffered by a fast 100nF capacitor (ceramic)
and a 10µF capacitor. The information to be programmed is set by command 25. The OTP bits 16 until 45 are used for AMS factory trimming and
cannot be overwritten.
Symbol
VDD
Parameter
Supply Voltage
Ground level
Min
5
Max
5.5
0
Unit
V
Note
GND
0
V
V_zapp
T_zapp
f_clk
Programming Voltage
Temperature
8
8.5
85
V
At pin PROG
At pin DCLK
0
ºC
kHz
CLK Frequency
100
After programming, the programmed OTP bits can be verified in two ways:
By Digital Verification: This is simply done by sending a READ OTP command (#15). The structure of this register is the same as for tOTP
PROG or OTP WRITE commands.
By Analog Verification: By switching into Extended Mode and sending an ANALOG OTP READ command (#9), pin PRG beomes an output,
sending an analog voltage with each clock representing a sequence of the bits in the OTP register (starting with D45). A voage of <500mV
indicates a correctly programmed bit (“1”) while a voltage level between 2V and 3.5V indicates a correctly unprorammebit (“0”). Any voltage
level in between indicates incorrect programming.
Figure 10. Analog OTP Verification
+5V
VDD
VDD
VDD
Output
Output
I/
CS
DCLK
DIO
100n
Micro
Controller
PROG
VSS
VSS
V
VS
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Revision 1.11
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AS5115
Datasheet - Detailed Description
7.10 Pre-programmed Version
Table 13. Pre-programmed Version
Output DC
Offset
Version
Marking
Sensitivity
Output
PGA Gain Setting Hall Bias Current
AS5115
YYWWMZZ
AS5115
Not programmed
1.5V
0
1
Not programmed
Untrimmed
12.15µA
AS5115A
YYWWMZZ
AS5115A
28 mV/mT
2.5V
00
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Revision 1.11
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AS5115
Datasheet - Application Information
8 Application Information
Figure 11. Vertical Cross Section of SSOP-16
Notes:
1. All dimensions in mm.
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Revision 1.11
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AS5115
Datasheet - Package Drawings and Markings
9 Package Drawings and Markings
The devices are available in a 16-Lead Shrink Small Outline package.
Figure 12. Package Drawings and Dimensions
Symbol
Min
1.73
0.05
1.68
0.22
0.09
5.90
7.40
5.00
-
Nom
1.86
Max
1.99
0.21
1.78
0.38
0.25
6.50
8.20
5.60
-
A
A1
A2
b
0.13
1.73
0.30
c
0.17
D
6.20
E
7.80
E1
e
5.30
0.65 BSC
0.75
L
0.55
-
0.95
-
L1
L2
R
1.25 REF
0.25 BSC
-
-
-
0.09
0º
-
N
4º
8º
16
Noes:
1. Dimensions and tolerancing conform to ASME Y14.5M-1994.
2All dimensions are in millimeters. Angles are in degrees.
Marking: YYWWMZZ.
YY
WW
M
ZZ
Last two digits of the manufacturing year
Manufacturing week
Plant identifier
Assembly traceability code
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Revision 1.11
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AS5115
Datasheet - Revision History
Revision History
Revision
1.0
Date
Owner
Description
Initial revision
Jul 03, 2008
Jul 15, 2008
Jul 14, 2009
Key Features and pin description updated.
Updated min, typ, max values for ‘Power up time’ parameter in Table 6.
1.1
1.2
Deleted ‘Displacement’ parameter from Table 5.
Updated the following parameters in Table 6:
- Values and conditions updated for
1. Propagation delay
2. Amplitude ratio tracking accuracy over temperature
3. DC Offset Drift
1.3
Nov 30, 2009
- Deleted the ‘Output Offset’ parameter from te table.
Updated following bits related information on pae 8 - vert_channel,
cm_sin, cm_cos, gain, dc_offset, Hall_b
apg
Inserted Figure 3 and Figure 4
UpdateKey Fatures (page 1), Table 11, ad Figure 8
Hall Ary Radiuvalue updated from 1.1mm to 1mm
dated values for ‘Magnetic Sensitivity’ parameter in Table 6.
1.4
1.5
Dec 11, 2009
Mar 02, 2010
Uted ‘Interface General aextended mode’ (see Table 9)
Upated values for ‘Poweup time’ parameter in Table 6.
Added pin type in Tab1, updated reserved bits information in Table 11.
Added ‘Current sumption’ parameter in Table 6.
Updated le 5 and Table 6.
Mar 19, 2010
Nov 10, 2010
sti
Added Fure 11. Updated Package Drawings and Markings (page 17),
Tab2 and Table 5. Removed magnet related detailed info.
1.6
1.7
Feb 07, 2011
mub
ated Table 5.
Feb 16, 2011
Mar 22, 2011
Apr 07, 2011
sti
dated Package Drawings and Markings (page 17).
Deleted Tubes variant in Ordering Information (page 19).
mub
apg
1.8
Updated Key Features, OTP Programming and Verification, Table 4,
Table 6.
May 26, 2011
mub
Updated Absolute Maximum Ratings (page 4).
Updated Ordering Information (page 19).
Added subversion AS5115A info in the datasheet.
Updated Figure 9 added Note on page13.
Updated Table 6 and Figure 9
Jun 10, 2011
Sep 19, 201
Dec 14, 211
Feb 102012
Mar 6, 2012
1.9
1.10
1.11
ekno
Note: Typos may not bexplicitly mentioned under revision history.
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Revision 1.11
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AS5115
Datasheet - Ordering Information
10 Ordering Information
The devices are available as the standard products shown in Table 14.
Table 14. Ordering Information
Ordering Code
AS5115-HSSP
AS5115A-HSSP
Description
Delivery Form
Tape & Reel
Tape & Reel
Package
16-pin SSOP
16-pin SSOP
Buffered Sine and Cosine output signals
Note: All products are RoHS compliant and austriamicrosystems green.
Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect
Technical Support is available at http://www.austriamicrosystems.com/Technical-Support
For further information and requests, please contact us mailto: sales@austriamicrosystems.com
or find your local distributor at http://www.austriamicrosystems.com/distributor
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Revision 1.11
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AS5115
Datasheet - Copyrights
Copyrights
Copyright © 1997-2012, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®.
All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of
the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale.
austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding
the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and pries
any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG fo
current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature rae,
unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment ar
specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100
parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location.
The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamirosysms AG shall not
be liable to recipient or any third party for any damages, including but not limited to personal injury, property dam, loss of profits, loss of use,
interruption of business or indirect, special, incidental or consequential damags, of any ind, in connection with or arig out of the furnishing,
performance or use of the technical data herein. No obligation or liability to recient or ny third party shall risoflow out of
austriamicrosystems AG rendering of technical or other services.
Contact Information
Headquarters
austriamicrosystems AG
Tobelbaderstrasse 30
A-8141 Unterpremstaetten, Austria
Tel: +43 (0) 3136 500 0
Fax: +43 (0) 3136 525 01
For Sales Offices, Distriutors and Representatives, please visit:
http://www.austrmicroystems.com/contact
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