AS8510-ASSP [AMSCO]
Data Acquisition Device for Battery Sensors; 数据采集设备的电池传感器
| 型号： | AS8510-ASSP |
| 厂家： | 
AMS(艾迈斯) |
| 描述： | Data Acquisition Device for Battery Sensors |
| 文件： | 总47页 (文件大小：482K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Datasheet: AS8510 Data Acquisition Device for Battery Sensors
Please be patient while we update our brand image as
austriamicrosystems and TAOS are now ams.
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AS8510
Data Acquisition Device for Battery Sensors
Option for multiplexing either one differential
1 General Description
input, or two single ended inputs or the internal temperature
sensor on one channel
The AS8510 is a virtually offset free, low noise, two channel
measurement device. It is tailored to accurately measure battery
current from mA range up to kA range in conjunction with a 100 µΩ
shunt resistor in series with the battery rail. Through the second
measurement channel it enables capture of, either battery voltage
synchronous with the current measurement, or, measure the analog
output of an internal or external temperature sensor. Both channels
are matched and can either measure small signals up to ±160 mV
versus ground, through programmable gain amplifier or larger
signals in the 0 to 1V range without the amplifier.
Programmable current source for external temperature sensor
connectable to any of the inputs
High precision and high stability 1.2V reference voltage source
Digital signal processing with filter options for both channels
Four operating modes providing
- Continuous data acquisition (or)
- Periodic single-shot acquisition, (or)
- Continuous acquisition on threshold crossing of programmed
current levels (or)
After analog to digital conversion and digital filtering, the resulting
16-bit digital words are accessible through 4-wire standard serial
interface.The device includes a number of additional features
explained in the next section.
- A combination of the above
On chip high-precision 4MHz RC oscillator or option for external
clock
-40ºC to +125ºC ambient operation
AEC - Q100 automotive qualified
Internal chip ID for full traceability
SSOP-20 pin package
2 Key Features
3.3V supply voltage
Two High resolution 16 bit Σ−Δ A/D converters
Programmable sampling to enable data throughputs from less
than 1Hz to 8kHz
3 Applications
Zero Offset for both channels
Independent control of data rate on both channels
The AS8510 is ideal for shunt based batteries sensor. For high-side
current sensing, the input signal may be conditioned using ams
device AS8525 before applying to this device.
Precision, low noise, programmable gain amplifiers for both
channels with gains 5, 25, 40, 100 to support wide dynamic
ranges.
Figure 1. AS8510 Block Diagram
REF
DVDD
AVDD
Internal Temperature Sensor
Prog-Cur
Bandgap Reference
Oscillators
ETR
ETS
Source
MUX and
Chopper
16-bit Sigma-Delta ADC
PGA
VBAT_IN
VBAT_GND
MEN
CHOP_CLK
FIR / MA
AS8510
INT
CLK
RSHH
RSHL
Chopper
PGA
16-bit Sigma-Delta ADC
Analog Common Mode
Serial Interface
AVSS
VCM
SCLK CS SDI
SDO DVSS
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AS8510
Datasheet - Contents
Contents
1 General Description ..................................................................................................................................................................
2 Key Features.............................................................................................................................................................................
3 Applications...............................................................................................................................................................................
4 Pin Assignments .......................................................................................................................................................................
4.1 Pin Descriptions....................................................................................................................................................................................
5 Absolute Maximum Ratings ......................................................................................................................................................
6 Electrical Characteristics...........................................................................................................................................................
6.1 Operating Conditions............................................................................................................................................................................
6.2 DC/AC Characteristics for Digital Inputs and Outputs..........................................................................................................................
6.3 Detailed System and Block Specifications ...........................................................................................................................................
1
1
1
4
4
6
7
7
7
9
6.3.1 Electrical System Specifications.................................................................................................................................................. 9
6.4 Current Measurement Ranges (across 100µΩ shunt resistor)............................................................................................................
9
6.4.1 Differential Input Amplifier for Current Channel......................................................................................................................... 10
6.4.2 Differential Input Amplifier for Voltage Channel......................................................................................................................... 11
6.4.3 Sigma Delta Analog to Digital Converter ................................................................................................................................... 12
6.4.4 Bandgap Reference Voltage...................................................................................................................................................... 12
6.4.5 Internal (Programmable) Current Source for External Temperature Measurement .................................................................. 13
6.4.6 CMREF Circuit (VCM) ............................................................................................................................................................... 13
6.4.7 Internal AVDD Power-on Reset................................................................................................................................................. 13
6.4.8 Internal DVDD Power-on Reset................................................................................................................................................. 14
6.4.9 Low Speed Oscillator................................................................................................................................................................. 14
6.4.10 High Speed Oscillator.............................................................................................................................................................. 14
6.4.11 External Clock.......................................................................................................................................................................... 14
6.4.12 Internal Temperature Sensor................................................................................................................................................... 15
6.5 System Specifications ........................................................................................................................................................................ 15
7 Detailed Description................................................................................................................................................................ 16
7.1 Current Measurement Channel .......................................................................................................................................................... 16
7.2 Voltage/Temperature Measurement Channel..................................................................................................................................... 16
7.3 Digital Implementation of Measurement Path..................................................................................................................................... 17
7.4 Modes of Operation............................................................................................................................................................................ 17
7.4.1 Normal Mode 1 (NOM1) ............................................................................................................................................................ 19
7.4.2 Normal Mode 2 (NOM2) ............................................................................................................................................................ 19
7.4.3 Standby Mode1 (SBM1) ............................................................................................................................................................ 20
7.4.4 Standby Mode2 (SBM2) ............................................................................................................................................................ 21
7.5 Reference-Voltage.............................................................................................................................................................................. 21
7.6 Oscillators........................................................................................................................................................................................... 21
7.7 Power-On Reset................................................................................................................................................................................. 21
7.8 4-Wire Serial Port Interface ................................................................................................................................................................ 22
7.8.1 SPI Frame.................................................................................................................................................................................. 22
7.8.2 Write Command......................................................................................................................................................................... 23
7.8.3 Read Command......................................................................................................................................................................... 24
7.8.4 Timing........................................................................................................................................................................................ 25
7.8.5 SPI Interface Timing .................................................................................................................................................................. 26
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AS8510
Datasheet - Contents
7.9 Control Register.................................................................................................................................................................................. 27
7.9.1 Standby Mode - Power Consumption........................................................................................................................................ 37
7.9.2 Initialization Sequence at Power ON ......................................................................................................................................... 38
7.9.3 Soft-reset of Device Using Bit D[7] of Reset Register 0x09....................................................................................................... 39
7.9.4 Soft-reset of the Measurement Path Using Bit D[7] of Reset Register 0x09 ............................................................................. 39
7.9.5 Reconfiguring Gain Setting of PGA .......................................................................................................................................... 40
7.9.6 Configuring the Device During Normal Mode ............................................................................................................................ 40
7.10 Low Side Current Measurement Application .................................................................................................................................... 41
8 Package Drawings and Markings ........................................................................................................................................... 42
8.1 Recommended PCB Footprint............................................................................................................................................................ 43
9 Ordering Information............................................................................................................................................................... 45
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AS8510
Datasheet - Pin Assignments
4 Pin Assignments
Figure 2. Pin Assignments (Top View)
1
2
20
19
INT
RSHH
RSHL
CLK
3
4
18
17
REF
SDI
MEN
VCM
5
6
16
15
AVDD
AVSS
CHOP_CLK
DVDD
AS8510
7
8
14
13
ETR
ETS
DVSS
SDO
SCLK
CS
9
12
11
VBAT_IN
VBAT_GND
10
4.1 Pin Descriptions
Table 1. Pin Descriptions
Pin Number
Pin Name
RSHH
Pin Type
Description
Positive Differential input for current channel
Negative differential input for current channel
1
2
Analog input
Analog output
Supply pad
RSHL
REF
Internal reference voltage to sigma-delta ADC; connect 100nF to
AVSS from this pin.
3
4
Common Mode voltage to the internal measurement path;
connect 100nF to AVSS from this pin.
VCM
+3.3V Analog Power-supply
0V Power-supply analog
5
6
AVDD
AVSS
7
ETR
Voltage channel single ended input
8
ETS
Analog input
Battery voltage (high) input
9
VBAT_IN
VBAT_GND
CS
Battery voltage (low) input
10
11
12
13
Chip select with an internal pull-up resistor (SPI Interface)
Clock signal (SPI Interface)
Digital input with pull-up
Digital input
SCLK
Serial Data Input (SPI Interface)
SDO
Digital output
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AS8510
Datasheet - Pin Assignments
Table 1. Pin Descriptions
Pin Number
Pin Name
DVSS
Pin Type
Description
0V Digital Ground
14
15
Supply pad
+3.3V Digital Supply
DVDD
Chop Clock used in High side measurements to synchronize
external chopper.
16
17
CHOP_CLK
MEN
(As an example, when AS8525 is used to condition the input
signal to the input range of AS8510, the chop clock is used by
AS8525.)
Digital output
Digital output issued during the Standby Mode (SBM) to signal
the short duration of data sampling. This signal is useful in the
case of a High Side Measurement application.
(For example: This signal is used by AS8525 device to wake-up
and enable the measurement path.)
Data signal (SPI Interface)
18
19
20
SDI
CLK
INT
Digital input
Digital I/O
By default this pin is the internal clock output which can be used
by a Microcontroller. The internal clock may also be disabled as
an output by programming Register 08. To use an external Clock,
Register 08 has to be programmed.
Active High Interrupt to indicate data is ready
Digital output
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AS8510
Datasheet - Absolute Maximum Ratings
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only. Functional operation of the
device at these or any other conditions beyond those indicated in Electrical Characteristics on page 7 is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Table 2. Absolute Maximum Ratings
Parameter
Electrical Parameters
Min
Max
Units
Notes
DC supply voltage (AVDD and DVDD)
Input voltage (VIN)
-0.3
-0.3
5
V
V
AVDD + 0.3
DVDD + 0.3
Input current (latchup immunity)
-100
100
mA
kV
AEC - Q100 - 004
AEC - Q100 - 002
(ISCR
)
Electrostatic Discharge
Electrostatic discharge (ESD) all pins
±2
Continuous Power Dissipation
SSOP20 in still air, soldered on JEDEC
standard board @ 125º ambient, static
operation with no time limit
Total power dissipation
(all supplies and outputs) (Pt)
50
mW
Temperature Ranges and Storage Conditions
Storage temperature (TSTRG
Junction temperature (TJ)
Thermal resistance (RthJC)
)
-50
125
130
80
ºC
ºC
K/W
JEDEC standard test board, 0 air velocity
Norm: IPC/JEDEC J-STD-020
The reflow peak soldering temperature (body
temperature) is specified according IPC/
JEDEC J-STD-020 “Moisture/Reflow Sensitivity
Classification for Nonhermetic Solid State
Surface Mount Devices”.
Package body temperature (TBODY
)
260
85
ºC
%
The lead finish for Pb-free leaded packages is
matte tin (100% Sn).
Humidity non-condensing
5
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AS8510
Datasheet - Electrical Characteristics
6 Electrical Characteristics
6.1 Operating Conditions
Table 3. Operating Conditions
Symbol
AVDD
AVSS
A - D
Parameter
Positive analog supply voltage
0V Ground
Conditions
Min
3.0
0
Max
3.6
0
Units
V
V
Difference in analog and digital supplies
Positive digital supply
0V Digital Ground
0.1
3.63
0
V
DVDD
DVSS
TAMB
2.97
0
V
V
Ambient temperature
Supply current
-40
125
5.5
ºC
mA
ISUPP
System clock frequency1
fCLK
4.096
MHz
1. Nominal clock frequency from external or internal oscillator.
6.2 DC/AC Characteristics for Digital Inputs and Outputs
All pull-up and pull-down have been implemented with active devices. SDO has been measured with 10pF load.
Table 4. INT
Symbol
ILEAK
VOH
Parameter
Conditions
Min
-1
Typ
Typ
Typ
Max
Units
µA
V
Tri-state leakage current
High level output voltage
Low level output voltage
Output Current
+1
2.5
VOL
0.4
4
V
IO
mA
Table 5. CS Input
Symbol
VIH
Parameter
Conditions
Min
Max
Units
V
High level input voltage
Low level input voltage
Input leakage current
Pull up current
2.0
VIL
0.8
+1
V
ILEAK
Ipu
-1
µA
µA
CS pulled to DVDD = 3.3V
-150
-15
Table 6. SDI
Symbol
VIH
Parameter
Conditions
Min
Max
Units
V
High level input voltage
Low level input voltage
Input leakage current
2.0
VIL
0.8
+1
V
ILEAK
-1
µA
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AS8510
Datasheet - Electrical Characteristics
Table 7. SDO Output
Symbol
VOH
VOL
Parameter
Conditions
Isource = 8mA
Isink = 8mA
Min
Typ
Typ
Typ
Max
Units
V
High level output voltage
Low level output voltage
Output Current
2.5
0.4
8
V
Io
mA
Table 8. CHOP_CLK Output
Symbol
Parameter
Conditions
Min
Max
Units
V
VOH
VOL
Io
High level output voltage
Low level output voltage
Output Current
2.5
0.4
4
V
mA
Table 9. CLK I/O with Input Schmitt Trigger and Output Buffer
Symbol
VIH
Parameter
Conditions
DVDD = 3.3V
DVDD = 3.3V
Min
Max
Units
V
High level input voltage
Low level input voltage
Input leakage current
Pull down current
2.4
VIL
1.0
+1
100
4
V
ILEAK
IPD
-1
µA
µA
mA
V
CLK pulled to DVSS
10
Io
Output Current
VOH
VOL
High level output voltage
Low level output voltage
2.5
0.4
V
Table 10. SCLK with Input Schmitt Trigger
Symbol
VIH
Parameter
Conditions
DVDD = 3.3V
DVDD = 3.3V
Min
Typ
Typ
Max
Units
V
High level input voltage
Low level input voltage
Input leakage current
2.4
VIL
1.0
+1
V
ILEAK
-1
µA
Table 11. MEN Output
Symbol
VOH
Parameter
Conditions
Min
Max
Units
V
High level output voltage
Low level output voltage
Output Current
2.5
VOL
0.4
2
V
IO
mA
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AS8510
Datasheet - Electrical Characteristics
6.3 Detailed System and Block Specifications
6.3.1 Electrical System Specifications
Table 12. Electrical System Specifications
Symbol
Parameter
Min
Typ
Max
Units
Notes
IDDNOM
Current consumption normal mode
3
5.5
mA
Average of NORMAL Mode Power
consumption over a period of 10sec
when the device is in STANDBY Mode
IDDSBM
Current consumption standby mode
40
µA
6.4 Current Measurement Ranges (across 100µΩ shunt resistor)
Table 13. Current Measurement Ranges
PGA
Gain
Nominal
1
PSR2
[dB]
Imax
[A]
Vsh
[mV]
Data Rate
(fOUT
VINADC
[mV]
Symbol
Parameter
)
I10
I200
I400
I1500
Input current range of 10A in NOM
Input current range of 200A in NOM
Input current range of 400A in NOM
Input current range of 1500A in NOM
±10
±200
±400
±1500
±1
±20
±40
±150
100
40
25
5
@ 1 kHz
@ 1 kHz
@ 1 kHz
@ 1 kHz
±100
±800
±1000
±750
60
60
60
60
Input current range of 1A in SBM 3
Input current range of 10A in SBM 3
Input current range of 200A in SBM 3
I1
±1
±0.1
±1
100
100
40
@ 1 Hz
@ 1 Hz
@ 1 Hz
±10
±100
±800
60
60
60
I10
±10
I200
±200
±20
1. VINADC = Vsh * Gain, gain deviations to be considered according to Table 15 and Table 16.
2. AVDD, DVDD of 3.3V with ±5% variation.
3. For low power current monitoring, single shot measurement is performed with internal oscillator.
Note: The Data Rate at the output can be calculated according to the formula:
fsout=2*fchop /R2 (R2 is down sampling ratio taking values 1, 2, 4 up to 32768 as powers of 2)
Table 14. Valid Combinations of the Chopper Clock, Oversampling Clock and Decimation Ratios
Over Sampling Frequency
1.024MHz
Chopper Frequency
Decimation Ratio
2kHz
2kHz
2kHz
4kHz
64
64
2.048MHz
2.048MHz
128
64
2.048MHz
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AS8510
Datasheet - Electrical Characteristics
6.4.1 Differential Input Amplifier for Current Channel
Table 15. Differential Input Amplifier for Current Channel
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VIN_AMP
Input voltage range
RSHH and RSHL
-160
+160
mV
RSHH and RSHL@ +160mV input
voltage at 125ºC with PGA
Input current 1, 11
IIN_AMP
ICM
-50
2
50
nA
-160
+300
Absolute input voltage range 2
mV
Gain1 3, 4, 9
Gain2 3, 4, 9
Gain3 3, 4, 9
G = G1
G = G2
G = G3
I10
100
40
25
5
I200
I400
Gain4 3, 4, 9
G = G4
e
I1500
Gain deviation
i = 1, 2, 3, 4
0.9 * Gi
15
1.1 * Gi
±0.3
Pole frequency 4, 5
fP_AMP
kHz
%
-20ºC to +65ºC
Gain 5, 25, referenced to room
temperature
Gain drift with temperature 6
Offset drift with temperature 7, 10
εT1
VOSDRIFT
Vos
350
µV
µV
After trim,
for temperature range -20 to +65ºC
350
Input referred offset 7, 10
Vos_ch
VNdin
THD
Chopping enabled
0
LSB
nV/√Hz
dB
Noise density 4, 8
25
70
Total harmonic distortion
For 150 Hz input signal
Notes:
1. Leakage test accuracy is limited by tester resource accuracy and tester hardware.
2. For gain 100 PGA input common mode is 0V and the minimum supply is 3.15V.
3. The measurement ranges are referred only by the gain of input amplifier, while other parameters such as bandwidth etc. are pro-
grammed independently.
4. This parameter is not measured directly in production. It is measured indirectly via gain measurements of the whole path. It is guaran-
teed by design.
5. Pole frequency of input amplifier changes with GAIN. The number is valid for the gain at G1, while the bandwidth will be higher for other
ranges. This parameter is not measured in production.
6. Based on device evaluation. Not tested.
7. These offsets are cancelled if chopping enabled (default).
8. Noise density calculated by taking system bandwidth as 150Hz.
9. Refer to Measurement Ranges shown in Table 13.
10. No impact on the measurement path. If the chopping is enabled, both the offset and offset drift will be eliminated.
11. For negative input voltages up to -160mV below ground, Input leakage is typically -20nA @ 65ºC due to forward conductance of
protection diode.
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AS8510
Datasheet - Electrical Characteristics
6.4.2 Differential Input Amplifier for Voltage Channel
Table 16. Differential Input Amplifier for Voltage Channel
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Input voltage range 1, 10
VIN_AMP
-160
+160
mV
VBAT_IN, ETR, ETS @ +160mV input
voltage at 125ºC with PGA
Input current 2, 10
IIN_AMP
ICM
-50
2
50
nA
-160
+300
Absolute input voltage range 3
mV
Gain1 4, 5
Gain2 4, 5
Gain3 4, 5
G = G1
G = G2
G = G3
100
40
25
5
Gain4 4, 5
G = G4
e
Gain deviation
i = 1, 2, 3, 4
0.9 * Gi
15
1.1 * Gi
Pole frequency 5, 6
fP_AMP
kHz
Noise density 5, 7
VNDIN
THD
25
70
nV/√Hz
Total harmonic distortion
For 150Hz input signal
dB
-20ºC to +65ºC
Gain 5, 25, referenced to room
temperature
Gain drift with temperature 8
εT1
±0.3
350
%
VOS
After trim at +65ºC
Chopping enabled
µV
LSB
µV
Input referred offset 9
Vos_ch
VOSDRIFT
0
Offset drift with temperature 9
350
Notes:
1. Input for the voltage channel can be as high as 1220mV, in this high input case PGA will be bypassed.
2. Leakage test accuracy is limited by tester resource accuracy and tester hardware, especially at low temperatures due to condensing
moisture.
3. For gain 100 PGA input common mode is 0V and the minimum supply is 3.15V.
4. The measurement ranges are referred only by the gain of input amplifier, while other parameters such as bandwidth etc. are pro-
grammed independently.
5. This parameter is not measured directly in production. It is measured indirectly via gain measurements of the whole path. It is guaran-
teed by design.
6. Pole frequency of input amplifier changes with changing the GAIN. The number is valid for the gain at G1, while the bandwidth will be
higher for other ranges. This parameter is not measured in production.
7. Noise density calculated by taking system bandwidth as 150Hz.
8. Based on device evaluation. Not tested.
9. No impact on the measurement path. If the chopping is enabled, both the offset and offset drift will be eliminated.
10. For negative input voltages up to -160mV below ground, Input leakage is typically -20nA @ 65ºC due to forward conductance of
protection diode.
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AS8510
Datasheet - Electrical Characteristics
6.4.3 Sigma Delta Analog to Digital Converter
Table 17. Sigma Delta Analog to Digital Converter
Symbol
VREF
Parameter
Reference voltage 6
Conditions
Min
Typ
Max
Units
1.225
V
Input range 1
VINADC
At Vref = 1.22V
0
±1.22
128
V
Oversampling ratio/Decimation Ratio 2
R1
64
128
1024/
2048
Oversampling frequency 3
fovs
kHz
RES
BW
16
bits
Hz
dB
Number of bits
Bandwidth 4
1
500
Signal to noise ratio 5
S/N
90
Notes:
1. Production test at ±800mV. Maximum VIN can be 1.22V with VREF=1.225V.
2. Programmable. It is defined with respect to the first decimator in the ΣΔ ADC.
3. Programmable: Internal clock is 1024/2048 kHz; external clock max is 8192 kHz.
4. Dependent on fovs, R1 and R2. The bandwidth is calculated according to the formula:
BW=fovs/(2*R1*R2); the sampling frequency at the output of the A/D converter is 2*BW.
5. Defined at maximum input signal, BW=500 Hz (1Hz to 500 Hz), fovs=1024 kHz, R1=64, fchop=2 kHz and R2=2.
6. Reference voltage might be forced from external.
6.4.4 Bandgap Reference Voltage
Table 18. Bandgap Reference Voltage
Symbol
VREFTRIM
VREFACC
Parameter
Conditions
Min
Typ
Max
Units
Reference Voltage after trim 1, 2
Reference Voltage Initial Accuracy 1, 2
Trim at 65ºC
1.225
V
At 65ºC
±3.5
±0.4
mV
%
Temperature range
-20 to 65 ºC
VREFDRIFT
Reference Voltage Temperature drift
Temperature range
-40 to 125 ºC
+0.4/
-0.6
%
PSRRREF
SUTAVDD
PSR @ dc
80
5
dB
ms
Start Up Time with supply ramp 3
Start Up Time from power down 3
Output resistance of band gap
SUTPD
RNDVREF
VNDVREF
CLVREF
1
ms
Ω
500
100
1000
300
Bandgap reference thermal noise density 3
nV/√Hz
nF
Output Capacitor (Ceramic)
ESRVREF
0.02
1
Ω
Notes:
1. Accuracy at 65ºC.
2. No DC current is allowed from this pin.
3. This is a design parameter and not production tested.
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AS8510
Datasheet - Electrical Characteristics
6.4.5 Internal (Programmable) Current Source for External Temperature Measurement
Table 19. External Temperature Measurement
Symbol
ICURON
Parameter
Conditions
Min
Typ
270
10
Max
Units
µA
5-bit current source enabled 1
5-bit current source disabled
5-bit programmable current source
Limited by leakage
0
320
ICUROFF
nA
ppm
/ ºK
Temperature coefficient of current source 2
Voltage on pin ETR 3
TK_CS
1000
VMAXETR
1000/G
1.22
mV
V
Max voltage on pin ETR when PGA is
bypassed 4
VMAXETRMOD
VMAXETS
Voltage on pin ETS for resistor sensor 3
1000/G
1.22
V
Max. Voltage on pin ETS when PGA is
bypassed 5
VMAXETSMOD
V
Notes:
1. Current value can be programmed in steps of 8μA from 0 to 256μA with a process error of 30%.
2. Temperature coefficient is not important since external temperature measurement is a 2 step measurement. The value specified is
guaranteed by design and will not be tested in production.
3. Maximum voltage on pin ETR (reference) can be calculated by given formula, where G is the gain of PGA (G=100).
4. Maximum voltage on pin ETR, if PGA is bypassed.
5. Maximum voltage on pin ETS, if PGA is bypassed.
6.4.6 CMREF Circuit (VCM)
Table 20. CMREF Circuit
Symbol
VVCM
CL
Parameter
Output voltage
Load capacitance
Min
Typ
1.7
Max
Units
V
1.6
1.8
100
nF
6.4.7 Internal AVDD Power-on Reset
Table 21. Internal AVDD Power-on Reset
Symbol
Parameter
Min
Typ
Max
Units
Power On Reset Threshold
VPORHIA
2.2
2.4
2.6
V
POR time - The duration from Power ON till
the time, internal Power On Reset signal
tPORA
1
µs
goes HIGH1
Current consumption in POR block2
IPORA
1.5
µA
1. POR pulse is always longer than tPORA whatever the slope of the supply.
2. IPORA can not be switched off.
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6.4.8 Internal DVDD Power-on Reset
Table 22. Internal DVDD Power-on Reset
Symbol
Parameter
Min
Typ
Max
Units
Power On Reset Threshold
VPORHID
2.2
2.4
2.7
V
Hysteresis1
VHYST
tPORD
IPORD
0.2
1
0.25
0.4
V
POR time - The duration from Power ON till the
time, internal Power On Reset signal goes
µs
µA
HIGH2
Current3
1.5
1. VPORLO = VPORHI - VHYST where VPORLO is the lower threshold of POR.
2. VPORLO = VPORHI - VHYST where VPORLO is the lower threshold of POR.
3. IPORD can not be switched off.
6.4.9 Low Speed Oscillator
Table 23. Low Speed Oscillator
Symbol
fLS
Parameter
Frequency
Min
Typ
Max
Units
kHz
%
262.144
fLS_ACC
ILS
Accuracy
± 7
5
Supply current
µA
6.4.10 High Speed Oscillator
Table 24. High Speed Oscillator
Symbol
Parameter
Min
Typ
Max
Units
fHS
Frequency
4.096
MHz
Accuracy 1, 2
fHSACC
IHS
±4
%
Supply current
300
µA
Notes:
1. Accuracy after trimming.
2. Accuracy for limited temperature range of -20 to 65 ºC.
6.4.11 External Clock
Table 25. External Clock
Symbol
Parameter
Conditions
Min
Typ
Max
Units
2048/
4096/
8192
fCLKEXT
Clock frequency
kHz
to be programmed in Register 08
CLK_REG through the serial bus SPI.
DIVCLKEXT
DCCLKEXT
Clock division factor
2/4/8
Duty Cycle of external clock
40
60
%
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Datasheet - Electrical Characteristics
6.4.12 Internal Temperature Sensor
Table 26. Internal Temperature Sensor
Symbol
TINTRNG
ΔTIN
Parameter
Conditions
Min
Typ
Max
Units
ºC
Temperature sensor range
Temperature measurement accuracy
-40
125
3
ºC
Guaranteed by design; at PGA gain 5
which is the recommended Gain for
internal temperature measurement.
TINTSLP
Temperature sensor slope
27
Digits/C
Digits
TINT65G5
Temperature sensor output at gain 5
40660
41807
43012
6.5 System Specifications
Table 27. System Specifications
Symbol
Parameter
Min
Typ
Max
Units
Channel to channel isolation 1
IS
-90
dB
dB
Difference in channel to channel attenuation
@600Hz 1, 2
At
3
5
Difference in phase shift between the two
channels @600Hz 1, 2
Ph
Deg
System Measurement Error Budget for Voltage and Current Channel.
Temperature Range: -20ºC to +65ºC; Output data rate is 1kHz, VCC = 3.3V, chopping enabled.
Table 28. System Measurement Error Budget for Gains 5 and 25
Symbol
Parameter
Conditions
Min
Typ
Max
Units
System measurement error 3, 4
Err
±0.5
±0.8
%
%
From device evaluation
±0.3
Measurement error due to PGA gain drift
Measurement error due to VREF drift6
±0.4
%
%
Measurement error due to non-linearity of PG Tested by distortion measurements
±0.025
Notes:
1. These specifications are defined by taking one channel as reference and measured on the other channel.
2. Guaranteed by design.
3. System measurement error due to noise, individual block parameter drifts and non linearity. Based on evaluation, not tested.
4. System error due to offset is neglected because of chopper architecture.
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7 Detailed Description
The AS8510 consists of two independent high resolution 16-bit SD analog to digital conversion channels. The measurement path of these two
channels integrates a programmable gain amplifier, chopper and de-chopper, sigma-delta modulator, decimator and a digital filter for
simultaneous measurement of Current and Voltage/Temperature.
The two measurement channels, namely the Current and Voltage/Temperature measurement channels have identical data path.
The input signal is amplified in the Programmable Gain Amplifier (PGA) with any of the selected gains of 1, 5, 25, 40 and 100 facilitating
measurement of a wide range of Current, voltage and temperature levels. Gain Settings for different input ranges and any associated restrictions
are explained in the Table 13.
Offset in the measurement path is minimized with the use of a chopper and a de-chopper at appropriate stages in the data path. By default the
chopper/de-chopper is ON in the measurement path. It may be disabled by programming the appropriate register.
The amplified input signal is converted into a single-bit pulse-density modulated stream by the Σ-Δ Modulator. A decimator acting as a low-pass
filter filters out the quantization noise and generates 16-bit data corresponding to the input signal. The decimation ratios of 64, 128 may be
selected in the first filter stage. For reducing data rate further, the second stage decimation can be used.
An optional FIR Filter is provided to offer matched low pass filter response typically required in lead acid battery sensor systems.
7.1 Current Measurement Channel
The voltage across a Shunt Resistor, connected in series with the Battery negative terminal, forms the input signal to the Current Measurement
channel. RSHH and RSHL are the Current measurement input pins. Offset in the input signal is nullified with the use of a chopper and a de-
chopper at appropriate stages in the data path. The programmable gain amplifier in the data path with programmable settings of 1, 5, 25, 40 and
100 enables measurement of current ranges from ±1A to ±1500A. The sampled input signal is converted into a single-bit pulse-density
modulated stream by the Σ-Δ Modulator. A decimator acting as a low-pass filter filters out the quantization noise and generates 16-bit data
equivalent to the input current signal. The programmable input sampling rate and the decimation ratio determine the output data rates. The data
path can be programmed to provide 1Hz to 2 kHz rates in the various modes available. An optional FIR filter is provided to offer matched low
pass filter response typically required in lead acid battery sensor systems.
After enabling the current measurement channel, the delay for the availability of the first sample is two conversion cycles.
7.2 Voltage/Temperature Measurement Channel
The other two parameters of the Battery for measurement are Voltage and its Temperature. The second channel accepts signals from four
independent sources through a Multiplexer as listed below:
An attenuated battery voltage obtained through appropriate external resistor divider, (or)
A signal from the external temperature sensor, (or)
A signal from external reference, (or)
A signal from the internal temperature sensor.
Apart from this difference in the multiplexing of four input signals, the rest of the data path is identical to the Current measurement channel.
RSHH and RSHL are the Current measurement input pins
The Battery Voltage which can go up to 18V is attenuated through a Resistor Divider externally and is applied to the Voltage Channel. For
Automotive Battery measurement, the Gain of the PGA should be restricted to 5 and 25. The latency for the first result from the voltage
measurement channel is two conversion cycles.
A second option on this measurement channel is to measure Temperature. Internally generated constant current is pumped through the
Temperature Sensor with positive temperature coefficient, and, a high- precision resistor. The voltages across the sensor and the resistor form
the inputs to the measurement channel one at a time. The difference between the two voltages which is independent of the magnitude of the
current is used to determine the temperature accurately. The Voltage across the sensor is applied between the ETS and VSS pins and, the
voltage across the high-precision resistor is applied between ETR and VSS. External Temperature measurement involves the acquisition of two
signals one after the other using the same constant current source. The latency for the first result from the temperature measurement channel is
two conversion cycles.
A third option on the measurement channel is to measure the internal temperature. Hence, one of the three options for measurement of Battery
Voltage, External Temperature and, internal temperature may be carried out by selection of appropriate inputs through the internal multiplexer
selection.
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7.3 Digital Implementation of Measurement Path
Figure 3. Block Diagram of Digital Implementation
R2
FIR_MA_SEL
R1
fchop * 2 / R2
fchop * 2 / R2
fchop * 2
fmod / R1
MOD_IN
CIC1
64 / 128
Dechopper
CIC2
FIR/MA
DATAOUT
fmod
R1
MOD_CLK
fchop
R1 = First decimation ratio (64 or 128)
R2 = Second decimation ratio (1 to 32768)
CHP_CLK
CLK DIVISION
BLOCK
MOD_CLK
Figure 3 shows the digital implementation of the decimator and filter to process the 1-bit output of the Modulator. This block receives a 1-bit pulse
density modulated output (MOD_IN) from the second order sigma delta modulator along with the oversampling frequency clock (MOD_CLK).
The MOD_CLK directly goes to a clock division block, which generates chopper clock (CHOP_CLK). The CHOP_CLK can be one of 2kHz or
4kHz selected by Register CLK_REG in Table 33. The MOD_CLK can be either 1MHz or 2MHz. The Decimation is a two phase process. In the
first phase, the R1 down sampling rate can be obtained by selecting either 64 or 128 in Registers DECREG_R1_I, DECREG_R1_V in Table 33.
The 16-bit CIC1 output is dechopped with respect to CHOP_CLK. The output of Dechopper is passed through the CIC2 filter with a decimation
ratio of 1to 32768 in steps of power of 2. This output is then processed through a FIR or Moving Average (MA) filter. FIR Filter is provided to offer
matched low pass filter response typically required in lead acid battery sensor systems. MA filter is used to provide averaged output and the
number of samples for averaging can be any integer value from 1 to 15.
7.4 Modes of Operation
The device operates in four different modes, namely,
Normal Mode 1 (NOM1),
Normal Mode 2 (NOM2),
Standby Mode 1 (SBY1), and,
Standby Mode 2 (SBY2).
The Normal Modes are full-power modes with the exception that in Normal Mode 2, sampling is normally at a programmed lower frequency and
is increased to a higher rate only when a measured input signal level crosses the programmed threshold in the current measurement channel.
The Standby Modes are lower power modes. Sampling is normally at a very low frequency interval. In Standby Mode 2, data sampling can be
carried out only when the internal comparator detects the input current to be greater than the programmed threshold and it generates interrupt on
the INT pin.
The device enters into the “Stop” state on Power On. This is a state where in the data path is inactive and can be entered into from any of the
four Modes. The State transition Diagram involving the state of Stop and the four Modes is illustrated in the Figure 4.
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Figure 4. State Transition Diagram
RESET
Wait for otp_load
Completes in 32 cycles
of lp_clk
OTP_INT
STOP
1.5msec &
NORM
Analog Stablization
period
Wait for 1.5msec
A_STB
NORM
NORM
or
stop
Wait for x
number of
conversions
Wait for TT1
timeout
SBM
SBM_ON
SBM_OFF
Note:
1. Device soft reset can be written in any of the following states STOP, A_STB, SBM_ON, SBM_OFF by writing “0” into D[7] of the RESET
_REG (Address 0X09).
2. Measurement path of soft reset should be written in any the states, STOP, SBM_OFF by writing “0” into D[6] of the RESET _REG (Address
0X09).
3. When soft reset is used for the measurement path or for the device, external clock needs to be disabled if the system clock is external
clock in the application.
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7.4.1 Normal Mode 1 (NOM1)
On Power-on-reset of the device, AS8510 goes into STOP State.
Transition to Normal mode1 (NOM1) occurs when the “START BIT” D0 of Mode Control Register MOD_CTL_REG in Table 33 is set to “1”
through the serial port SPI. Data Rate of voltage and current channels can be independently programmed and both the channels generate
interrupts for every output available from ADC. The interrupt signal is generated on the INT pin. The width of the interrupt pulse is eight cycles of
lp_clk. The data is stable up to the next interrupt. If the data rate is different for the two channels, the interrupt rate would follow the higher rate
among the two channels. Data update can be known by reading the status register. The functionality is explained in the waveform shown in
Figure 5. When the device is configured to NORMAL Mode1 from any mode the configuration should be through the STOP state only.
Figure 5. Normal Mode 1
I
IDATA
Sampling with f1
t
V,T
V,TDATA
Sampling with f2
STOP
t
START
Current Channel
DATA Register
Voltage Channel
DATA Register
INT at f1 rate from
current channel
T
INT
Interrupt from the current channel is at f1 rate which is integer multiple of f2 rate from voltage channel
7.4.2 Normal Mode 2 (NOM2)
NOM2 differs from NOM1 in such a way that it allows for a relaxed data rate at a period of TMC by programming the corresponding register as
long as the amplitude of current is less than a programmed threshold ITHC. However, when, the measured input signal exceeds the programmed
threshold, the data rate is changed to the rate of NOM1 mode.
Transition to NOM2 occurs when the “START BIT” D0 of Mode Control register MOD_CTL_REG in Table 33 is set to 1 and mode control bits to
01 through SPI. In this mode the data rate should be programmed with the time of TMC. An interrupt signal is generated on INT at the rate of TMC
secs with a pulse width of eight cycles of lp_clk. The data is stable up to the next interrupt. The data sample is compared against the programmed
threshold and when it is exceeded, the data sampling rate is changed to provide data at the data rate of NOM1 mode. However, as soon as the
data sample amplitude falls below the programmed threshold, the sampling rate is restored to provide data at the rate of TMC. The functionality is
illustrated in the waveform Figure 6.
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Figure 6. Normal Mode 2
I
I < I THS
V,I,T
V,I,T
V,I,T
V,I,T
V,I,T
IDD
TMC
TMC
ITHS
t
Sampling with f
I > ITHS
INT
T
INT
7.4.3 Standby Mode1 (SBM1)
The low-power Standby Mode can be entered only through the STOP state. Transition to SBM1 mode occurs when the “START BIT” D0 of Mode
Control register MOD_CTL_REG in Table 33 is set to “1” and Mode Control Bits to “10” through SPI. In this mode the date rate is programmable
with the time of Ta. An interrupt signal is generated on INT at the rate of Ta secs., and with a pulse width of eight cycles of lp_clk. The data is
stable up to the next interrupt. The functionality is illustrated in Figure. During the period of Ta, only one data sample is made available and,
during the rest of the period, the device is maintained in STOP state to reduce power consumption. The microcontroller which receives the data
on the Interrupt, is also expected to be processing the data for a short time as shown clearly in the Figure 7 to ensure the overall low-power
consumption of the data acquisition and processing system.
Figure 7. Standby Mode 1
I DD
MCU
MCU
MCU
V, I, T
V, I, T
ADC
t
Ta sec.
Ta sec.
Ta sec.
T
conv
T
conv
T
conv
Start SBM1
Channel
DATA Register
DATA – A0
DATA – A1
DATA – A2
DATA – A3
INT
T
INT
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7.4.4 Standby Mode2 (SBM2)
Standby Mode 2 is an extension of the Standby Mode1 to achieve even a lower power in the data acquisition system by providing interrupt to the
microcontroller only when the data sample exceeds the set current threshold. The Standby Mode can be entered only through the STOP state.
Transition to SBM2 mode occurs when the “START BIT” D0 of Mode Control register MOD_CTL_REG in Table 33 is set to “1” and Mode Control
Bits D7,D6 to “1,1” through SPI. In this mode the date rate is programmable with the time of Ta in the Ta control registers B, C. The data sample
is made available and an interrupt signal is generated on INT pin only when the input signal exceeds the threshold set in Current Threshold
Registers D,E. It should be noted here that the data is stable for Ta secs. The functionality is illustrated in Figure 8.
Figure 8. Standby Mode 2
IDD
MCU
|I| > I Threshold I
I
ADC
t
T
a
sec.
Ta sec.
Ta sec.
T
conv
T
conv
Tconv
Start SBM2
Channel
DATA Register
DATA – A3
DATA – A0
DATA – A1
DATA – A2
INT
T
INT
7.5 Reference-Voltage
Band gap-reference voltage is used for the ADC as a reference and for the generation of the current for external temperature measurement.
7.6 Oscillators
A High-speed oscillator (HS) generates the oversampling clock. For internal state machine and Interrupt generation, a low-speed Oscillator (LS)
is also available.
7.7 Power-On Reset
The AS8510 has PORs, APOR and DPOR on analog and digital power supplies respectively. On PORs of both supplies, initialization sequence
happens and the system status is shown in state diagram (see Figure 4).
As shown in the state diagram, the system is in RESET state until DPOR output goes to logic HIGH and subsequently until APOR output goes to
logic HIGH. Once analog power supply is available, the system goes into OTP_INT state and loads the default values into the control and data
registers and goes into STOP state. If analog POR, APOR goes low at any time, the system goes into RESET state. In the STOP state, the
AS8510 can be programmed and by giving start command it starts working following the state machine.
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7.8 4-Wire Serial Port Interface
The SPI interface is used as interface between the AS8510 and an external micro-controller to configure the device and access the status
information. The micro-controller begins communication with the SPI which is configured as a slave. The SPI protocol is simple and the length of
each frame is an integer multiple of bytes except when a transmission is started. Each frame has 1 command bit, 7 address/configuration bits,
and one or more data bytes. The edge of CS and the level of SCLK during the start of a SPI transaction, determine the edge on which the data is
transferred from the SPI and the edge on which the data is sampled by the slave. Table 29 describes the setting of the transfer and sampling
edges of SCLK. Figure 9 shows the falling edge and rising edge for data transfer and data sampling respectively, when SCLK is HIGH on the
falling edge of CS.
Table 29. CS and SCLK
CS
SCLK
LOW
HIGH
ANY
Description
Serial data transferred on rising edge of SPI clock. Sampled at falling edge of SPI clock.
Serial data transferred on falling edge of SPI clock. Sampled at rising edge of SPI clock.
Serial data transfer edge is unchanged.
FALL
FALL
ANY
Figure 9. Protocol for Serial Data Write with Length = 1
CS
SCLK
0
A5
A4
A3
A2
A1
A0 D7
D6
D5
D4
D3
D2
D1
D0
A6
SDI
SDO
Data D7 – D0 is moved
to Address A4..A0 here
Transfer edge
Sampling edge
7.8.1 SPI Frame
A frame is formed by a first byte for command and address/configuration and a following bit stream that can be formed by an integer number of
bytes. Command is coded on the 1 first bit, while address is given on LSB 7 bits (see Table 30).
Table 30. Command Bits
Command Bits
Register Address or Transmission Configuration
C0
A6
A5
A4
A3
A2
A1
A0
Table 31. Command Bits
C0
0
Command
WRITE
<A6:A0>
ADDRESS
ADDRESS
Description
Writes data byte on the given starting address.
Read data byte from the given starting address.
1
READ
If the command is read or write, one or more bytes follow. When the micro-controller sends more bytes (keeping CS LOW and SCLK toggling),
the SPI interface increments the address of the previous data byte and writes/reads data to/from consecutive addresses.
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7.8.2 Write Command
For write command, C0=0. After the command code C0 is transferred, the address of register to be written is provided from MSB to LSB.
Subsequently one or more data bytes can be transferred from MSB to LSB. For each data byte following the first one, used address is the
incremented value of the previously written address. Each bit of the frame has to be driven by the SPI master on the SPI clock transfer edge. The
SPI slave samples it on the next clock edge. These edges are determined by the level of SCLK as shown in Table 29. Figure 10 and Figure 11
are examples of write command without and with address self-increment.
Figure 10. Protocol for Serial Data Write with Length = 1
CS
SCLK
0
A5
A4 A3
A2
A1
A0 D7
D6
D5
D4 D3
D2
D1
D0
A6
SDI
SDO
Data D7 – D0 is moved
to Address A4..A0 here
Figure 11. Protocol for Serial Data Write with Length = 4
CS
SCLK
D D D D D D D D
D D D D D D D D
A
4
A A A A
3 2 1 0
D D D D D D D D D D D D D D D D D D D D D D D D
A A
6 5
0
SDI
7 6
5 4 3 2 1 0
5 4 3 2 1 0
7 6
7 6
5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
SDO
Data D7-D0 is
moved to Address
A4-A0 here
Data D7-D0 is
moved to Address moved to Address moved to Address
A4-A0 +1 here A4-A0 +3 here
Data D7-D0 is
Data D7-D0 is
Data D7-D0 is
moved to Address
A4-A0 +4 here
A4-A0 +2 here
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7.8.3 Read Command
For Read command C0=1. After the command code C0, the address of register to be read is provided from MSB to LSB. Then one or more data
bytes can be transferred from the SPI slave to the master, always from MSB to LSB. To transfer more bytes from consecutive addresses, SPI
master keeps CS signal LOW and SPI clock active as long as it desires to read data from the slave. Each bit of the command and address of the
frame is to be driven by the SPI master on the SPI clock transfer edge where SPI slave samples it on the next SPI clock edge.
Each bit of the data section of the frame is driven by the SPI slave on the SPI clock transfer edge and SPI master samples it on the next SPI
clock edge. These edges are determined as per Table 29 and examples of read command without and with address self-increment.
Figure 12. Protocol for Serial Data Read with Length = 1
CS
SCLK
A6
1
A5
A4
A3
A2
A1
A0
SDI
SDO
D7
D6
D5
D4
D3
D2
D1
D0
Data D7 – D0 at
Address A4..A0 is
read here
Figure 13. Protocol for Serial Data Read with Length = 4
CS
SCLK
A
6
A A A A A A
4 3 2 1 0
5
1
SDI
D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
SDO
Data D7-D0 at
Address A4-A0 Address A4-A0 +1 Address A4-A0 +2 Address A4-A0 +3 Address A4-A0 +4
is read here is read here is read here is read here is read here
Data D7-D0 at
Data D7-D0 at
Data D7-D0 at
Data D7-D0 at
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7.8.4 Timing
In the following timing waveforms and parameters are exposed.
Figure 14. Write Timing for Writing
CS
...
...
tCPS tCPHD
tSCLKH
tSCLKL
tCSH
SCLK
CLK
polarity
tDIS
tDIH
...
...
DATAI
DATAI
DATAI
SDI
SDO
Figure 15. Read Timing for Reading
CS
tSCLKH
tSCLKL
SCLK
DATAI
DATAI
SDI
tDOD
tDOHZ
DATAO (D7 )
DATAO (D0 )
SDO
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7.8.5 SPI Interface Timing
Table 32. SPI Interface Timing
Symbol
General
Parameter
Conditions
Min
Typ
Max
Units
BRSPI
TSCLKH
TSCLKL
Write timing
tDIS
Bit rate
1
Mbps
ns
Clock high time
Clock low time
400
400
ns
Data in setup time
Data in hold time
CS hold time
20
20
20
ns
ns
ns
tDIH
TCSH
Read timing
tDOD
Data out delay
80
80
ns
ns
Time for the SPI to release the SDO
bus
tDOHZ
Data out to high impedance delay
Timing parameters when entering 4-Wire SPI mode (for determination of CLK polarity)
Clock setup time
(CLK polarity)
Setup time of SCLK with respect to CS
falling edge
tCPS
20
20
ns
ns
Clock hold time
(CLK polarity)
Hold time of SCLK with respect to CS
falling edge
tCPHD
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7.9 Control Register
This section describes the control registers used in AS8510. Registers can be broadly classified into the following categories.
Data access registers
Status Registers
Digital signal path control registers
Digital Control registers
Analog Control Registers
Table 33. Control Registers
Addr in
HEX
Register Name
POR Value
R/W
8-bit Control / Status Data
Data Access Registers
DREG_I1
(ADC Data Register for Current)
00
0000_0000
0000_0000
0000_0000
0000_0000
R
R
R
R
D[7:0]
D[7:0]
D[7:0]
D[7:0]
Denotes the Current ADC MSB Byte (ADC_I[15:8])
Denotes the Current ADC LSB Byte (ADC_I[7:0])
Denotes the Voltage ADC MSB Byte (ADC_V[15:8])
Denotes the Voltage ADC LSB Byte (ADC_V[7:0])
DREG_I2
(ADC Data Register for Current)
01
02
03
DREG_V1
(ADC Data Register for Voltage)
DREG_V2
(ADC Data Register for Voltage)
Status Registers
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
NOM1/NOM2 Data Ready
NOM2 Threshold Crossover
SBM1 Data Ready
SBM2 Threshold Crossover
APOR status
04
STATUS_REG
0000_0000
R
Data from current channel updated
Data from voltage channel updated
Reserved
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AS8510
Datasheet - Detailed Description
Table 33. Control Registers
Addr in
HEX
Register Name
POR Value
R/W
8-bit Control / Status Data
Digital Signal Path Control Registers for Current Channel
This bit selects decimation rate is used for current
channel. Default is 0 (Down Sampling Rate is 64)
D[7]
0
1
Down Sampling Rate is 64
Down Sampling Rate is 128
These two bits select division ratio of oversampling
frequency clock MOD_CLK to be used as chopper
clock, CHOP_CLK.
Default is “10” (divide by 512)
00
01
10
11
Chopper Clock Always High
Divide by 256
D[6:5]
Divide by 512
Divide by 1024
These four bits select the decimation ratio of second
CIC stage. Default is “0010” (equal to 4)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
2
4
8
05
DEC_REG_R1_I
0100_ 0101 R/W
16
32
64
D[4:1]
128
256
512
1024
2048
4096
8192
16384
32768
CIC1 Saturation Interrupt Mask Control.
Default is 1
D[0]
0
1
Unmask
Mask
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AS8510
Datasheet - Detailed Description
Table 33. Control Registers
Addr in
HEX
Register Name
POR Value
R/W
8-bit Control / Status Data
D[7]
D[6]
I-Channel Enable, Default 1=enable
V-Channel Enable, Default 1=enable
Interrupt polarity
D[5]
D[4]
0
1
Active high
Active low
. Interrupt Mask Control for Current Channel Data
Ready Interrupt on INT pin (Default is 0)
0
1
Unmasked
Masked
These two bits select the source of output 16-bit data in
Normal mode from Current channel. Default is 01
06
DEC_REG_R2_I
1100_0101
R/W
00
01
10
11
FIR / MA Output
CIC2 Output
D[3:2]
D[1:0]
Dechop/Demod Output
CIC1 Output
These two bits select the source of output 16-bit data in
SBM mode from Current channel. Default is 01
00
01
10
11
FIR / MA Output
CIC2 Output
Dechop/Demod Output
CIC1 Output
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Datasheet - Detailed Description
Table 33. Control Registers
Addr in
HEX
Register Name
POR Value
R/W
8-bit Control / Status Data
This bit selects FIR / MA Filter in Current channel.
Default is 0 (FIR)
D[7]
0
1
FIR
MA Filter
These bits select the number of data samples for
averaging in MA filter in Current channel.
Default is 0000 (bypass)
0000
0001
0011
0111
1111
bypass
D[6:3]
1
3
7
07
FIR CTL_REG_I
0000_0100
R/W
15
These two bits select the Measurement Path
architecture in both Current and Voltage channels.
Default is 10 (Dechopper after CIC)
00
01
Demodulator after CIC1
Demodulator before CIC1
D[2:1]
D[0]
Dechopper after CIC1
(preferred and suggested)
10
11
Demodulator before CIC1 with settled
sample
Reserved. Default 0. Do not change
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AS8510
Datasheet - Detailed Description
Table 33. Control Registers
Addr in
HEX
Register Name
POR Value
R/W
8-bit Control / Status Data
Digital Control Registers
Oversampling frequency clock selection. Default is 00
(high speed (HS) internal Clock)
00
01
10
Internal HS Clock with No Clock Output
Internal HS Clock with Clock Output
External Clock
D[7:6]
D[5:4]
These two bits select the division ratio for HS clock/
external clock. Default is 10 (division by 4)
00
01
10
11
No division
Divide by 2
Divide by 4
Divide by 8
CLK_REG
(Clock Control Register)
08
0010_0000
R/W
These two bits select the division ratio of HS clock, by
which it should be divided before providing it on CLK
pin. Default is 00 (No Division)
00
01
10
11
No Division
Divide by 2
Divide by 4
Divide by 8
D[3:2]
D[1]
This bit selects the division ratio of LS clock
LS _CLK undivided (Low Speed clock)
LS _CLK divide by 2
0
1
D[0]
D[7]
Reserved
Entire device can be soft reset by writing “0” into this
register bit. This bit will take a default 1 value on coming
out of Reset
RESET_REG
(Reset Control Register)
09
1100_0000
R/W
Measurement Path can be soft reset by writing “0” into
this register bit. This bit will take a default 1 value after
Measurement Path is reset.
D[6]
D[5:0]
Reserved
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AS8510
Datasheet - Detailed Description
Table 33. Control Registers
Addr in
HEX
Register Name
POR Value
R/W
8-bit Control / Status Data
These two bits select the operating mode of the Device.
Default is 00 (Normal Mode 1)
00
01
10
11
Normal Mode 1
Normal Mode 2
Standby Mode 1
Standby Mode 2
D[7:6]
These three bits select the number of cycles to be
ignored before comparison with the set threshold in
Standy Mode. Default is 000 (3 cycles of data)
000
001
010
011
100
101
110
111
3 cycles of data
4 cycles of data
5 cycles of data
6cycles of data
7 cycles of data
8 cycles of data
9 cycles of data
10 cycles of data
D[5:3]
MOD_CTL_REG
(Mode Control Registers)
0A
0000_0000
R/W
This bit controls the CHOP_CLK availability on
CHOP_CLK pin.
Default is 0
D[2]
D[1]
0
1
Disabled
Enabled
Enabling the MEN pin to indicate transition from
Standby to Normal Mode.
0
1
Disabled
Enabled
This bit is used to take the device from STOP state to
any of the Modes based on D[7:6] selection of this
register.
D[0]
D[7]
0
1
Retain in STOP state
Enables transition to Normal or Standby
Modes.
Unit of Ta in SBM1/SBM2. Default is 1
Unit is in milliseconds
Unit is in seconds
0
1
MOD_Ta_REG1
(Ta Control Register)
0B
1000_0000
D[6:0]
D[7:0]
MSB value of Ta
MOD_Ta_REG2
(Ta Control Register)
Unit of Ta in SBM1/SBM2
LSB value of Ta
0C
0D
0E
0000_0000
0000_0000
0000_0000
R/W
R/W
R/W
MOD_ITH_REG1
(Current Threshold Register)
D[7:0]
D[7:0]
MSB bits of 16 bits SBM2 threshold register
LSB bits of 16 bits SBM2 threshold register
MOD_ITH_REG2
(Current Threshold Register)
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AS8510
Datasheet - Detailed Description
Table 33. Control Registers
Addr in
Register Name
POR Value
0000_0000
0000_0000
R/W
R/W
R/W
8-bit Control / Status Data
HEX
MOD_TMC_REG1
(TMC Control Registers)
MSB value of number of data samples to be dropped
from ADC before sending Interrupt in NOM2
0F
D[7:0]
D[7:0]
MOD_TMC_REG2
(TMC Control Register)
LSB value of number of data samples to be dropped
from ADC before sending Interrupt in NOM2
10
11
12
NOM_ITH_REG1
NOM_ITH_REG2
0000_0000
0000_0000
R/W
R/W
D[7:0]
D[7:0]
Eight MSB bits of NOM2 current threshold register
Eight LSB bits of NOM2 current threshold register
Analog Control Registers
Setting of Gain G of Current Channel PGA. Default is
01 (G = 25)
00
01
10
11
5
D[7:6]
25
40
100
PGA_CTL_REG
(PGA Control Registers)
13
0101_0000
R/W
Setting of Gain G in Voltage channel. Default is 01 (G =
25)
00
01
10
11
5
D[5:4]
D[3:0]
25
40
100
Reserved
0
1
0
1
Disable Chopper clock to Current channel
Enable Chopper clock to Current channel
Disable Chopper clock to Voltage channel
Enable Chopper clock to Voltage channel
Reserved
D[7]
D[6]
D[5]
D[4]
Reserved
PD_CTL_REG_1
(Power Down Control Register)
14
1100_1111
R/W
0
1
0
1
0
1
0
1
Disable Current channel PGA
D[3]
D[2]
D[1]
D[0]
Enable Current channel PGA
Disable Current channel ΣΔ Modulator
Enable Current channel ΣΔ Modulator
Disable Voltage channel PGA
Enable Voltage channel PGA
Disable Voltage channel ΣΔ Modulator
Enable Voltage channel ΣΔ Modulator
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AS8510
Datasheet - Detailed Description
Table 33. Control Registers
Addr in
HEX
Register Name
POR Value
R/W
8-bit Control / Status Data
Disable CIC1 of both channels
0
1
0
1
0
1
0
1
D[7]
D[6]
D[5]
D[4]
Enable CIC1 of both channels
Disable CIC2 of both channels
Enable CIC2 of both channels
Disable Dechopper in both channels
Enable Dechopper in both channels
Disable FIR in both channels
Enable FIR in both channels
PD_CTL_REG_2
(Power Down Control Register)
Do not bypass PGA in Current Channel
Default 0
15
1111_0011
R/W
0
1
0
D[3]
D[2]
Bypass PGA in Current Channel
Do not bypass PGA in Voltage Channel
Default 0
1
0
1
0
1
0
1
0
1
0
1
Bypass PGA in Voltage Channel
Disable Current Channel Chopper
Enable Current Channel Chopper
Disable Voltage Channel Chopper
Enable Voltage Channel Chopper
Disable Common Mode Reference
Enable Common Mode Reference
Disable Internal Current Source
D[1]
D[0]
D[7]
D[6]
D[5]
Enable Internal Current Source
Disable Internal temperature sensor
Enable Internal temperature sensor
Reserved. (Default 1) Do not change
Reserved. (Default 1) Do not change
Data Output in binary numbering system
PD_CTL_REG_3
(Power Down Control Register)
16
1111_1000
D[4]
D[3]
0
1
D[2]
Data Output in 2’s complement numbering
system
D[1]
D[0]
Reserved. (Default 0) Do not change
Reserved
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AS8510
Datasheet - Detailed Description
Table 33. Control Registers
Addr in
HEX
Register Name
POR Value
R/W
8-bit Control / Status Data
These bits specify the selection of voltage/temperature
in Voltage Channel
Default is 00 (Voltage Channel)
00
01
10
11
Voltage Channel
External Temperature Channel ETR
External Temperature Channel ETS
Internal Temperature Channel
D[7:6]
D[5]
D[4]
Reserved. (Default 0) Do not change
Internal current source switch enable. Default is 0
Note: D4 bit is used for Enabling current source to
the channel selected by bits D[7,6] of this
register.
ACH_CTL_REG
(Analog Channel Selection
Register)
17
0000_0000
R/W
0
1
Disabled
Enabled
Enable/disable Internal current source to RSHH pin of
Current channel
D[3]
0
1
Disabled
Enabled
Enable/disable current source switch to RSHL pin of
Current channel
D[2]
0
1
Disabled
Enabled
D[1:0]
Reserved
These three bits specify the selection of magnitude of
current from the Internal current source. Default is
00000 (0µA).
00000
00001
00010
00100
01000
10000
11111
0µA
8.5µA
17µA
D[7:3]
ISC_CTL_REG
(Current Source Setting Register)
18
0000_0000
R/W
34.5µA
68µA
135µA
270µA
D[2:0]
D[7]
Reserved
1
Reserved (default = 1) Do not change
Reserved
19
44
OTP_EN_REG
0000_0000
0000_0000
R/W
R
D[6:0]
D[7]
Status indicating data saturation in Current channel
Status indicating data saturation in Voltage channel
Reserved
STATUS_REG_2
D[6]
D[5:0]
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AS8510
Datasheet - Detailed Description
Table 33. Control Registers
Addr in
HEX
Register Name
POR Value
R/W
8-bit Control / Status Data
Digital Signal path control registers for Voltage Channel
Selection of Decimation ratio for Voltage/Temperature
channel.
Default is 0 (Down Sampling Rate is 64)
D[7]
0
1
Down Sampling Rate is 64
Down Sampling Rate is 128
Division of oversampling clock, which is used as
Chopper Clock. Default is 10 (divide by 512)
00
01
10
11
Chopper Clock Always High
Divide by 256
D[6:5]
Divide by 512
Divide by 1024
Decimation ratio of CIC2. Default is 0010 (4)
0000
1
2
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
4
8
45
DEC_REG_R1_V
0100_ 0101 R/W
16
32
64
D[4:1]
128
256
512
1024
2048
4096
8192
16384
32768
CIC1 Saturation Interrupt Mask Control.
Default is 1
D[0]
0
1
Unmasked
Masked
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AS8510
Datasheet - Detailed Description
Table 33. Control Registers
Addr in
HEX
Register Name
POR Value
R/W
8-bit Control / Status Data
D[7:5]
D[4]
Reserved
Interrupt Mask Control for Voltage channel data Ready
Interrupt on INT pin (Default is 0)
0
1
Unmasked
Masked
These two bits select the source of output 16-bit data in
Normal mode from Voltage channel. Default is 01
46
DEC_REG_R2_V
R/W
0000_0100
00
01
10
11
FIR / MA Output
CIC2 Output
D[3:2]
Dechop/Demod Output
CIC Output
D[1:0]
D[7]
Reserved
This bit selects FIR / MA Filter in Voltage channel.
Default is 0 (FIR)
0
1
FIR
MA Filter
These bits select the number of data samples for
averaging in MA filter in Voltage channel.
Default is 0000 (bypass)
47
FIR CTL_REG_V
0000_0000
R/W
0000
0001
0011
0111
1111
bypass
D[6:3]
D[2:0]
1
3
7
15
Reserved
Note: All the registers from address 0x19 to 0x2C are read-only.
7.9.1 Standby Mode - Power Consumption
In Standby Mode 1 there is a timer based accurate measurement every Ta seconds. The device itself stays in idle-mode as long as it does not
get a different command from the SPI interface. Internal oscillator frequency is typically foscint=262 kHz to reduce power consumption as long as
the timer runs. After every time out of Ta secs, it performs accurate measurement of current, voltage/ temperature. Data ready is signaled to
microcontroller through an interrupt signal on INT and goes into STOP state.
In the SBM the following equations hold:
Tsbm1 = Ta= 10s (default value is 10secs); the power consumption is valid for this setting. This is the period of the repetition rate in SBM 1
and SBM2.
Tsett ≈ 2ms (depending on external capacitors). This is the time required by the analog part to settle when the new measuring period is
started. Any measurements performed during Tsett produce invalid results.
T1 = 3ms (by default setting, every third measurement is sent to microcontroller in the SBM mode 1) is the time needed to perform the first
measurement.
Tmeas =Tsett +T1 is the total active time needed to get a valid result.
DRSBM = Tmeas/Tsbm ≈ 5ms/10s. This is the ratio of repetition time versus the active time (Device in NOM mode).
Power consumption = (DRSBM*NOM mode power consumption) + ((10s-5ms)/10s)*Stop mode power consumption)
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AS8510
Datasheet - Detailed Description
7.9.2 Initialization Sequence at Power ON
Figure 16. AS8510 Device Initialization Sequence at Power ON
VPORHID/VPORHIA
DVDD/AVDD
POR_N
INT
Start
ADC
1.5mS
TADC
D2
500µS
D3
D4
D3
D4
D3
D4
D1
D1
D2
D1
D2
Configure
Device
CHOP_CLK
Channel Data
Register
0x0000
DATA1
DATA2
TDATA_INVALID
TDATA_STATUS_RD
TDATA_VALID
Device initialization starts if the DVDD and AVDD supplies are switched ON and DVDD > VPORHID. The duration period of Initialization is 500μsec
and during this period, INT pin toggles at the rate of internal low power oscillator. Toggling on INT during the period of initialization should be
ignored in the system. Device configuration and activation should be carried out only after the initialization period.
On ADC start, device enters into analog stabilization state and takes 1.5msec for oscillator and Reference to settle. After this 1.5msec period, the
first interrupt will occur after a time period of TADC
.
TDATA_STATUS_RD is the time period during which the micro-controller should complete reading of data and status from the device. If reading is
carried out beyond this time period, then, ADC performance will degrade for next sample generation. Status register gets cleared automatically
only when micro-controller reads this register. Data in the channel registers is changed after TDATA_VALID duration. Ensure that data channel
registers and status registers are not read during the TDATA_INVALID duration.
Example:
Configuration registers are set as follows:
CLK_REG = 8’b0010_0000
DEC_REG_R1_I = 0100_0101
DEC_REG_R2_I = 1100_0101
FIR_CTL_REG_I = 0000_0100
ADC is configured to a data rate of 1KHz, CHOP_CLK to 2KHz, and Modulator clock to 1MHz, Decimation ratio of CIC1 = 64, and Decimation
ratio of CIC2 = 4. With these settings the various time periods as shown in the Figure 16 are as follows:
TDATA_STATUS_RD = 100 μsec
(TDATA_STATUS_RD = (1/mod_clk) * R1 * [((mod_clk/(2*chop_clk))*(1/R1)) - 2.5)
TDATA_INVALID = 8 μsec
TADC = 1msec
TDATA_VALID = TADC - TDATA_INVALID = 1msec - 8 μsec
CHOP_CLK and POR_N are internal signals of the device.
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AS8510
Datasheet - Detailed Description
Table 34 provides valid combinations of Modulator clock, Chopper clock and Decimation R1 and the corresponding values of TDATA_STATUS_RD and
TADC
.
Table 34. Valid Combinations of Modulator Clock, Chopper Clock and Decimation Ratio R1
TADC
Chopper Frequency
TDATA_STATUS_RD
Modulator Clock
Decimation Ratio R1
R2/(2*CHOP_CLK)
for R2=4
CHOP_CLK
1.024MHz
2.048MHz
2KHz
64
64
1usec * 64 * [4 - 2.5] = 96usec
1mSec
1mSec
0.5usec * 64 * [8 - 2.5] = 176usec
2KHz
0.5usec * 128 * [4 - 2.5] = 96usec
0.5usec * 64 * [4 - 2.5] = 48usec
2.048MHz
2.048MHz
2KHz
4KHz
128
64
1mSec
0.5mSec
7.9.3 Soft-reset of Device Using Bit D[7] of Reset Register 0x09
It is possible to soft-reset the device by writing “0” into D[7] bit of Reset Register at 0x09. On applying soft-reset, the device enters into
initialization state and D[6] bit changes back to “1”. The duration period of Initialization is 500μsec, and, during this period, INT pin toggles at the
rate of internal low power oscillator. Toggling on INT during the period of initialization should be ignored in the system. Device configuration and
activation should be carried out only after the initialization period. See Figure 17 for the timing details of the sequence of device initialization on
soft-reset.
Figure 17. AS8510 Device Initialization Sequence at Soft-reset
Start
ADC
1.5mS
INT
500µS
D4
D3
D4
D
3
D4
D3
D4
D3
D4
D1
D2
D1 Soft Reset
D1
D2
D1
D2
D1
D2
Re-Configure
Device
Using D7
CHOP_CLK
Channel Data
Register
0x0000
DATA-N
DATA-N+1
TDATA_INVALID
DATA1
DATA2
TDATA_STATUS_RD
TDATA_STATUS_RD
TDATA_VALID
TDATA_INVALID
TDATA_VALID
7.9.4 Soft-reset of the Measurement Path Using Bit D[7] of Reset Register 0x09
Measurement path also can be reset by using D[6] bit of Reset Register at 0x09. On applying soft-reset only signal measurement path registers
will be reset. For applying this reset, device should be in STOP state. If the device is working with external clock, at the time of soft-reset the
clock needs to be disabled.
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Datasheet - Detailed Description
7.9.5 Reconfiguring Gain Setting of PGA
Only PGA gain settings can be changed dynamically while ADC conversions are in progress. When PGA gain settings are changed, the first
sample from the ADC is invalid. Ignore the first interrupt after the gain re-configuration. Valid data starts from the second interrupt onwards.
Figure 18. AS8510 - Re-configuration of Gain Setting of PGA
Gain Re-Configuration can be
carried out in this slot, skip next
interrupt and Channel Data.
Read Channel
data in this slot
VALID
DATA
TDATA_STATUS_RD
INT
D3
D4
D4
D3
D4
D3
D4
D3
D4
D1
D2
D1
D2
D1
D2
D1
D2
CHOP_CLK
Channel Data
Register
DATA-N
DATA-N+1
DATA1
TDATA_STATUS_RD
DATA2
TDATA_STATUS_RD
TDATA_INVALID
TDATA_INVALID
TDATA_VALID
TDATA_VALID
7.9.6 Configuring the Device During Normal Mode
Following registers can be programmed dynamically when the device is in operational mode (Normal mode).
ACH_CTL_REG address is 0x17 for channel selection on the voltage measurement path
PGA_CTL_REG address is 0x13 for gain setting
PD_CTL_REG2 address is 0x15 for PGA Bypass
ISC_CTL_REG address is 0x18 for current source programmability
During the operation (Normal mode) of the device, if any of the registers need to be programmed or changed other than the above mentioned
registers, then it is required to STOP the device by writing into MOD_CTL_REG “STOP” bit and configure the device as per the requirements and
start the device.
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AS8510
Datasheet - Detailed Description
7.10 Low Side Current Measurement Application
Figure 19. Application Diagram
RSHH
RSHL
INT
CLK
REF
SDI
100nF
VCM
MEN
AS8510
100nF
3.3V
1µF
CHOP_CLK
AVDD
20 pin
(SSOP20)
3.3V
AVSS
ETR
DVDD
DVSS
SDO
SCLK
CS
1µF
+12V
481 R
R
ETS
VBAT_IN
VBAT_GND
100 µohm
+
-
Load
µC
12V
Battery
Note: On ETR connect constant resistor (temp co = 0)
On ETS connect Temperature sensor (use sensor resistor more than 10K)
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AS8510
Datasheet - Package Drawings and Markings
8 Package Drawings and Markings
The product is available in a 20-pin SSOP package.
Figure 20. Drawings and Dimensions
Symbol Min
Nom
Max
2.00
-
A
A1
A2
b
-
-
0.05
1.65
0.22
0.09
6.90
7.40
5.00
-
-
1.75
1.85
0.38
0.25
7.50
8.20
5.60
-
-
-
c
D
7.20
7.80
5.30
0.65 BSC
0.75
1.25 REF
0.25 BSC
-
E
E1
e
L
0.55
-
0.95
-
L1
L2
R
YYWWIXX
AS8510
-
-
0.09
0º
-
θ
4º
8º
N
20
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Revision 3.5
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AS8510
Datasheet - Package Drawings and Markings
Notes:
1. Dimensions & tolerancing conform to ASME Y14.5M-1994.
2. All dimensions are in millimeters. Angles are in degrees.
Marking: YYWWIXX.
YY
WW
I
XX
Last two digits of the current year
Manufacturing week
Assembly plant identifier
Assembly traceability code
8.1 Recommended PCB Footprint
Figure 21. PCB Footprint
Recommended Footprint Data
Symbol
mm
9.02
6.16
0.46
0.65
6.31
A
B
C
D
E
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Revision 3.5
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AS8510
Datasheet - Revision History
Revision History
Revision
Date
Owner
mbr
Description
Initial version
1.1
Jun 22, 2009
Dec 02, 2009
Updated the datasheet according to 1.8 specification
ss2, rad
Following modifications carried out in Table 27:
1) Deleted Max value for parameter ‘Temperature upper limit’
2) Added Footnote 2
3) Added new parameter ‘Temperature Sensor Output (without gain
calibration)
1.2
Dec 08, 2009
Feb 19, 2010
ss2
Updated Table 15 with PGA information
Updated Voltage Measurement
1.3
2.0
mbr
Updated VREFand VIN values in Table 17 and VREF in Table 18
Inserted new Table 28 - System Measurement Error Budget
Changed the pin name AGND to VCM
Current source added in the block diagram
Added application diagram
June 01, 2010
mbr
Updated Electrical Characteristics on page 7
Updated Detailed System and Block Specifications on page 9
Updated Standby Mode - Power Consumption on page 37
Updates carried out across the datasheet
3.0
3.1
3.2
Oct 29, 2010
Nov 02, 2010
Nov 14, 2010
Nov 26, 2010
Dec 03, 2010
ss2
ss2
ss2
vel
Updated Ref Voltage Offset in Table 18
Added sections 7.9.2, 7.9.3, 7.9.5
Formatted figures 17, 18 in portrait mode. Index modified from page 39
Added Configuring the Device During Normal Mode on page 40
3.3
ss2
Updated General Description, Key Features, Applications, Pin Descriptions,
Current Measurement Ranges, Differential Input Amplifier for Current
Channel, Differential Input Amplifier for Voltage Channel, Sigma Delta Analog
to Digital Converter, Bandgap Reference Voltage, System Measurement Error
Budget for Gains 5 and 25, Package Drawings and Markings. Deleted Voltage
Measurement.
3.4
Mar 01, 2011
mbr /ss2
Updated Table 14, Figure 4, Table 19, Table 18, Section 7.9.6, Figure 19.
Added Section 7.9.4
Aug 05, 2011
Dec 31, 2012
mbr,ss2,vel
sju
3.5
Updated ordering table.
Note: Typos may not be explicitly mentioned under revision history.
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Revision 3.5
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AS8510
Datasheet - Ordering Information
9 Ordering Information
The devices are available as the standard products shown in Table 35.
Table 35. Ordering Information
Ordering Code
AS8510-ASSP
AS8510-ASSM
Description
Delivery Form
Package
Data Acquisition Device for Battery Sensors
Data Acquisition Device for Battery Sensors
Tape and Reel (2000 pcs)
Tape and Reel (500 pcs)
20-pin SSOP
20-pin SSOP
Note: All products are RoHS compliant and ams green.
Buy our products or get free samples online at www.ams.com/ICdirect
Technical Support is available at www.ams.com/Technical-Support
For further information and requests, email us at sales@ams.com
(or) find your local distributor at www.ams.com/distributor
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Revision 3.5
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AS8510
Datasheet - Copyrights
Copyrights
Copyright © 1997-2012, ams AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights
reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the
copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. ams AG makes no
warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described
devices from patent infringement. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior
to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in normal
commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability
applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing
by ams AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard
production flow, such as test flow or test location.
The information furnished here by ams AG is believed to be correct and accurate. However, ams AG shall not be liable to recipient or any third
party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or
indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the
technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other
services.
Contact Information
Headquarters
ams AG
Tobelbaderstrasse 30
A-8141 Unterpremstaetten, Austria
Tel : +43 (0) 3136 500 0
Fax : +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit:
http://www.ams.com/contact
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Revision 3.5
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