MCF5328CVM240_技术文档

MCF5329DS

Rev. 0.1, 03/2006

Freescale Semiconductor

Data Sheet: Advance Information

MCF5329 ColdFire^®

Microprocessor Data Sheet

Supports MCF5327, MCF5328, & MCF5329

by: Microcontroller Division

Table of Contents

The MCF532x devices are a family of highly-integrated

32-bit microprocessors based on the Version 3 ColdFire

microarchitecture. All MCF532x devices contain a

32-Kbyte internal SRAM, an LCD controller, USB host

and On-the-Go controllers, a 2-bank SDR/DDR

SDRAM controller, a 16-channel DMA controller, up to

three UARTs, a queued SPI, as well as other peripherals

that enable the MCF532x family for use in general

purpose industrial control applications. Optional

peripherals include a Fast Ethernet controller, a CAN

module, and cryptography hardware accelerators.

1

2

3

4

5

6

MCF532x Family Configurations .........................2

Ordering Information ...........................................3

Signal Descriptions..............................................3

Mechanicals and Pinouts ..................................10

Preliminary Electrical Characteristics................15

Revision History ................................................46

This document provides an overview of the MCF532x

microprocessor family, focusing on its highly diverse

feature set. It was written from the perspective of the

MCF5329 device. However, it also pertains to the

MCF5327, and MCF5328. See the following section for

a summary of differences between the various devices of

the MCF532x family.

This document contains information on a new product. Specifications and information herein

are subject to change without notice.

• Preliminary

MCF532x Family Configurations

1 MCF532x Family Configurations

The following table compares the various device derivatives available within the MCF532x family.

Table 1. MCF532x Family Configurations

Module

MCF5327

MCF5328

MCF5329

ColdFire Version 3 Core with EMAC

(Enhanced Multiply-Accumulate Unit)

x

Core (System) Clock

up to 240 MHz

up to 80 MHz

Peripheral and External Bus Clock

(Core clock ÷ 3)

Performance (Dhrystone/2.1 MIPS)

Unified Cache

up to 211

16 Kbytes

Static RAM (SRAM)

32 Kbytes

LCD Controller

x

3

x

4

x

4

x

2

x

SDR/DDR SDRAM Controller

USB 2.0 Host

x

USB 2.0 On-the-Go

x

UTMI+ Low Pin Interface (ULPI)

Synchronous Serial Interface (SSI)

Fast Ethernet Controller (FEC)

Cryptography Hardware Accelerators

FlexCAN 2.0B communication module

UARTs

—

3

x

—

3

x

I²C

x

QSPI

x

PWM Module

x

Real Time Clock

x

32-bit DMA Timers

4

x

Watchdog Timer (WDT)

Periodic Interrupt Timers (PIT)

Edge Port Module (EPORT)

Interrupt Controllers (INTC)

16-channel Direct Memory Access (DMA)

FlexBus External Interface

General Purpose I/O Module (GPIO)

JTAG - IEEE^®1149.1 Test Access Port

Package

x

4

x

2

x

196

256

MAPBGA

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Preliminary

2

Freescale Semiconductor

Ordering Information

2 Ordering Information

Table 2. Orderable Part Numbers

Freescale Part

Number

Description

Speed

Temperature

MCF5327CVM240

MCF5328CVM240

MCF5329CVM240

MCF5327 RISC Microprocessor, 196 MAPBGA

MCF5328 RISC Microprocessor, 256 MAPBGA

MCF5329 RISC Microprocessor, 256 MAPBGA

240 MHz

–40° to +85° C

3 Signal Descriptions

The following table lists all the MCF532x pins grouped by function. The “Dir” column is the direction for

the primary function of the pin only. Refer to Section 4, “Mechanicals and Pinouts,” for package diagrams.

For a more detailed discussion of the MCF532x signals, consult the MCF5329 Reference Manual

(MCF5329RM).

NOTE

In this table and throughout this document a single signal within a group is

designated without square brackets (i.e., A23), while designations for

multiple signals within a group use brackets (i.e., A[23:21]) and is meant to

include all signals within the two bracketed numbers when these numbers

are separated by a colon.

NOTE

The primary functionality of a pin is not necessarily its default functionality.

Pins that are muxed with GPIO will default to their GPIO functionality.

Table 3. MCF5327/8/9 Signal Information and Muxing

MCF5327

196

MCF5328

256

MCF5329

256

Signal Name

GPIO

Alternate 1

Alternate 2 Dir.¹

MAPBGA

Reset

RESET²

RSTOUT

—

I

M12

P14

N15

P14

N15

P14

O

Clock

EXTAL

XTAL²

—

I

L14

K14

M11

N11

P16

N16

P13

R13

P16

N16

P13

R13

O

I

EXTAL32K

XTAL32K

O

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Preliminary

Freescale Semiconductor

3

Signal Descriptions

Table 3. MCF5327/8/9 Signal Information and Muxing (continued)

MCF5327

196

MCF5328

MCF5329

256

Signal Name

GPIO

Alternate 1

Alternate 2 Dir.¹

256

MAPBGA

FB_CLK

—

O

L1

T2

Mode Selection

RCON²

—

I

N7

M8

DRAMSEL

G10

H12

FlexBus

A[23:22]

A[21:16]

—

FB_CS[5:4]

—

O

B11,C11

C13, D13

B12, A12,

D11, C12,

B13, A13

E13, A14,

B14, C14,

A15, B15

E13, A14,

B14, C14,

A15, B15

A[15:14]

A[13:11]

—

SD_BA[1:0]

—

O

A14, B14

D14, B16

SD_A[13:11]

—

C13, C14,

D12

C15, C16,

D15

C15, C16,

D15

A10

—

O

D13

D16

A[9:0]

SD_A[9:0]

D14,

E11–14,

F11–F14,

G14

E14–E16,

F13–F16,

G16– G14

E14–E16,

F13–F16,

G16– G14

D[31:16]

D[15:1]

—

SD_D[31:16]³

FB_D[31:17]³

—

O

H3–H1,

M1–M4,

J4–J1, K1, N1–N4, T3, N1–N4, T3,

L4, M2, M3, P4, R4, T4, P4, R4, T4,

N1, N2, P1, N5, P5, R5, N5, P5, R5,

P2, N3

T5

F4–F1,

J3–J1,

G4–G2, L5, K4–K1, L2, K4–K1, L2,

N4, P4, M5, R6, N7, P7, R6, N7, P7,

N5, P5, M6 R7, T7, P8, R7, T7, P8,

R8

D0²

—

FB_D[16]³

—

O

N6

T8

BE/BWE[3:0]

PBE[3:0]

SD_DQM[3:0]

H4, P3, G1, L4, P6, L3, L4, P6, L3,

M4

N6

OE

TA²

R/W

TS

PBUSCTL3

PBUSCTL2

PBUSCTL1

PBUSCTL0

—

O

I

L7

R9

G13

P6

G13

N8

G13

N8

—

O

DACK0

D2

H4

Chip Selects

FB_CS[5:4]

FB_CS[3:1]

PCS[5:4]

PCS[3:1]

—

O

—

B13, A13

A11, D10,

C10

A12, B12,

C12

A12, B12,

C12

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Preliminary

4

Freescale Semiconductor

Signal Descriptions

Table 3. MCF5327/8/9 Signal Information and Muxing (continued)

MCF5327

196

MCF5328

MCF5329

256

Signal Name

GPIO

Alternate 1

Alternate 2 Dir.¹

256

MAPBGA

FB_CS0

—

O

B10

D12

SDRAM Controller

SD_A10

SD_CKE

—

O

L2

E1

K3

K2

—

P2

H2

R1

R2

J4

P2

H2

R1

R2

J4

SD_CLK

SD_CS1

SD_CS0

E2

H5

L6

L3

M1

K4

D1

H1

L1

H1

L1

SD_DQS3

SD_DQS2

SD_SCAS

SD_SRAS

SD_SDR_DQS

SD_WE

T6

P3

R3

P1

H3

T6

P3

R3

P1

H3

External Interrupts Port⁴

IRQ7²

IRQ6²

PIRQ7²

PIRQ6²

—

I

H14

—

J13

J14

J13

J14

USBHOST_

VBUS_EN²

IRQ5²

PIRQ5²

USBHOST_

VBUS_OC²

—

I

—

J15

IRQ4²

IRQ3²

IRQ2²

IRQ1²

PIRQ4²

PIRQ3²

PIRQ2²

PIRQ1²

SSI_MCLK²

—

I

H13

H12

J14

J13

J16

K14

K15

K16

J16

K14

K15

K16

—

USB_CLKIN²

DREQ1²

—

SSI_CLKIN²

FEC

FEC_MDC

FEC_MDIO

FEC_TXCLK

FEC_TXEN

FEC_TXD0

FEC_COL

PFECI2C3

PFECI2C2

PFECH7

PFECH6

PFECH5

PFECH4

PFECH3

PFECH2

I2C_SCL²

I2C_SDA²

—

O

I/O

I

—

C1

C2

A2

B2

E4

A8

C8

D8

C1

C2

A2

B2

E4

A8

C8

D8

—

O

I

ULPI_DATA0

ULPI_CLK

ULPI_NXT

ULPI_STP

FEC_RXCLK

FEC_RXDV

I

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Preliminary

Freescale Semiconductor

5

Signal Descriptions

Signal Name

Table 3. MCF5327/8/9 Signal Information and Muxing (continued)

MCF5327

196

MCF5328

MCF5329

256

GPIO

Alternate 1

Alternate 2 Dir.¹

256

MAPBGA

FEC_RXD0

FEC_CRS

PFECH1

PFECH0

ULPI_DATA4

ULPI_DIR

—

I

—

C6

B8

C6

B8

FEC_TXD[3:1]

FEC_TXER

FEC_RXD[3:1]

FEC_RXER

PFECL[7:5] ULPI_DATA[3:1]

PFECL4

PFECL[3:1] ULPI_DATA[7:5]

O

I

D3–D1

B1

D3–D1

B1

—

E7, A6, B6 E7, A6, B6

PFECL0

—

I

D4

LCD Controller

LCD_D17

LCD_D16

LCD_D17

LCD_D16

LCD_D15

LCD_D14

LCD_D13

LCD_D12

LCD_D[11:8]

PLCDDH1

PLCDDH0

PLCDDH1

PLCDDH0

PLCDDM7

PLCDDM6

PLCDDM5

PLCDDM4

CANTX

CANRX

—

O

—

C9

D9

—

A6

B6

C6

D6

A5

B5

C9

D9

A7

B7

C7

D7

—

FEC_COL

FEC_CRS

A7

B7

C7

D7

FEC_RXCLK

FEC_RXDV

—

PLCDDM[3:0] FEC_RXD[3:0]

C5, D5, A4, D6, E6, A5, D6, E6, A5,

B4

C4

B3

A3

A2

B5

C5

D5

A4

A3

B5

C5

D5

A4

A3

LCD_D7

LCD_D6

PLCDDL7

PLCDDL6

PLCDDL5

PLCDDL4

FEC_RXER

FEC_TXCLK

FEC_TXEN

FEC_TXER

—

O

LCD_D5

LCD_D4

LCD_D[3:0]

PLCDDL[3:0] FEC_TXD[3:0]

D4, C3, D3, B4, C4, B3, B4, C4, B3,

B2

C3

LCD_ACD/

LCD_OE

PLCDCTLH0

—

O

D7

B9

LCD_CLS

PLCDCTLL7

—

O

C7

B7

A7

A9

LCD_CONTRAST PLCDCTLL6

D10

C10

D10

C10

LCD_FLM/

PLCDCTLL5

LCD_VSYNC

LCD_LP/

PLCDCTLL4

—

O

A8

B10

LCD_HSYNC

LCD_LSCLK

LCD_PS

PLCDCTLL3

PLCDCTLL2

PLCDCTLL1

—

O

B8

C8

D8

B9

A10

A11

B11

C11

A10

A11

B11

C11

LCD_REV

LCD_SPL_SPR PLCDCTLL0

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Preliminary

6

Freescale Semiconductor

Signal Descriptions

Table 3. MCF5327/8/9 Signal Information and Muxing (continued)

MCF5327

196

MCF5328

MCF5329

256

Signal Name

GPIO

Alternate 1

Alternate 2 Dir.¹

256

MAPBGA

USB Host & USB On-the-Go

USBOTG_M

USBOTG_P

USBHOST_M

USBHOST_P

—

I/O

J12

K13

L12

M13

L15

L16

L15

L16

M15

M16

M15

M16

FlexCAN (MCF5329 only)

CANRX and CANTX do not have dedicated bond pads. Please refer to the following pins for muxing:

I2C_SDA, SSI_RXD, or LCD_D16 for CANRX and I2C_SCL, SSI_TXD, or LCD_D17 for CANTX.

PWM

PWM7

PWM5

PWM3

PWM1

PPWM7

PPWM5

PPWM3

PPWM1

—

I/O

—

H13

H14

H15

H16

H13

H14

H15

H16

—

DT3OUT

DT2OUT

DT3IN

DT2IN

G12

G11

SSI

SSI_MCLK

SSI_BCLK

SSI_FS

PSSI4

PSSI3

PSSI2

PSSI1

PSSI0

PSSI1

PSSI0

—

PWM7

PWM5

CANRX

CANTX

—

I/O

I

—

G4

F4

G3

—

G4

F4

G3

G2

G1

—

U2CTS

U2RTS

U2RXD

U2TXD

U2RXD

U2TXD

SSI_RXD²

SSI_TXD²

SSI_RXD²

SSI_TXD²

O

—

I

G2

G1

—

O

—

I²C

I2C_SCL²

I2C_SDA²

I2C_SCL²

I2C_SDA²

PFECI2C1

PFECI2C0

PFECI2C1

PFECI2C0

CANTX

CANRX

—

U2TXD

U2RXD

U2TXD

U2RXD

I/O

—

F3

F2

—

E3

E4

F3

F2

—

DMA

DACK[1:0] and DREQ[1:0] do not have dedicated bond pads. Please refer to the following pins for muxing:

TS for DACK0, DT0IN for DREQ0, DT1IN for DACK1, and IRQ1 for DREQ1.

QSPI

QSPI_CS2

QSPI_CS1

PQSPI5

PQSPI4

U2RTS

PWM7

—

O

P10

L11

T12

T13

T12

T13

USBOTG_

PU_EN

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Preliminary

Freescale Semiconductor

7

Signal Descriptions

Signal Name

Table 3. MCF5327/8/9 Signal Information and Muxing (continued)

MCF5327

196

MCF5328

MCF5329

256

GPIO

Alternate 1

Alternate 2 Dir.¹

256

MAPBGA

QSPI_CS0

QSPI_CLK

QSPI_DIN

PQSPI3

PQSPI2

PQSPI1

PQSPI0

PWM5

I2C_SCL²

U2CTS

—

O

I

—

P11

R12

N12

P12

P11

R12

N12

P12

N10

L10

M10

QSPI_DOUT

I2C_SDA

O

UARTs

U1CTS

U1RTS

U1TXD

U1RXD

U0CTS

U0RTS

U0TXD

U0RXD

PUARTL7

PUARTL6

PUARTL5

PUARTL4

PUARTL3

PUARTL2

PUARTL1

PUARTL0

SSI_BCLK

SSI_FS

SSI_TXD²

SSI_RXD²

—

I

O

I

C9

D9

D11

E10

E11

E12

R15

T15

T14

R14

D11

E10

E11

E12

R15

T15

T14

R14

A9

A10

P13

N12

P12

P11

I

—

O

I

—

Note: The UART2 signals are multiplexed on the QSPI, SSI, DMA Timers, and I2C pins.

DMA Timers

DT3IN

DT2IN

DT1IN

DT0IN

PTIMER3

PTIMER2

PTIMER1

PTIMER0

DT3OUT

DT2OUT

DT1OUT

DT0OUT

U2RXD

U2TXD

DACK1

DREQ0²

I

C1

B1

A1

C2

F1

E1

E2

E3

F1

E1

E2

E3

BDM/JTAG⁵

JTAG_EN⁶

DSCLK

PSTCLK

BKPT

—

I

J11

N14

M7

M13

P15

T9

M13

P15

T9

TRST²

TCLK²

TMS²

TDI²

TDO

—

O

I

N13

M14

P9

R16

N14

N11

R16

N14

N11

DSI

I

DSO

O

DDATA[3:0]

P7, L8, M8, N9, P9, N10, N9, P9, N10,

N8

P10

PST[3:0]

—

O

P8, L9, M9, R10, T10,

R10, T10,

R11, T11

N9 R11, T11

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Preliminary

8

Freescale Semiconductor

Signal Descriptions

Table 3. MCF5327/8/9 Signal Information and Muxing (continued)

MCF5327

196

MCF5328

MCF5329

256

Signal Name

GPIO

Alternate 1

Alternate 2 Dir.¹

256

MAPBGA

Test

TEST⁶

—

I

E10

—

A16

N13

A16

N13

PLL_TEST⁷

Power Supplies

EVDD

—

E6, E7,

E8, F5–F8, E8, F5–F8,

F5–F7, H9, G5, G6, H5, G5, G6, H5,

J8, J9, K8,

K9

H6, J11,

K11, K12,

H6, J11,

K11, K12,

L9–L11, M9, L9–L11, M9,

M10 M10

IVDD

—

E5, K5, K10 E5,G12,M5, E5, G12,M5,

M11, M12

PLL_VDD

SD_VDD

—

H10

J12

E8, E9,

E9, F9–F11, E9, F9–F11,

F8–F10, J6, G11, H11,

G11, H11,

J5, J6, K5,

K6, J7, K7

J5, J6, K5,

K6, L5–L8, K6, L5–L8,

M6, M7

USBOTG_VDD

VSS

—

K12

L14

G6–G9,

H6–H8, P9

G7–G10,

H7–H10,

J7–10,

G7–G10,

H7–H10,

J7–10,

K7–K10,

L12, L13

K7–K10,

L12, L13

PLL_VSS

—

H11

L13

K13

M14

K13

M14

USBHOST_VSS

NOTES:

1

Refers to pin’s primary function.

Pull-up enabled internally on this signal for this mode.

2

3

Primary functionality selected by asserting the DRAMSEL signal (SDR mode). Alternate functionality selected by

negating the DRAMSEL signal (DDR mode). The GPIO module is not responsible for assigning these pins.

GPIO functionality is determined by the edge port module. The GPIO module is only responsible for assigning the

alternate functions.

If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not

responsible for assigning these pins.

4

5

6

7

Pull-down enabled internally on this signal for this mode.

Must be left floating for proper operation of the PLL.

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Freescale Semiconductor

9

Preliminary

Mechanicals and Pinouts

4 Mechanicals and Pinouts

This section contains drawings showing the pinout and the packaging and mechanical characteristics of

the MCF532x devices.

NOTE

The mechanical drawings are the latest revisions at the time of publication

of this document. The most up-to-date mechanical drawings can be found at

the product summary page located at http://www.freescale.com/coldfire.

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

10

Freescale Semiconductor

Preliminary

Mechanicals and Pinouts

4.1 Pinout—256 MAPBGA

Figure 1 shows a pinout of the MCF5328CVM240 and MCF5329CVM240 devices.

NOTE

The pin at location N13 (PLL_TEST) must be left floating, else improper

operation of the PLL module will occur.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

FEC_

TXCLK

LCD_

D4

LCD_

D5

LCD_

D9

FEC_

RXD2

LCD_

D15

FEC_

COL

LCD_

CLS

LCD_

LSCLK

LCD_

PS

A

B

C

D

E

F

NC

FB_CS3 FB_CS4

FB_CS2 FB_CS5

A20

A17

TEST

A

B

C

D

E

F

FEC_

TXER

FEC_

TXEN

LCD_

D1

LCD_

D3

LCD_

D8

FEC_

RXD1

LCD_

D14

FEC_

CRS

LCD_

ACD/OE HSYNC

LCD_LP/

LCD_

REV

A19

A18

A15

A9

A16

A13

A11

A8

A14

A12

A10

A7

FEC_

MDC

FEC_

MDIO

LCD_

D0

LCD_

D2

LCD_

D7

FEC_

RXD0

LCD_

D13

FEC_

RXCLK

LCD_ LCD_FLM/

D17

LCD_

SPL_SPR

FB_CS1

FB_CS0

U1RXD

NC

A23

A22

VSYNC

FEC_

TXD1

FEC_

TXD2

FEC_

TXD3

FEC_

RXER

LCD_

D6

LCD_

D11

LCD_

D12

FEC_

RXDV

LCD_ LCD_CON

D16 TRAST

U1CTS

U1TXD

FEC_

TXD0

LCD_

D10

FEC_

RXD3

DT2IN

DT3IN

DT1IN

DT0IN

IVDD

EVDD

EVDD SD_VDD U1RTS

A21

I2C_

SDA

I2C_

SCL

SSI_

BCLK

EVDD

VSS

EVDD SD_VDD SD_VDD SD_VDD

A6

A5

A4

A3

SSI_

TXD

SSI_

RXD

SSI_

MCLK

G

H

J

SSI_FS

VSS

SD_VDD

EVDD

IVDD

TA

A0

A1

A2

G

H

J

SD_

CS0

DRAM

SEL

SD_CKE SD_WE

TS

PWM7

IRQ7

PWM5

IRQ6

IRQ3

PWM3

IRQ5

PWM1

IRQ4

PLL_

VDD

D13

D9

D14

D10

D8

D15

D11

SD_CS1 SD_VDD SD_VDD

VSS

PLL_

VSS

K

L

D12

SD_VDD SD_VDD

VSS

EVDD

VSS

IRQ2

USB

IRQ1

USB

K

L

SD_

DQS3

BE/

BWE1

BE/

BWE3

USB_

VSS

USBOTG

_VDD

SD_VDD SD_VDD SD_VDD SD_VDD EVDD

EVDD

OTG_M OTG_P

JTAG_ USBHOST

EN

USB

M

N

P

R

T

D31

D27

D30

D26

D29

D25

D28

D24

D22

D21

IVDD SD_VDD SD_VDD RCON

BE/

EVDD

IVDD

M

N

P

R

T

_VSS

HOST_M HOST_P

TDO/

DSO

QSPI_

DIN

PLL_

TEST

D19

D18

D17

D6

D5

D4

R/W

DDATA3 DDATA1

DDATA2 DDATA0

TDI/DSI

RESET

XTAL

BWE0

SD_DR

_DQS

BE/

BWE2

QSPI_

CS0

QSPI_

DOUT

EXTAL

32K

TRST/

DSCLK

SD_A10 SD_CAS

D2

RSTOUT

U0RXD

EXTAL

QSPI_

CLK

XTAL

32K

TMS/

BKPT

SD_CLK SD_CLK SD_RAS

D7

D1

OE

PST3

PST1

U0CTS

SD_

DQS2

TCLK/

PSTCLK

QSPI_

CS2

QSPI_

CS1

NC

1

FB_CLK

2

D23

3

D20

4

D16

5

D3

7

D0

8

PST2

10

PST0

11

U0TXD

14

U0RTS

15

NC

16

6

9

12

13

Figure 1. MCF5328CVM240 and MCF5329CVM240 Pinout Top View (256 MAPBGA)

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Preliminary

Freescale Semiconductor

11

Mechanicals and Pinouts

4.2 Package Dimensions—256 MAPBGA

Figure 2 shows MCF5328CVM240 and MCF5329CVM240 package dimensions.

X

D

M

Laser mark for pin A1

identification in

this area

5

Y

0.30 Z

A2

K

A

A1

256X

4

0.15 Z

Z

E

Detail K

Rotated 90° Clockwise

Notes:

1.

2.

Dimensions are in millimeters.

Interpret dimensions and tolerances

per ASME Y14.5M, 1994.

Top View

M

0.20

15X e

3.

4.

5.

Dimension b is measured at the

maximum solder ball diameter, parallel

to datum plane Z.

Datum Z (seating plane) is defined by

the spherical crowns of the solder

balls.

Parallelism measurement shall exclude

any effect of mark on top surface of

package.

Metalized mark for

pin A1 identification

in this area

S

15 13 11

16 14 12 10

7 6 5 4 3 2 1

A

B

C

D

E

F

S

15X e

3

G

H

J

256X

b

M

0.25

0.10

Z X Y

Millimeters

K

L

M

N

P

R

T

Dim Min

1.25

A1 0.27

Max

1.60

0.47

Z

A

1.16 REF

A2

b

D

E

e

0.40

17.00 BSC

0.60

Bottom View

1.00 BSC

0.50 BSC

View M-M

S

Figure 2. 256 MAPBGA Package Outline

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Preliminary

12

Freescale Semiconductor

Mechanicals and Pinouts

4.3 Pinout—196 MAPBGA

The pinout for the MCF5327CVM240 package is shown below.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

LCD_

D4

LCD_

D5

LCD_

D9

LCD_

D13

LCD_ LCD_FLM/ LCD_LP/

D17 VSYNC HSYNC

A

B

C

D

E

F

DT1IN

U1TXD

U1RXD FB_CS3

A20

A16

A15

A

B

C

D

E

F

LCD_

D0

LCD_

D6

LCD_

D8

LCD_

D12

LCD_ LCD_CON LCD_

LCD_

D2TIN

DT3IN

FB_CS0

A23

A22

A19

A8

A21

A18

A17

A13

A10

A6

A14

A12

D16

TRAST

LSCLK SPL_SPR

LCD_

D2

LCD_

D7

LCD_

D11

LCD_

D15

LCD_

CLS

LCD_

PS

DT0IN

TS

U1CTS FB_CS1

U1RTS FB_CS2

LCD_

D1

LCD_

D3

LCD_

D10

LCD_

D14

LCD_

ACD/OE

LCD_

REV

SD_WE

A11

A9

SD_CKE SD_CS0 I2C_SCL I2C_SDA IVDD

EVDD

VSS

EVDD

VSS

SD_VDD SD_VDD

TEST

A7

A5

D12

D13

D8

D14

D9

D15

D10

EVDD

D11

SD_VDD SD_VDD SD_VDD

DRAM

A4

A3

A2

A1

BE/

BWE1

G

H

J

VSS

EVDD

PST1

PST0

PWM1

PWM3

IRQ3

TA

A0

G

H

J

SEL

BE/

BWE3

SD_

DQS3

PLL_

VDD

PLL_

VSS

D29

D25

D24

D30

D26

D31

D27

VSS

IRQ4

IRQ1

IRQ7

IRQ2

XTAL

EXTAL

TDI/DSI

JTAG_

EN

USB

OTG_M

D28

SD_VDD SD_VDD SD_VDD

SD_

EVDD

DDATA1

DDATA0

PST3

IVDD

SD_DR_

DQS

USBHOST

_VDD

USB

OTG_P

K

L

SD_CLK SD_CLK

IVDD

SD_VDD

EVDD

K

L

DQS2

TCLK/

PSTCLK

QSPI_

DIN

QSPI_

CS1

USB

HOST_M

USBHOST

_VSS

FB_CLK SD_A10 SD_CAS

D23

D7

D1

BE/

BWE0

QSPI_

DOUT

EXTAL

32K

USB

HOST_P

M

N

P

SD_RAS

D20

D22

D19

D21

D16

D4

D0

RCON

RESET

U0RTS

M

N

P

TDO/

DSO

QSPI_

CLK

XTAL

32K

TMS/

BKPT

TRST/

DSCLK

D6

D3

R/W

DDATA3

BE/

BWE2

QSPI_

CS2

D18

1

D17

2

D5

4

D2

5

OE

6

DDATA2

7

PST2

8

VSS

9

U0RXD

11

U0TXD

12

U0CTS RSTOUT

3

10

13

14

Figure 3. MCF5327CVM240 Pinout Top View (196 MAPBGA)

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Preliminary

Freescale Semiconductor

13

Mechanicals and Pinouts

4.4 Package Dimensions—196 MAPBGA

Figure 4 shows the MCF5327CVM240 package dimensions.

NOTES:

D

X

Y

1. Dimensions are in millimeters.

2. Interpretdimensionsandtolerances

per ASME Y14.5M, 1994.

Laser mark for pin 1

identification in

this area

3. Dimension B is measured at the

maximum solder ball diameter,

parallel to datum plane Z.

4. Datum Z (seating plane) is defined

bythesphericalcrownsofthesolder

balls.

M

K

5. Parallelism measurement shall

exclude any effect of mark on top

surface of package.

Millimeters

DIM Min Max

A 1.32 1.75

A1 0.27 0.47

A2 1.18 REF

E

b

D

E

e

0.35 0.65

15.00 BSC

1.00 BSC

0.50 BSC

S

M

Top View

0.20

13X e

S

Metalized mark for

pin 1 identification

in this area

14 13 12 11 10

9

6

5

4

3

2

1

A

B

C

D

E

F

5

S

0.30 Z

13X e

A2

A

G

H

J

A1

0.15 Z

4

Z

K

L

Detail K

Rotated 90 Clockwise

°

M

N

P

3

196X

b

Bottom View

0.30 Z X Y

0.10 Z

View M-M

Figure 4. 196 MAPBGA Package Dimensions (Case No. 1128A-01)

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Preliminary

14

Freescale Semiconductor

Preliminary Electrical Characteristics

5 Preliminary Electrical Characteristics

This document contains electrical specification tables and reference timing diagrams for the MCF5329

microcontroller unit. This section contains detailed information on power considerations, DC/AC

electrical characteristics, and AC timing specifications of MCF5329.

The electrical specifications are preliminary and are from previous designs or design simulations. These

specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however

for production silicon these specifications will be met. Finalized specifications will be published after

complete characterization and device qualifications have been completed.

NOTE

The parameters specified in this MCU document supersede any values

found in the module specifications.

5.1 Maximum Ratings

1, 2

Table 4. Absolute Maximum Ratings

Rating

Symbol

Value

Unit

Core Supply Voltage

IV_DD

EV_DD

SDV_DD

PLLV_DD

V_IN

– 0.5 to +2.0

– 0.3 to +4.0

– 0.3 to +2.0

– 0.3 to +3.6

25

V

CMOS Pad Supply Voltage

DDR/Memory Pad Supply Voltage

PLL Supply Voltage

V

Digital Input Voltage ³

V

Instantaneous Maximum Current

I_D

mA

Single pin limit (applies to all pins) ^{3, 4, 5}

Operating Temperature Range (Packaged)

T_A

(T_L- T_H)

– 40 to +85

°C

Storage Temperature Range

N₁OTES:

T_stg

– 55 to +150

Functional operating conditions are given in Section 5.4, “DC Electrical Specifications.”

Absolute maximum ratings are stress ratings only, and functional operation at the maxima is

not guaranteed. Continued operation at these levels may affect device reliability or cause

permanent damage to the device.

This device contains circuitry protecting against damage due to high static voltage or

electrical fields; however, it is advised that normal precautions be taken to avoid application of

any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of

operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g.,

either V_SSor EV_DD).

2

3

4

Input must be current limited to the value specified. To determine the value of the required

current-limiting resistor, calculate resistance values for positive and negative clamp voltages,

then use the larger of the two values.

All functional non-supply pins are internally clamped to V_SSand EV_DD

.

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Preliminary

Freescale Semiconductor

15

Preliminary Electrical Characteristics

5

Power supply must maintain regulation within operating EV_DDrange during instantaneous

and operating maximum current conditions. If positive injection current (V_in> EV_DD) is greater

than I_DD, the injection current may flow out of EV_DDand could result in external power supply

going out of regulation. Insure external EV_DDload will shunt current greater than maximum

injection current. This will be the greatest risk when the MCU is not consuming power (ex; no

clock). Power supply must maintain regulation within operating EV_DDrange during

instantaneous and operating maximum current conditions.

5.2 Thermal Characteristics

Table 5. Thermal Characteristics

Characteristic

Symbol

256MBGA 196MBGA Unit

Junction to ambient, natural convection

Four layer board

(2s2p)

θ_JMA

26^1,2

32^1,2

°C/W

Junction to ambient (@200 ft/min)

Four layer board

(2s2p)

θ_JMA

23^1,2

29^1,2

°C/W

Junction to board

θ_JB

θ_JC

Ψ_jt

T_j

15³

10⁴

2^1,5

105

20³

10⁴

2^1,5

105

°C/W

^oC

Junction to case

Junction to top of package

Maximum operating junction temperature

N₁OTES:

θ

_JMAand Ψ_jtparameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection.

Freescale recommends the use of θ_JmAand power dissipation specifications in the system design to prevent

device junction temperatures from exceeding the rated specification. System designers should be aware

that device junction temperatures can be significantly influenced by board layout and surrounding devices.

Conformance to the device junction temperature specification can be verified by physical measurement in

the customer’s system using the Ψ_jtparameter, the device power dissipation, and the method described in

EIA/JESD Standard 51-2.

2

3

Per JEDEC JESD51-6 with the board horizontal.

Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8.

Board temperature is measured on the top surface of the board near the package.

Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL

SPEC-883 Method 1012.1).

Thermal characterization parameter indicating the temperature difference between package top and the

junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal

characterization parameter is written in conformance with Psi-JT.

4

5

The average chip-junction temperature (T ) in °C can be obtained from:

J

T_J= T_A+ (P_D× Θ_JMA

)

Eqn. 1

Where:

T

= Ambient Temperature, °C

= Package Thermal Resistance, Junction-to-Ambient, °C/W

= P + P

A

Q

JMA

P

D

INT

I/O

P

= I × IV , Watts - Chip Internal Power

DD DD

INT

P

= Power Dissipation on Input and Output Pins — User Determined

I/O

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

16

Freescale Semiconductor

Preliminary

Preliminary Electrical Characteristics

For most applications P < P

and can be ignored. An approximate relationship between P and T (if

I/O

INT

D

J

P

is neglected) is:

I/O

K

--------------------------------

P_D

=

Eqn. 2

(T_J+ 273°C)

Solving equations 1 and 2 for K gives:

K = P_D× (T_A× 273°C) + Q_JMA× P²_D

Eqn. 3

where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring

P (at equilibrium) for a known T . Using this value of K, the values of P and T can be obtained by

D

A

D

J

solving Equation 1 and Equation 2 iteratively for any value of T .

A

5.3 ESD Protection

1, 2

Table 6. ESD Protection Characteristics

Characteristics

Symbol

Value

Units

ESD Target for Human Body Model

N₁OTES:

HBM

2000

V

All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for

Automotive Grade Integrated Circuits.

2

A device is defined as a failure if after exposure to ESD pulses the device no longer meets

the device specification requirements. Complete DC parametric and functional testing is

performed per applicable device specification at room temperature followed by hot

temperature, unless specified otherwise in the device specification.

5.4 DC Electrical Specifications

Table 7. DC Electrical Specifications

Characteristic

Symbol

Min

Max

Unit

Core Supply Voltage

PLL Supply Voltage

IV_DD

PLLV_DD

EV_DD

1.4

1.6

V

1.6

CMOS Pad Supply Voltage

3.0

3.6

1.95

Mobile DDR/Bus Pad Supply Voltage

DDR/Bus Pad Supply Voltage

SDR/Bus Pad Supply Voltage

USB Supply Voltage

SDV_DD

USBV_DD

EV_IH

1.65

2.25

3.0

2.75

3.6

3.0

3.6

CMOS Input High Voltage

2

EV_DD+ 0.05

0.8

CMOS Input Low Voltage

EV_IL

-0.05

TBD

-0.05

2

Mobile DDR/Bus Input High Voltage

Mobile DDR/Bus Input Low Voltage

DDR/Bus Input High Voltage

DDR/Bus Input Low Voltage

SDV_IH

SDV_IL

SDV_IH

SDV_IL

SDV_DD+ 0.05

TBD

SDV_DD+ 0.05

0.8

-0.05

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Preliminary

Freescale Semiconductor

17

Preliminary Electrical Characteristics

Table 7. DC Electrical Specifications (continued)

Characteristic

Symbol

Min

Max

Unit

Input Leakage Current

I_in

-1.0

1.0

µA

V_in= V_DDor V_SS, Input-only pins

CMOS Output High Voltage

EV_OH

EV_OL

EV_DD- 0.4

—

0.4

—

V

I_OH= –5.0 mA

CMOS Output Low Voltage

—

SDV_DD- 0.4

—

I_OL= 5.0 mA

DDR/Bus Output High Voltage

I_OH= –5.0 mA

SDV_OH

SDV_OL

DDR/Bus Output Low Voltage

0.4

-130

I_OL= 5.0 mA

Weak Internal Pull-Up Device Current, tested at V_ILMax.¹

I_APU

C_in

-10

µA

Input Capacitance ²

pF

All input-only pins

All input/output (three-state) pins

—

7

NOTES:

1

Refer to the signals section for pins having weak internal pull-up devices.

This parameter is characterized before qualification rather than 100% tested.

2

5.4.1 PLL Power Filtering

To further enhance noise isolation, an external filter is strongly recommended for PLL analog V pins.

DD

The filter shown in Figure 5 should be connected between the board V and the PLLV pins. The

DD

resistor and capacitors should be placed as close to the dedicated PLLV pin as possible.

DD

10 Ω

Board V_DD

PLL V_DDPin

10 µF

0.1 µF

GND

Figure 5. System PLL V Power Filter

DD

5.4.2 USB Power Filtering

To minimize noise, external filters are required for each of the USB power pins. The filter shown in

Figure 6 should be connected between the board EV or IV and each of the USBV pins. The

DD

resistor and capacitors should be placed as close to the dedicated USBV pin as possible.

DD

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

18

Freescale Semiconductor

Preliminary

Preliminary Electrical Characteristics

0 Ω

Board EV_DD/IV_DD

USB V_DDPin

10 µF

0.1 µF

GND

Figure 6. USB V Power Filter

DD

NOTE

In addition to the above filter circuitry, a 0.01 F capacitor is also

recommended in parallel with those shown.

5.4.3 Supply Voltage Sequencing and Separation Cautions

Figure 7 shows situations in sequencing the I/O V (EV ), SDRAM V (SDV ), PLL V

DD

(PLLV ), and Core V (IV ).

DD

EV_DD, SDV_DD, USBV_DD

SDV_DD(2.5V/1.8V)

3.3V

2.5V

Supplies Stable

IV_DD, PLLV_DD

1.5V

1

2

0

Time

Notes:

1. IVDD should not exceed EVDD, SDVDD or PLLVDD by more than

0.4 V at any time, including power-up.

2. Recommended that IVDD/PLLVDD should track EVDD/SDVDD up to

0.9 V, then separate for completion of ramps.

3. Input voltage must not be greater than the supply voltage (EVDD, SDVDD,

IVDD, or PLLVDD) by more than 0.5 V at any time, including during power-up.

4. Use 1 ms or slower rise time for all supplies.

Figure 7. Supply Voltage Sequencing and Separation Cautions

The relationship between SDV and EV is non-critical during power-up and power-down sequences.

DD

Both SDV (2.5V or 3.3V) and EV are specified relative to IV .

DD

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Preliminary

Freescale Semiconductor

19

Preliminary Electrical Characteristics

5.4.3.1 Power Up Sequence

If EV /SDV are powered up with IV at 0 V, then the sense circuits in the I/O pads will cause all

DD

pad output drivers connected to the EV /SDV to be in a high impedance state. There is no limit on

DD

how long after EV /SDV powers up before IV must powered up. IV should not lead the EV ,

DD

SDV or PLLV by more than 0.4 V during power ramp-up, or there will be high current in the internal

DD

ESD protection diodes. The rise times on the power supplies should be slower than 1 µs to avoid turning

on the internal ESD protection clamp diodes.

The recommended power up sequence is as follows:

1. Use 1 µs or slower rise time for all supplies.

2. IV /PLLV and EV /SDV should track up to 0.9 V, then separate for the completion of

DD

ramps with EV /SD V going to the higher external voltages. One way to accomplish this is to

DD

use a low drop-out voltage regulator.

5.4.3.2 Power Down Sequence

If IV /PLLV are powered down first, then sense circuits in the I/O pads will cause all output drivers

DD

to be in a high impedance state. There is no limit on how long after IV and PLLV power down before

DD

EV or SDV must power down. IV should not lag EV , SDV , or PLLV going low by more

DD

than 0.4 V during power down or there will be undesired high current in the ESD protection diodes. There

are no requirements for the fall times of the power supplies.

The recommended power down sequence is as follows:

1. Drop IV /PLLV to 0 V.

DD

2. Drop EV /SDV supplies.

DD

5.5 Power Consumption Specifications

Estimated maximum RUN mode power consumption measurements are shown in the below figure.

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

20

Freescale Semiconductor

Preliminary

Preliminary Electrical Characteristics

Estimated Power Consumption vs. Core Frequency

300

250

200

150

100

50

0

40

80

120

160

200

240

Core Frequency (MHz)

Figure 8. Estimated Maximum RUN Mode Power Consumption

Table 8 lists estimated maximum power and current consumption for the device in various operating

modes.

Table 8. Estimated Maximum Power Consumption Specifications

Characteristic

Symbol Typical

Max

Unit

Run Mode - Total Power Dissipation

—

250

5.74

244

mW

Static

Dynamic

Core Operating Supply Current ¹

Run Mode

I_DD

EI_DD

—

TBD

mA

Pad Operating Supply Current

Run Mode (application dependent)

Wait Mode

—

144

96

1

mA

Stop Mode

NOTES:

1

Current measured at maximum system clock frequency, all modules active, and default drive

strength with matching load.

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Freescale Semiconductor

21

Preliminary

Preliminary Electrical Characteristics

5.6 Oscillator and PLL Electrical Characteristics

Table 9. PLL Electrical Characteristics

Min.

Value

Max.

Value

Num

Characteristic

Symbol

Unit

1

PLL Reference Frequency Range

Crystal reference

f_{ref_crystal}

f_{ref_ext}

TBD

16

MHz

External reference

2

Core frequency

f_sys

f_sys/3

TBD

240

80

MHz

CLKOUT Frequency¹

3

4

Crystal Start-up Time^{2, 3}

t_cst

—

10

ms

EXTAL Input High Voltage

Crystal Mode⁴

All other modes (External, Limp)

V_IHEXT

TBD

V

5

EXTAL Input Low Voltage

Crystal Mode⁴

V_ILEXT

TBD

V

All other modes (External, Limp)

6

XTAL Load Capacitance²

PLL Lock Time ^{2, 5}

5

30

1

pF

ms

%

7

8

t_lpll

t_dc

—

40

Duty Cycle of reference ²

60

N₁OTES:

All internal registers retain data at 0 Hz.

2

3

4

5

This parameter is guaranteed by characterization before qualification rather than 100% tested.

Proper PC board layout procedures must be followed to achieve specifications.

This parameter is guaranteed by design rather than 100% tested.

This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in

the synthesizer control register (SYNCR).

5.7 External Interface Timing Characteristics

Table 10 lists processor bus input timings.

NOTE

All processor bus timings are synchronous; that is, input setup/hold and

output delay with respect to the rising edge of a reference clock. The

reference clock is the FB_CLK output.

All other timing relationships can be derived from these values. Timings

listed in Table 10 are shown in Figure 10 and Figure 11.

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

22

Freescale Semiconductor

Preliminary

Preliminary Electrical Characteristics

* The timings are also valid for inputs sampled on the negative clock edge.

1.5V

FB_CLK (80MHz)

TSETUP

THOLD

Invalid

1.5V Valid 1.5V

Invalid

Input Setup And Hold

Input Rise Time

Input Fall Time

t

rise

V

= V

IH

h

V = V

l

IL

fall

V

= V

IH

h

V = V

l

IL

FB_CLK

B4

B5

Inputs

Figure 9. General Input Timing Requirements

5.7.1 FlexBus

A multi-function external bus interface called FlexBus is provided with basic functionality to interface to

slave-only devices up to a maximum bus frequency of 80MHz. It can be directly connected to

asynchronous or synchronous devices such as external boot ROMs, flash memories, gate-array logic, or

other simple target (slave) devices with little or no additional circuitry. For asynchronous devices a simple

chip-select based interface can be used. The FlexBus interface has six general purpose chip-selects

(FB_CS[5:0]) which can be configured to be distributed between the FlexBus or SDRAM memory

interfaces. Chip-select, FB_CS0 can be dedicated to boot ROM access and can be programmed to be byte

(8 bits), word (16 bits), or longword (32 bits) wide. Control signal timing is compatible with common

ROM/flash memories.

5.7.1.1 FlexBus AC Timing Characteristics

The following timing numbers indicate when data will be latched or driven onto the external bus, relative

to the system clock.

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Freescale Semiconductor

23

Preliminary

Preliminary Electrical Characteristics

Table 10. FlexBus AC Timing Specifications

Num

Characteristic

Symbol

Min

Max

Unit Notes

Frequency of Operation

FB1 Clock Period (FB_CLK)

—

80

12.5

7.0

Mhz

ns

f_sys/3

t_FBCK

t_cyc

1

FB2 Address, Data, and Control Output Valid (A[23:0], D[31:0],

FB_CS[5:0], R/W, TS, BE/BWE[3:0] and OE)

t_FBCHDCV

ns

1, 2

FB3 Address, Data, and Control Output Hold (A[23:0], D[31:0],

FB_CS[5:0], R/W, TS, BE/BWE[3:0], and OE)

t_FBCHDCI

1

—

ns

FB4 Data Input Setup

t_DVFBCH

t_DIFBCH

t_CVFBCH

t_CIFBCH

t_FBCHAV

t_FBCHAI

3.5

0

—

6.0

—

ns

FB5 Data Input Hold

FB6 Transfer Acknowledge (TA) Input Setup

FB7 Transfer Acknowledge (TA) Input Hold

FB8 Address Output Valid (A[23:0])

FB9 Address Output Hold (A[23:0])

4

0

3

—

1

N₁OTES:

Timing for chip selects only applies to the FB_CS[5:0] signals. Please see Section 5.8.2, “DDR SDRAM AC Timing

Characteristics” for SD_CS[3:0] timing.

2

3

The FlexBus supports programming an extension of the address hold. Please consult the MCF5329 Reference

Manual for more information.

These specs are used when the A[23:0] signals are configured as 23-bit, non-muxed FlexBus address signals.

FB_CLK

FB1

FB3

A[23:0]

D[31:0]

R/W

A[23:0]

FB2

FB5

DATA

FB4

TS

FB_CSn

BE/BWEn

FB7

OE

TA

FB6

Figure 10. FlexBus Read Timing.

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Preliminary

24

Freescale Semiconductor

Preliminary Electrical Characteristics

FB_CLK

A[23:0]

D[31:0]

R/W

FB1

FB3

FB2

FB3

TS

FB_CSn

BE/BWEn

FB7

OE

TA

FB6

Figure 11. Flexbus Write Timing

5.8 SDRAM Bus

The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports

either standard SDRAM or double data rate (DDR) SDRAM, but it does not support both at the same time.

5.8.1 SDR SDRAM AC Timing Characteristics

The following timing numbers indicate when data will be latched or driven onto the external bus, relative

to the memory bus clock, when operating in SDR mode on write cycles and relative to SD_DQS on read

cycles. The device’s SDRAM controller is a DDR controller that has an SDR mode. Because it is designed

to support DDR, a DQS pulse must still be supplied to device for each data beat of an SDR read. Te

processor accomplishes this by asserting a signal named SD_DQS during read cycles. Care must be taken

during board design to adhere to the following guidelines and specs with regard to the SDR_DQS signal

and its usage.

Table 11. SDR Timing Specifications

Symbol

Characteristic

Frequency of Operation

Symbol

Min

Max

Unit

Notes

1

TBD

12.5

—

80

Mhz

ns

2

3

SD1 Clock Period

SD2 Clock Skew

t_SDCK

t_SDSK

TBD

0.55

SD3 Pulse Width High

t_SDCKH

0.45

SD_CLK

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Preliminary

Freescale Semiconductor

25

Preliminary Electrical Characteristics

Table 11. SDR Timing Specifications (continued)

Symbol

Characteristic

Symbol

Min

Max

Unit

Notes

4

SD4 Pulse Width Low

t_SDCKH

0.45

—

0.55

SD_CLK

ns

SD5 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,

SD_CS[1:0] - Output Valid

t_SDCHACV

0.5 × SD_CLK

+ 1.0

SD6 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,

SD_CS[1:0] - Output Hold

t_SDCHACI

2.0

—

ns

5

6

SD7 SD_SDR_DQS Output Valid

t_DQSOV

Self timed

ns

SD8 SD_DQS[3:0] input setup relative to SD_CLK

t_DQVSDCH

0.25 ×

0.40 × SD_CLK

SD_CLK

7

8

SD9 SD_DQS[3:2] input hold relative to SD_CLK

t_DQISDCH

t_DVSDCH

t_DISDCH

Does not apply. 0.5×SD_CLK fixed

width.

SD10 Data (D[31:0]) Input Setup relative to SD_CLK (reference

only)

0.25 ×

—

ns

SD_CLK

SD11 Data Input Hold relative to SD_CLK (reference only)

1.0

—

ns

SD12 Data (D[31:0]) and Data Mask(SD_DQM[3:0]) Output Valid t_SDCHDMV

0.75 × SD_CLK

+ 0.5

SD13 Data (D[31:0]) and Data Mask (SD_DQM[3:0]) Output Hold t_SDCHDMI

1.5

—

ns

NOTES:

1

The device supports same frequency of operation for both FlexBus and SDRAM clock operates as that of the internal bus clock.

Please see the PLL chapter of the MCF5329 Reference Manual for more information on setting the SDRAM clock rate.

SD_CLK is one SDRAM clock in (ns).

Pulse width high plus pulse width low cannot exceed min and max clock period.

SD_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle variation

from this guideline is expected. SD_DQS will only pulse during a read cycle and one pulse will occur for each data beat.

SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle

variation from this guideline is expected. SDR_DQS will only pulse during a read cycle and one pulse will occur for each data

beat.

2

3

4

5

6

7

8

The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge does

not affect the memory controller.

Since a read cycle in SDR mode still uses the DQS circuit within the device, it is most critical that the data valid window be

centered 1/4 clk after the rising edge of DQS. Ensuring that this happens will result in successful SDR reads. The input setup

spec is just provided as guidance.

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

26

Freescale Semiconductor

Preliminary

Preliminary Electrical Characteristics

SD1

SD3

SD2

SD_CLK0

SD2

SD4

SD_CLK1

SD6

SD_CSn

SD_RAS

SD_CAS

SD_WE

CMD

SD5

A[23:0]

SD_BA[1:0]

ROW

COL

SD12

SDDM

D[31:0]

SD13

WD1

WD2

WD3

WD4

Figure 12. SDR Write Timing

SD1

SD2

SD_CLK0

SD_CLK1

SD6

SD_CSn,

SD_RAS,

SD_CAS,

SD_WE

CMD

3/4 MCLK

Reference

SD5

A[23:0],

SD_BA[1:0]

ROW

COL

tDQS

SDDM

SD7

SD_DQS (Measured at Output Pin)

SD_DDQS (Measured at Input Pin)

Board Delay

SD9

Board Delay

SD8

Delayed

SD_CLK

SD10

D[31:0]

from

WD1

WD2

WD3

WD4

Memories

NOTE: Data driven from memories relative

to delayed memory clock.

SD11

Figure 13. SDR Read Timing

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Preliminary

Freescale Semiconductor

27

Preliminary Electrical Characteristics

5.8.2 DDR SDRAM AC Timing Characteristics

When using the SDRAM controller in DDR mode, the following timing numbers must be followed to

properly latch or drive data onto the memory bus. All timing numbers are relative to the four DQS byte

lanes. The following timing numbers are subject to change at anytime, and are only provided to aid in early

board design. Please contact your local Freescale representative if questions develop.

Table 12. DDR Timing Specifications

Num

Characteristic

Frequency of Operation

Symbol

Min

Max

Unit

Notes

1

t_DDCK

t_DDSK

80

TBD

0.45

—

TBD

12.5

0.55

Mhz

ns

2

3

4

DD1 Clock Period

DD2 Pulse Width High

DD3 Pulse Width Low

t_DDCKH

t_DDCKL

t_SDCHACV

SD_CLK

ns

DD4 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,

SD_CS[1:0] - Output Valid

0.5 × SD_CLK

+ 1.0

DD5 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,

SD_CS[1:0] - Output Hold

t_SDCHACI

2.0

—

ns

DD6 Write Command to first DQS Latching Transition

t_CMDVDQ

t_DQDMV

—

1.25

—

SD_CLK

ns

5

6

DD7 Data and Data Mask Output Setup (DQ-->DQS)

Relative to DQS (DDR Write Mode)

1.5

7

DD8 Data and Data Mask Output Hold (DQS-->DQ)

Relative to DQS (DDR Write Mode)

t_DQDMI

1.0

—

ns

8

9

DD9 Input Data Skew Relative to DQS (Input Setup)

DD10 Input Data Hold Relative to DQS.

t_DVDQ

t_DIDQ

—

1

ns

0.25 × SD_CLK

—

+ 0.5ns

DD11 DQS falling edge from SDCLK rising (output hold time) t_DQLSDCH

0.5

0.9

—

ns

DD12 DQS input read preamble width

DD13 DQS input read postamble width

DD14 DQS output write preamble width

DD15 DQS output write postamble width

N₁OTES:

t_DQRPRE

t_DQRPST

t_DQWPRE

t_DQWPST

1.1

0.6

SD_CLK

0.4

0.25

0.4

0.6

The frequency of operation is either 2x or 4x the FB_CLK frequency of operation. FlexBus and SDRAM clock operate at the

same frequency as the internal bus clock.

2

3

4

SD_CLK is one SDRAM clock in (ns).

Pulse width high plus pulse width low cannot exceed min and max clock period.

Command output valid should be 1/2 the memory bus clock (SD_CLK) plus some minor adjustments for process,

temperature, and voltage variations.

This specification relates to the required input setup time of today’s DDR memories. Rigoletto’s output setup should be larger

than the input setup of the DDR memories. If it is not larger, then the input setup on the memory will be in violation.

MEM_DATA[31:24] is relative to MEM_DQS[3], MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to

MEM_DQS[1], and MEM_[7:0] is relative MEM_DQS[0].

The first data beat will be valid before the first rising edge of DQS and after the DQS write preamble. The remaining data

beats will be valid for each subsequent DQS edge.

This specification relates to the required hold time of today’s DDR memories. MEM_DATA[31:24] is relative to MEM_DQS[3],

MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to MEM_DQS[1], and MEM_[7:0] is relative

MEM_DQS[0].

5

6

7

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

28

Freescale Semiconductor

Preliminary

Preliminary Electrical Characteristics

8

Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line

becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other

factors).

⁹Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line

becomes invalid.

SD_CLK

V_IX

V_ID

V_MP

V_IX

SD_CLK

Figure 14. SD_CLK and SD_CLK crossover timing

DD1

DD2

SD_CLK

DD3

SD_CLK

DD5

SD_CSn,SD_WE,

SD_RAS, SD_CAS

CMD

ROW

DD4

DD6

A[13:0]

COL

DD7

DM3/DM2

SD_DQS3/SD_DQS2

D[31:24]/D[23:16]

DD8

DD7

WD1 WD2 WD3 WD4

DD8

Figure 15. DDR Write Timing

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Preliminary

Freescale Semiconductor

29

Preliminary Electrical Characteristics

DD1

DD2

SD_CLK

DD3

SD_CLK

DD5

CL=2

SD_CSn,SD_WE,

SD_RAS, SD_CAS

CMD

ROW

DD4

CL=2.5

A[13:0]

COL

DD9

DQS Read

Postamble

DQS Read

Preamble

SD_DQS3/SD_DQS2

D[31:24]/D[23:16]

DD10

WD1 WD2 WD3 WD4

DQS Read

Preamble

DQS Read

Postamble

SD_DQS3/SD_DQS2

D[31:24]/D[23:16]

WD1 WD2 WD3 WD4

Figure 16. DDR Read Timing

5.9 General Purpose I/O Timing

1

Table 13. GPIO Timing

Num

Characteristic

Symbol

Min

Max

Unit

G1 FB_CLK High to GPIO Output Valid

G2 FB_CLK High to GPIO Output Invalid

G3 GPIO Input Valid to FB_CLK High

G4 FB_CLK High to GPIO Input Invalid

t_CHPOV

t_CHPOI

t_PVCH

t_CHPI

—

1.5

9

10

—

ns

1.5

N₁OTES:

GPIO pins include: IRQn, PWM, UART, FlexCAN, and Timer pins.

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Preliminary

30

Freescale Semiconductor

Preliminary Electrical Characteristics

FB_CLK

G2

G1

GPIO Outputs

G3

G4

GPIO Inputs

Figure 17. GPIO Timing

5.10 Reset and Configuration Override Timing

Table 14. Reset and Configuration Override Timing

Num

Characteristic

Symbol

Min

Max

Unit

R1 RESET Input valid to FB_CLK High

t_RVCH

t_CHRI

9

1.5

5

—

10

—

1

ns

R2 FB_CLK High to RESET Input invalid

R3 RESET Input valid Time ¹

t_RIVT

t_CYC

ns

R4 FB_CLK High to RSTOUT Valid

t_CHROV

t_ROVCV

t_COS

—

0

R5 RSTOUT valid to Config. Overrides valid

R6 Configuration Override Setup Time to RSTOUT invalid

R7 Configuration Override Hold Time after RSTOUT invalid

R8 RSTOUT invalid to Configuration Override High Impedance

ns

20

0

t_CYC

ns

t_COH

t_ROICZ

—

t_CYC

N₁OTES:

During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to

the system. Thus, RESET must be held a minimum of 100 ns.

FB_CLK

R1

R2

R3

RESET

R4

RSTOUT

R8

R5

R6

R7

Configuration Overrides*:

(RCON, Override pins])

Figure 18. RESET and Configuration Override Timing

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Preliminary

Freescale Semiconductor

31

Preliminary Electrical Characteristics

NOTE

Refer to the CCM chapter of the MCF5329 Reference Manual for more

information.

5.11 LCD Controller Timing Specifications

This sections lists the timing specifications for the LCD Controller.

Table 15. LCD_LSCLK Timing

Num

Parameter

Minimum Maximum

Unit

T1

T2

T3

LCD_LSCLK Period

Pixel data setup time

Pixel data up time

25

11

2000

—

ns

—

Note: The pixel clock is equal to LCD_LSCLK / (PCD + 1). When it is in CSTN, TFT or monochrome mode

with bus width = 1,LCD_LSCLK is equal to the pixel clock. When it is in monochrome with other bus width

settings, LCD_LSCLK is equal to the pixel clock divided by bus width. The polarity of LCD_LSCLK and LCD_LD

signals can also be programmed.

T1

LCD_LSCLK

LCD_LD[17:0]

T2

T3

Figure 19. LCD_LSCLK to LCD_LD[17:0] timing diagram

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Preliminary

32

Freescale Semiconductor

Preliminary Electrical Characteristics

Non-display region

Display region

T3

T1

T4

LCD_VSYNC

LCD_HSYNC

LCD_OE

T2

Line Y

Line 1

Line Y

LCD_LD[17:0]

T5

T6

XMAX

T7

LCD_HSYNC

LCD_LSCLK

LCD_OE

(1,1)

(1,2)

LCD_LD[15:0]

(1,X)

Figure 20. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing

Table 16. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing

Number

Description

Minimum

Value

Unit

T1

T2

T3

T4

T5

T6

T7

End of LCD_OE to beginning of LCD_VSYNC

LCD_HSYNC period

T5+T6+T7-1

(VWAIT1·T2)+T5+T6+T7-1

XMAX+T5+T6+T7

VWIDTH·T2

Ts

—

T2

1

LCD_VSYNC pulse width

End of LCD_VSYNC to beginning of LCD_OE

LCD_HSYNC pulse width

(VWAIT2·T2)+1

HWIDTH+1

1

End of LCD_HSYNC to beginning to LCD_OE

End of LCD_OE to beginning of LCD_HSYNC

3

HWAIT2+3

1

HWAIT1+1

Note: Ts is the LCD_LSCLK period. LCD_VSYNC, LCD_HSYNC and LCD_OE can be programmed as active high or

active low. In Figure 20, all 3 signals are active low. LCD_LSCLK can be programmed to be deactivated during the

LCD_VSYNC pulse or the LCD_OE deasserted period. In Figure 20, LCD_LSCLK is always active.

Note: XMAX is defined in number of pixels in one line.

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Freescale Semiconductor

33

Preliminary

Preliminary Electrical Characteristics

XMAX

LCD_LSCLK

LCD_LD

D2

D1

D320

LCD_SPL_SPR

T1

T3

T2

LCD_HSYNC

T4

LCD_CLS

T5

T6

LCD_PS

T7

LCD_REV

Figure 21. Sharp TFT Panel Timing

Table 17. Sharp TFT Panel Timing

Minimum

Num

Description

LCD_SPL/LCD_SPR pulse width

Value

Unit

T1

T2

T3

T4

T5

T6

T7

—

1

Ts

End of LCD_LD of line to beginning of LCD_HSYNC

End of LCD_HSYNC to beginning of LCD_LD of line

LCD_CLS rise delay from end of LCD_LD of line

LCD_CLS pulse width

HWAIT1+1

4

HWAIT2 + 4

3

CLS_RISE_DELAY+1

CLS_HI_WIDTH+1

1

LCD_PS rise delay from LCD_CLS negation

LCD_REV toggle delay from last LCD_LD of line

0

PS_RISE_DELAY

1

REV_TOGGLE_DELAY+1

Note: Falling of LCD_SPL/LCD_SPR aligns with first LCD_LD of line.

Note: Falling of LCD_PS aligns with rising edge of LCD_CLS.

Note: LCD_REV toggles in every LCD_HSYN period.

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Preliminary

34

Freescale Semiconductor

Preliminary Electrical Characteristics

T1

LCD_VSYNC

T3

T4

T2

XMAX

LCD_HSYNC

LCD_LSCLK

Ts

LCD_LD[15:0]

Figure 22. Non-TFT Mode Panel Timing

Table 18. Non-TFT Mode Panel Timing

Num

Description

Minimum

Value

Unit

T1

T2

T3

T4

LCD_HSYNC to LCD_VSYNC delay

LCD_HSYNC pulse width

2

1

HWAIT2 + 2

HWIDTH + 1

0 ≤ T3 ≤ Ts

HWAIT1 + 1

Tpix

—

LCD_VSYNC to LCD_LSCLK

LCD_LSCLK to LCD_HSYNC

—

1

Tpix

Note: Ts is the LCD_LSCLK period while Tpix is the pixel clock period. LCD_VSYNC, LCD_HSYNC and LCD_LSCLK

can be programmed as active high or active low. In Figure 22, all these 3 signals are active high. When it is in CSTN

mode or monochrome mode with bus width = 1, T3 = Tpix = Ts. When it is in monochrome mode with bus width = 2, 4

and 8, T3 = 1, 2 and 4 Tpix respectively.

5.12 USB On-The-Go

The MCF5329 device is compliant with industry standard USB 2.0 specification.

5.13 ULPI Timing Specification

Control and data timing requirements for the ULPI pins are given in Table 19. These timings apply in

synchronous mode only. All timings are measured with either a 60 MHz input clock from the

USB_CLKIN pin or a 60MHz output clock at the ULPI_CLK pin. Both clocks need to maintain a 50%

duty cycle. Control signals and 8-bit data are always clocked on the rising edge, while the optional

double-edge 4-bit data signals are clocked on rising and falling edges.

The ULPI interface on the MCF5329 processor is compliant with the industry standard definition.

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Freescale Semiconductor

35

Preliminary

Preliminary Electrical Characteristics

TDDD

THD

TSD

THC

TDD

TDDD

THDD

TSC

TDC

ULPI_CLK

ULPI_STP

(Input)

ULPI_DATA

(Input-8bit)

ULPI_DATA

(Input-4bit)

TSDD

ULPI_DIR/ULPI_NXT

(Output)

ULPI_DATA

(Output-8bit)

ULPI_DATA

(Output-4bit)

Figure 23. ULPI Timing Diagram

Table 19. ULPI Interface Timing

Parameter

Symbol

Min

Max

Units

Timing with reference to ULPI_CLK

Setup time (control in, 8-bit data in)

Output delay (control out, 8-bit data out)

Timing with reference to USB_CLKIN

Setup time (control in, 8-bit data in)

Hold time (control in, 8-bit data in)

Output delay (control out, 8-bit data out)

TSC, TSD

THC, THD

TDC, TDD

—

0.0

—

6.0

—

ns

9.0

TSC, TSD

THC, THD

TDC, TDD

—

-1.5

—

3.0

—

ns

6.0

5.14 SSI Timing Specifications

The following figure and table lists the specifications for the SSI module.

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Preliminary

36

Freescale Semiconductor

Preliminary Electrical Characteristics

S1

S2

S3

SSI_BCLK

S4

S5

SSI_MCLK

STFS

S6

S7

SSI_TXD (Output)

STFS

S6

SSI_RXD (Input)

Note: SSI External. Continous clock Synchronous mode only

Figure 24. SSI External Continous Clock Timing Diagram

Table 20. SSI Timing

1.8 +/- 0.10V

Num

Description

Unit

Minimum

Maximum

S1

S2

SSI_BCLK clock period

SSI_BCK high-level time

SSI_BCK low-level time

1/(64f_s)¹

35

49

—

ns

S3

35

S4

SSI_BCK rising edge to SSI_MCLK edge

SSI_MCLK edge to SSI_BCLK rising edge

SSI_TXD/SSI_RXD data set-up time

SSI_TXD/SSI_RXD data hold time

10

S5

10

S6

10

S7

10

NOTES:

¹f_{s is the sampling frequency. SSI_BCLK can be operated upto 512 times the sampling frequency to a max frequency of 49.152MHz}

5.15 I²C Input/Output Timing Specifications

2

Table 21 lists specifications for the I C input timing parameters shown in Figure 25.

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Freescale Semiconductor

37

Preliminary

Preliminary Electrical Characteristics

2

Table 21. I C Input Timing Specifications between SCL and SDA

Num

Characteristic

Start condition hold time

Min

Max

Units

I1

I2

I3

I4

I5

I6

I7

I8

I9

2

8

—

1

t_cyc

ms

ns

Clock low period

I2C_SCL/I2C_SDA rise time (V_IL= 0.5 V to V_IH= 2.4 V)

Data hold time

—

0

—

1

I2C_SCL/I2C_SDA fall time (V_IH= 2.4 V to V_IL= 0.5 V)

Clock high time

—

4

ms

t_cyc

ns

—

Data setup time

0

Start condition setup time (for repeated start condition only)

Stop condition setup time

2

t_cyc

2

Table 22 lists specifications for the I C output timing parameters shown in Figure 25.

2

Table 22. I C Output Timing Specifications between SCL and SDA

Num

I1¹Start condition hold time

I2 ¹Clock low period

Characteristic

Min

Max

Units

6

—

3

t_cyc

µs

10

—

7

I3 ²I2C_SCL/I2C_SDA rise time (V_IL= 0.5 V to V_IH= 2.4 V)

I4 ¹Data hold time

t_cyc

ns

I5 ³I2C_SCL/I2C_SDA fall time (V_IH= 2.4 V to V_IL= 0.5 V)

I6 ¹Clock high time

—

10

2

—

t_cyc

I7 ¹Data setup time

I8 ¹Start condition setup time (for repeated start condition only)

I9 ¹Stop condition setup time

20

10

N₁OTES:

Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum

frequency (IFDR = 0x20) results in minimum output timings as shown in Table 22. The I²C interface is

designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual

position is affected by the prescale and division values programmed into the IFDR; however, the numbers

given in Table 22 are minimum values.

Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively

drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance

and pull-up resistor values.

2

3

Specified at a nominal 50-pF load.

Figure 25 shows timing for the values in Table 22 and Table 21.

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Preliminary

38

Freescale Semiconductor

Preliminary Electrical Characteristics

I5

I6

I2

I2C_SCL

I2C_SDA

I7

I8

I1

I9

I4

I3

2

Figure 25. I C Input/Output Timings

5.16 Fast Ethernet AC Timing Specifications

MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.

5.16.1 MII Receive Signal Timing (FEC_RXD[3:0], FEC_RXDV,

FEC_RXER, and FEC_RXCLK)

The receiver functions correctly up to a FEC_RXCLK maximum frequency of 25 MHz +1%. There is no

minimum frequency requirement. In addition, the processor clock frequency must exceed twice the

FEC_RXCLK frequency.

Table 23 lists MII receive channel timings.

Table 23. MII Receive Signal Timing

Num

Characteristic

Min

Max

Unit

M1

M2

M3

M4

FEC_RXD[3:0], FEC_RXDV, FEC_RXER to FEC_RXCLK setup

FEC_RXCLK to FEC_RXD[3:0], FEC_RXDV, FEC_RXER hold

FEC_RXCLK pulse width high

5

—

ns

5

ns

35%

65%

FEC_RXCLK period

FEC_RXCLK pulse width low

Figure 26 shows MII receive signal timings listed in Table 23.

M3

FEC_RXCLK (input)

M4

FEC_RXD[3:0] (inputs)

FEC_RXDV

FEC_RXER

M1

M2

Figure 26. MII Receive Signal Timing Diagram

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Preliminary

Freescale Semiconductor

39

Preliminary Electrical Characteristics

5.16.2 MII Transmit Signal Timing (FEC_TXD[3:0], FEC_TXEN,

FEC_TXER, FEC_TXCLK)

Table 24 lists MII transmit channel timings.

The transmitter functions correctly up to a FEC_TXCLK maximum frequency of 25 MHz +1%. There is

no minimum frequency requirement. In addition, the processor clock frequency must exceed twice the

FEC_TXCLK frequency.

The transmit outputs (FEC_TXD[3:0], FEC_TXEN, FEC_TXER) can be programmed to transition from

either the rising or falling edge of FEC_TXCLK, and the timing is the same in either case. This options

allows the use of non-compliant MII PHYs.

Refer to the Ethernet chapter for details of this option and how to enable it.

Table 24. MII Transmit Signal Timing

Num

Characteristic

Min

Max

Unit

M5

M6

M7

M8

FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER invalid

FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER valid

FEC_TXCLK pulse width high

5

—

25

ns

—

ns

35%

65%

FEC_TXCLK period

FEC_TXCLK pulse width low

Figure 27 shows MII transmit signal timings listed in Table 24.

M7

FEC_TXCLK (input)

M5

M8

FEC_TXD[3:0] (outputs)

FEC_TXEN

FEC_TXER

M6

Figure 27. MII Transmit Signal Timing Diagram

5.16.3 MII Async Inputs Signal Timing (FEC_CRS and FEC_COL)

Table 25 lists MII asynchronous inputs signal timing.

Table 25. MII Async Inputs Signal Timing

Num

Characteristic

Min

Max

Unit

M9

FEC_CRS, FEC_COL minimum pulse width

1.5

—

FEC_TXCLK period

Figure 28 shows MII asynchronous input timings listed in Table 25.

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Preliminary

40

Freescale Semiconductor

Preliminary Electrical Characteristics

FEC_CRS

FEC_COL

M9

Figure 28. MII Async Inputs Timing Diagram

5.16.4 MII Serial Management Channel Timing (FEC_MDIO and

FEC_MDC)

Table 26 lists MII serial management channel timings. The FEC functions correctly with a maximum

MDC frequency of 2.5 MHz.

Table 26. MII Serial Management Channel Timing

Num

Characteristic

Min Max

Unit

M10 FEC_MDC falling edge to FEC_MDIO output invalid (minimum

propagation delay)

0

—

ns

M11 FEC_MDC falling edge to FEC_MDIO output valid (max prop delay)

M12 FEC_MDIO (input) to FEC_MDC rising edge setup

M13 FEC_MDIO (input) to FEC_MDC rising edge hold

M14 FEC_MDC pulse width high

—

10

0

25

—

ns

40% 60% FEC_MDC period

M15 FEC_MDC pulse width low

Figure 29 shows MII serial management channel timings listed in Table 26.

M14

M15

FEC_MDC (output)

FEC_MDIO (output)

M10

M11

FEC_MDIO (input)

M12

M13

Figure 29. MII Serial Management Channel Timing Diagram

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Preliminary

Freescale Semiconductor

41

Preliminary Electrical Characteristics

5.17 32-Bit Timer Module Timing Specifications

Table 27 lists timer module AC timings.

Table 27. Timer Module AC Timing Specifications

Name

Characteristic

Unit

Min

Max

T1

T2

DT0IN / DT1IN / DT2IN / DT3IN cycle time

DT0IN / DT1IN / DT2IN / DT3IN pulse width

3

1

—

t_CYC

5.18 QSPI Electrical Specifications

Table 28 lists QSPI timings.

Table 28. QSPI Modules AC Timing Specifications

Name

Characteristic

Min

Max

Unit

QS1

QS2

QS3

QS4

QS5

QSPI_CS[3:0] to QSPI_CLK

1

—

2

510

10

—

t_CYC

ns

QSPI_CLK high to QSPI_DOUT valid.

QSPI_CLK high to QSPI_DOUT invalid. (Output hold)

QSPI_DIN to QSPI_CLK (Input setup)

QSPI_DIN to QSPI_CLK (Input hold)

ns

9

—

ns

9

—

ns

The values in Table 28 correspond to Figure 30.

QS1

QSPI_CS[3:0]

QSPI_CLK

QS2

QSPI_DOUT

QS3

QS4

QS5

QSPI_DIN

Figure 30. QSPI Timing

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Preliminary

42

Freescale Semiconductor

Preliminary Electrical Characteristics

5.19 JTAG and Boundary Scan Timing

Table 29. JTAG and Boundary Scan Timing

Num

Characteristics¹

TCLK Frequency of Operation

Symbol

Min

Max

Unit

J1

J2

J3

J4

J5

J6

J7

J8

J9

f_JCYC

t_JCYC

DC

4

1/4

—

3

f_sys/3

t_CYC

ns

TCLK Cycle Period

TCLK Clock Pulse Width

t_JCW

26

0

TCLK Rise and Fall Times

t_JCRF

ns

Boundary Scan Input Data Setup Time to TCLK Rise

Boundary Scan Input Data Hold Time after TCLK Rise

TCLK Low to Boundary Scan Output Data Valid

TCLK Low to Boundary Scan Output High Z

TMS, TDI Input Data Setup Time to TCLK Rise

t_BSDST

t_BSDHT

t_BSDV

4

—

33

—

26

8

ns

26

0

ns

t_BSDZ

0

ns

t_TAPBST

t_TAPBHT

t_TDODV

t_TDODZ

t_TRSTAT

t_TRSTST

4

ns

J10 TMS, TDI Input Data Hold Time after TCLK Rise

J11 TCLK Low to TDO Data Valid

10

0

ns

J12 TCLK Low to TDO High Z

0

ns

J13 TRST Assert Time

100

10

—

ns

J14 TRST Setup Time (Negation) to TCLK High

ns

N₁OTES:

JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.

J2

J3

V_IH

TCLK

(input)

V_IL

J4

Figure 31. Test Clock Input Timing

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Preliminary

Freescale Semiconductor

43

Preliminary Electrical Characteristics

TCLK

V_IL

V_IH

J5

Input Data Valid

J6

Data Inputs

J7

J8

Data Outputs

Output Data Valid

Data Outputs

J7

Output Data Valid

Figure 32. Boundary Scan (JTAG) Timing

TCLK

V_IL

V_IH

J9

Input Data Valid

J10

TDI

TMS

J11

TDO

Output Data Valid

J12

J11

TDO

Output Data Valid

Figure 33. Test Access Port Timing

TCLK

TRST

J14

J13

Figure 34. TRST Timing

5.20 Debug AC Timing Specifications

Table 30 lists specifications for the debug AC timing parameters shown in Figure 36.

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

44

Freescale Semiconductor

Preliminary

Preliminary Electrical Characteristics

Table 30. Debug AC Timing Specification

Characteristic

Num

Units

Min

Max

DE0

DE1

DE2

DE3

DE4

PSTCLK cycle time

—

4

0.3

—

t_cyc

ns

PST valid to PSTCLK high

PSTCLK high to PST invalid

DSCLK cycle time

1.5

5

ns

t_cyc

ns

DSI valid to DSCLK high

1

DE5¹DSCLK high to DSO invalid

4

DE6

DE7

BKPT input data setup time to FB_CLK high

FB_CLK high to BKPT invalid

4

0

ns

N₁OTES:

DSCLK and DSI are synchronized internally. DE4 is measured from the synchronized DSCLK input

relative to the rising edge of FB_CLK.

Figure 35 shows real-time trace timing for the values in Table 30.

PSTCLK

DE0

DE1

DE2

PST[3:0]

DDATA[3:0]

Figure 35. Real-Time Trace AC Timing

Figure 36 shows BDM serial port AC timing and BKPT pin timing for the values in Table 30.

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Freescale Semiconductor

45

Preliminary

Revision History

FB_CLK

BKPT

DE6

DE7

DE5

DSCLK

DSI

DE3

Current

Past

DSO

Current

Figure 36. BDM Serial Port AC Timing

6 Revision History

Table 31. MCF5329DS Document Revision History

Rev. No.

Substantive Changes

Date of Release

0

• Initial release.

11/2005

3/2006

0.1

• Added not to Section 4, “Mechanicals and Pinouts.”

• Added “top view” and “bottom view” where appropriate in mechanical

drawings and pinout figures.

• Figure 9: Corrected “FB_CLK (75MHz)” label to “FB_CLK (80MHz)”

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Preliminary

46

Freescale Semiconductor

THIS PAGE INTENTIONALLY LEFT BLANK

MCF5329 ColdFire^®Microprocessor Data Sheet, Rev. 0.1

Preliminary

Freescale Semiconductor

47

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MCF5329DS

Rev. 0.1

03/2006


型号：	MCF5328CVM240
厂家：	ADVANCED ANALOGIC TECHNOLOGIES
描述：	MCF5329 ColdFire Microprocessor Data Sheet MCF5329的ColdFire微处理器数据手册微处理器
文件：	总48页 (文件大小：975K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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