APL158115UC-TRG [ANPEC]
DUAL INPUT LOW DROPOUT REGULATOR; 双输入低压差稳压器
| 型号： | APL158115UC-TRG |
| 厂家： | 
ANPEC ELECTRONICS COROPRATION |
| 描述： | DUAL INPUT LOW DROPOUT REGULATOR |
| 文件： | 总17页 (文件大小：310K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APL1581
DUAL INPUT LOW DROPOUT REGULATOR
Features
General Description
·
·
Adjustable or Fixed Output
The APL1581 series of high performance positive volt-
age regulators are designed for use in applications re-
quiring very low dropout voltage at 5Amp.
520mV typ. Dropout at 5A in Dual Power
Voltage Mode
·
·
·
·
·
Remote Sense Pin Available
2% Accuracy Over Temperature Range
Build-in Over Temperature Protection
Build-in Current Limit
The APL1581 can provide a output voltage at the range of
1.25V to 2.55V where both 5V and 3.3V voltage supplies
are available.
The superior dropout characteristics result in reducing
heat dissipation compared to regular LDOs. The APL1581
also provides excellent regulation over line, load, and tem-
perature variations.
5 Pin TO-220 and TO-263, TO-252, SOP-8-P
Packages
·
Lead Free and Green Devices Available
(RoHS Compliant)
Current limit is trimmed to ensure specified output cur-
rent and controlled short-circuit current. On-chip thermal
limiting provides protection against any combina-
tion of overload that would create excessive junction
temperature.
Applications
·
·
·
·
Microprocessor Supplies
Chip Set Supplies
VGA Card Power
The APL1581 is available in both the through-hole and
surface mount versions of the industry standard 5-Pin
TO-220 and TO-263, TO-252, SOP-8P power packages.
LCD Monitor Power
Ordering and Marking Information
Package Code
F : TO-220-5
KA : SOP-8P
APL1581
G : TO-263-5
U :TO-252-5
Assembly Material
Handling Code
Temperature Range
C : 0 to 70 C
°
Handling Code
TR : Tape & Reel
Voltage Code :
Temperature Range
Package Code
15 : 1.5V
25 : 2.5V
18 : 1.8V
Blank : Adjustable Version
Assembly Material
L : Lead Free Device
Voltage Code
G : Halogen and Lead Free Device
15
APL1581
XXXXX
APL1581
XXXXX
APL1581-15 F/G/U :
XXXXX - Date Code
XXXXX - Date Code
APL1581 KA :
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Copyright ã ANPEC Electronics Corp.
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Rev. B.5 - Mar., 2008
APL1581
Pin Configuration
VIN
5
4
5
VIN
VCNTL
4
3
2
1
VCNTL
TAB is VOUT
3
2
1
VOUT
VOUT
TAB is VOUT
ADJ (or GND)
VSENSE
ADJ(or GND)
VSENSE
Front View of TO-252-5
Front View of TO-220-5
VSENSE
ADJ (or GND)
VCNTL
VOUT
VOUT
VOUT
VOUT
1
2
3
4
8
7
6
5
5
4
VIN
VCNTL
TAB is VOUT
3
2
1
VOUT
VIN
ADJ (or GND)
VSENSE
SOP-8-P (Top View)
NC = No internal connection
= Thermal Pad
Front View of TO-263-5
(connected to VOUT plane for better heat
dissipation)
Pin 5~8 must be connected together by a shortest
wide track or plane.
Pin Description
PIN
Description
Name
I/O
Positive side of the reference voltage, which allows remote sensing to
obtain excellent load regulation.
VSENSE
I
Negative side of the reference voltage, which allows to use resistor divider
to set an expect output voltage. A small bypass capacitor can be connected
from this pin to ground to improve PSRR performance.
ADJ
O
O
For fixed voltage devices this is the bottom of the resistor divider that sets
the output voltage.
GND
Output pin of the regulator, which connects to the TAB. A minimum of 10mF
capacitor must be connected from this pin to ground to ensure the stability.
VOUT
VCNTL
VIN
O
I
Supply pin of the control circuitry, which must be always higher than VOUT
for the device to regulate. (See electrical characteristics)
Power input pin of the regulator, which must be always higher than VOUT for
the device to regulate. (See electrical characteristics)
I
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Rev. B.5 - Mar., 2008
APL1581
Block Diagram
VOUT
VIN
VCNTL
Current
Limit
VSENSE
ADJ/GND
Thermal
Protection
Voltage
Regulation
Absolute Maximum Ratings (Note 1, 2)
Symbol
Parameter
Rating
Unit
V
VIN
Input Voltage
7
7
VCNTL
Control Voltage
V
PD
Power Dissipation
Internally Limited
W
TJ
Junction Temperature
150
-65 to +150
260
°C
°C
°C
TSTG
TSDR
Storage Temperature Range
Maximum Lead Soldering Temperature, 10 Seconds
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 2: The maximum allowable power dissipation at any TA (ambient temperature) is calculated using: PD
(max) = (TJ – TA) / qJA; TJ = 125°C. Exceeding the maximum allowable power dissipation will result in
excessive die temperature.
Thermal Characteristics
Symbol
Parameter
Typical Value
Unit
Junction-to-Ambient Resistance in free air (Note 3)
TO-263-5 (Toplayer plane size : 15mm x 15 mm)
TO-252-5 (Toplayer plane size : 10mm x 10 mm)
SOP-8-P (Toplayer plane size : 10mm x 10 mm)
Junction-to-Case Resistance (Note 4)
28
42
68
oC/W
oC/W
qJA
TO-220-5
3
4
5
qJC
TO-263-5
TO-252-5
Note 3: qJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The sizes of the
rectangular plane, where the devices are mounted, are shown in the table.
Note 4: The case temperature is measured on the TAB of the device mounted on the test board described in Note 3 except the
package TO-220-5. The case temperature of the TO-220-5 is measured on the bottom of the case directly below the die.
Copyright ã ANPEC Electronics Corp.
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Rev. B.5 - Mar., 2008
APL1581
Electrical Characteristics
Unless otherwise noted , these specifications apply over CIN = 10mF, CCNTL = 1mF, COUT = 10mF, and TA = 0 to 70°C.
Typical values refer to TA = 25°C. VOUT = VSENSE
.
APL1581
TYP
UNIT
Symbol
Parameter
Test Conditions
MIN
MAX
Reference Voltage
VCNTL=2.75~5.5V, VIN=2.05~5.5V,
IO =10mA~5A, VADJ=0V
VREF
1.225
1.250
1.275
V
APL1581
Output Voltage
(IO =0~5A for fixed versions)
1.470
1.764
2.450
1.500
1.800
2.500
1.530
1.836
2.550
APL1581-15 VCNTL=3~5.5V , VIN=2.3~5.5V
APL1581-18 VCNTL=3.3~5.5V , VIN=2.6~5.5V
APL1581-25 VCNTL=4~5.5V , VIN=3.3~5.5V
VOUT
V
Line Regulation
(IO =0A for fixed versions)
APL1581 VCNTL=2.75~5.5V, VIN=1.75~5.5V,
IO =10mA, VADJ=0V
REGLINE
3
5
mV
APL1581-15 VCNTL=3~5.5V, VIN=2.3~5.5V
APL1581-18 VCNTL=3.3~5.5V, VIN=2.6~5.5V
APL1581-25 VCNTL=4~5.5V, VIN=3~5.5V
Load Regulation (Note 5
)
(IO =0~5A for fixed versions)
APL1581 VCNTL=2.75V, VIN=2.1V, VADJ =0V,
IO =10mA~5A
REGLOAD
mV
APL1581-15 VCNTL=3V, VIN=2.35V
APL1581-18 VCNTL=3.3V, VIN=2.65V
APL1581-25 VCNTL=4V, VIN=3.35V
Dropout Voltage (Note 6)
IO =5A for all versions
APL1581 VIN=2.05V, VADJ =0V
APL1581-15 VIN=2.3V
VCNTL-VOUT
1.20
0.52
1.35
0.75
V
V
APL1581-18 VIN=2.6V
APL1581-25 VIN=3.3V
Dropout Voltage (Note 6)
IO =5A for all versions
APL1581 VCNTL=2.75V, VADJ =0V
APL1581-15 VCNTL=3V
VIN-VOUT
APL1581-18 VCNTL=3.3V
APL1581-25 VCNTL=4V
ILIMIT
ILMIN
5
A
Current Limit
VCNTL-VOUT=1.5V, VIN-VOUT=0.6V
VCNTL=5V, VIN=3.3V, VADJ =0V
Minimum Load Current
(Note7)
0.8
10
mA
%/W
APL1581
REGTHERMAL
0.01
Thermal Regulation
30ms Pulse
Power Supply Ripple
Rejection
VRIPPLE=1VPP at 120Hz, IO=5A
APL1581 VCNTL=5V, VIN=5V, VADJ =0V
APL1581-15 VCNTL=5.25V, VIN=5.25V
APL1581-18 VCNTL=5.55V, VIN=5.55V
APL1581-25 VCNTL=6.25V, VIN=6.25V
VCNTL-VOUT=1.5V, VIN-VOUT=0.8V,
PSRR
60
70
dB
ICNTL
IGND
IADJ
45
8
120
13
mA
mA
mA
CNTL Pin Current
IO =5A
Ground Pin Current
APL1581-15 VCNTL =3V, VIN =2.3V
APL1581-18 VCNTL =3.3V, VIN =2.6V
APL1581-25 VCNTL =4V, VIN =3.3V
Adjust Pin Current
APL1581 VCNTL=2.75V, VIN=2.05V , VADJ =0V
50
120
Note 5 : Low duty cycle pulse test with Kelvin connections are required to maintain data accuracy .
Note 6 : Dropout voltage is defined as the minimum difference between VIN and VOUT required to maintain 1% VOUT
regulation.
Note 7 : Minimum load current is defined as the minimum current required at the output to maintain VOUT regulation.
Copyright ã ANPEC Electronics Corp.
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Rev. B.5 - Mar., 2008
APL1581
Application Circuit
(1) Adjustable Output VoltageDevice
VIN
+3.3V
VIN
VOUT
APL1581
(Adj.)
VSENSE
ADJ
VOUT
+2.5V/5A
VCNTL
+5V
VCNTL
R1
VREF
120
COUT
CCNTL
CIN
470uF
10uF
100uF
R2
120
GND
GND
* VOUT = VREF ( 1+ R2 / R1 ) + IADJ * R2
where VREF =1.25V (typical)
IADJ=50mA (typical)
* R1 is typically in range of 100W to 125W to satisfy the minimum load current requirement.
(2) Fixed Output VoltageDevice
V
+3.3V
IN
VIN
VOUT
V
OUT
+2.5V/5A
APL1581-25
V
CNTL
VCNTL
VSENSE
+5V
GND
COUT
CCNTL
CIN
470uF
10uF
100uF
GND
GND
(3) With Enable Control Application
V
+3.3V
IN
VIN
VOUT
APL1581
(Adj.)
VSENSE
ADJ
V
OUT
+2.5V/5A
Q1
Q2
V
CNTL
VCNTL
10k
10k
R1
+5V
VREF
120
COUT
CCNTL
CIN
470uF
Enable
GND
10uF
100uF
R2
120
GND
Q1 : APM2301A
Q2 : APM2300A
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Rev. B.5 - Mar., 2008
APL1581
Typical Characteristics
Reference Voltage vs. Junction Temperature
Adjust Pin Current vs. Junction Temperature
80
1.275
1.270
1.265
1.260
1.255
1.250
1.245
1.240
1.235
1.230
1.225
70
60
50
40
30
20
10
0
-50 -25
0
25
50
75
100 125 150
-50 -25
0
25
50
75
100 125 150
JunctionTemperature (°C)
JunctionTemperature (°C)
Minimum Load Current vs. Junction Temperature
VIN-VOUT Dropout Voltage vs. Output Current
700
1.2
TJ=125°C
600
1.0
V
CNTL-VOUT=10.75V
500
0.8
0.6
0.4
0.2
0.0
TJ=25°C
400
V
CNTL-VOUT=1.45V
300
TJ=-50°C
200
100
0
-50
-25
0
25
50
75
100
125
150
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Output Current (A)
JunctionTemperature (°C)
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Rev. B.5 - Mar., 2008
APL1581
Typical Characteristics
Short-Circuit Current vs. Junction Temperature
VCONTROL-VOUT Dropout Voltage vs. Output Current
1.4
14
TJ=-50°C
VIN=5.0V
12
1.3
1.2
1.1
TJ=0°C
10
VIN=3.3V
8
TJ=25°C
1.0
0.9
0.8
0.7
6
4
2
0
TJ=125°C
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
-50
-25
0
25
50
75
100
125
150
JunctionTemperature (°C)
Output Current (A)
Control Pin Current vs. Output Current
Control Pin Current vs. Output Current
VIN-VOUT=0.6V
VIN-VOUT=0.8V
80
160
TJ=-50°C
TJ=0°C
TJ=25°C
TJ=75°C
TJ=125°C
TJ=25°C
70
60
50
40
30
20
10
0
140
120
100
80
60
40
TJ=0°C
TJ=-50°C
TJ=125°C
TJ=75°C
20
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Output Current (A)
Output Current (A)
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Rev. B.5 - Mar., 2008
APL1581
Typical Characteristics
Control Pin Current vs. Output Current
Control Pin Current vs. Output Current
VIN-VOUT=1.0V
VIN-VOUT=4.25V
80
70
TJ=-50°C
70
60
TJ=-50°C
TJ=0°C
TJ=25°C
60
50
40
30
20
10
0
TJ=0°C
TJ=25°C
50
40
30
20
TJ=75°C
TJ=75°C
TJ=125°C
TJ=125°C
10
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Output Current (A)
Output Current (A)
Application Information
General
APL1581 is available in SOP-8P, TO-252-5,
The APL1581 (adjustable or fixed) regulator is a 5 ter-
minal device designed specifically to provide extremely
low dropout voltages comparable to the PNP type with-
out the disadvantage of the extra power dissipation
due to the base current associated with PNP regulators.
This is done by bringing out the control pin of the regu-
lator that provides the base current to the power NPN
and connecting it to a voltage that is greater than the
voltage present at the VIN pin. This flexibility makes
APL1581 ideal for applications where dual inputs are
available, such as a computer motherboard with an
ATX power supply that provides 5V and 3.3V to the
board.
TO-263-5, and TO-220-5 packages to meet different
power dissipation applications.
Output Voltage Setting
See Figure 1 Adjustable APL1581 develops a 1.25V
reference voltage between the VSENSE pin and the
ADJ pin. Placing a resistor between these two termi-
nals causes a constant current to flow through R1 and
down through R2 to set the overall output voltage. In
general, R1 is chosen so that this current is the speci-
fied minimum load current of 10mA.The current out of
the ADJ pin is small, typically 50mA and itadds to the
current from R1. Because IADJ is very small, it needs
to be considered only when very precise output volt-
age setting is required. For best regulation, the top of
the resistor divider should be connected directly to
the SENSE pin. The adjustable APL1581 can be pro-
APL1581 is equipped with a 1.25V reference, preci-
sion and fast voltage regulations, on-chip current and
thermal limits, and remote sensing capability to re-
duce system total cost.
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Rev. B.5 - Mar., 2008
APL1581
Application Information (Cont.)
Output Voltage Setting (Cont.)
regardless of whether they are inside or outside the
regulation loop.
grammable to anyvoltagesin the range of 1.25V to 5.5V
according to the following formula:
VOUT
VIN
VIN
VOUT
R2
APL1581
VOUT = VREF x (1+
) + IADJ x R2
R1
VCNTL
VCNTL
VSENSE
Load
ADJ
R1
R2
where VREF = 1.25V (typical)
Adjustable
Device
IADJ = 50mA (typical)
The recommended R1 is in range of 100W to125W to
satisfy the minimum load current requirement. Proper
sizes of R2 and R1 are also concerned for power
dissipation.
RP
VOUT
V
IN
VIN
VOUT
APL1581
VCNTL VSENSE
V
CNTL
Load
GND
VIN
VIN
VOUT
VOUT
APL1581
Fixed Voltage
Device
VCNTL
VCNTL
VSENSE
ADJ
R1
VRE F
RP
Figure 2 Remote Voltage Sensing
Stability and Output Capacitors
IADJ=50uA
R2
Figure 1 Setting Output Voltage
Grounding and Output Sensing
The circuit design of using the APL1581 series re-
quires an output capacitor as part of the device fre-
quency compensation. The following chart shows a
stable region to select output capacitor for APL1581.
This region above the curve indicates minimum re-
quired ESR and capacitance to maintain stability.
However, the output capacitor should have an ESR
less than1W.
The APL1581 allows true Kelvin sensing for both the
high and low side of the load. Figure 2 shows the de-
vice connected to take advantage of the remote sense
feature. The SENSE pin and the top of the resistor
divider are connected to the top of the load; the bot-
tom of the resistor divider is connected to the bottom
of the load. Typically the load is a microprocessor
and parasitic resistance RPis made up of the PC traces
and /or connector resistance between the regulator
and the processor. RP is now connectedinside the
regulation loop of theAPL1581 and for reasonable val-
ues of RP the load regulation at the load will be
negligible. Voltage drops due to RP are not eliminated;
they will add to the dropout voltage of the regulator
100
80
Stable Region
60
40
20
0
1
10
100
1000
Capacitance(mF)
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Rev. B.5 - Mar., 2008
APL1581
Application Information (Cont.)
Stability and Output Capacitors (Cont.)
exceeded under continuous normal load conditions.
Careful consideration must be given to all sources of
thermal resistance from junction to ambient, includ-
ing junction-to-case, case-to-heat sink interface, and
heat sink resistance itself.
A low-ESR solid tantalum and aluminum electrolytic
capacitor (ESR<1W) works extremelywelland provides
good transient response andstabilityover temperature.
Ultra-low-ESR capacitors, such as ceramic chip
capacitors, may promote unstable or under-damped
transient response, but proper ceramic chip capaci-
tors placed near loads can be used as decoupling
capacitors.
See Figure 3 The SOP-8P is a cost-effective package
featuring a small size as a standard SOP-8 and a
bottom thermal pad to minimize the thermal resistance
of the package, being applicable to high current
applications. The thermal pad is soldered to the top
VOUT plane which may be connected to internal or
bottom VOUT plane by vias to reduce the heat sink
thermal resistance. Therefore, the printed circuit board
(PCB) forms a heat sink and dissipates heat into am-
bient air.
The output capacitors are also used to reduce the slew
rate of load current and help theAPL1581 to minimize
variations of the output voltage, improving transient
response. For this purpose, the low-ESR capacitors
are recommended.
Input Capacitors
The input capacitors of VCNTL and VIN pins are not
required for stability but for supplying surge currents
during large load transients, and this will prevent the
input rail from drooping and improve the performance
of theAPL1581. Because parasitic inductors from volt-
age sources or other bulk capacitors to the VCNTL
and VIN pins will limit the slew rate of the surge cur-
rents during large load transients, resulting in voltage
drop at VIN and VCNTL pins.
Top layer
VOUT plane
for Heat Dissipation
(Larger area is better)
COUT
8
1
7
2
6
3
5
4
Load
Vias
Vias
A capacitor of 1mF (ceramic chip capacitor) or greater
(aluminum electrolytic capacitor) is recommended and
connected near VCNTLpin. For VINpin, an aluminum
electrolytic capacitor (>33mF) is recommended. It is
not necessary to use low-ESR capacitors. More ca-
pacitance reduces the variations of the input voltage
at VIN pin.
Soldering area
(140mil x
110mil)
CIN
CCNTL
for bottom pad
Figure 3 Recommended SOP-8P Layout
Layout and Thermal Consideration
The APL1581 series have internal power and thermal
limiting (TJ=150oC typical) circuitry designed to pro-
tect the device under overload conditions. However,
maximum junction temperature ratings should not be
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Rev. B.5 - Mar., 2008
APL1581
Package Information
TO-220-5
D
Q
b
e
e1
E
L
H1
A
c
J1
F
Millimeters
Inches
Dim
Min.
3.55
0.63
0.35
14.22
1.57
6.68
9.65
1.14
5.84
2.03
13.72
3.53
2.54
Max.
4.83
1.02
0.56
16.51
1.83
6.94
10.67
1.40
6.60
3.05
14.22
4.09
3.43
Min.
Max.
0.190
0.040
0.022
0.650
0.072
0.273
0.420
0.055
0.260
0.120
0.560
0.161
0.135
A
b
0.140
0.025
0.014
0.560
0.062
0.263
0.380
0.045
0.230
0.080
0.540
0.139
0.100
c
D
e
e1
E
F
H1
J1
L
R
Q
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Rev. B.5 - Mar., 2008
APL1581
Package Information
TO-263-5
A
c2
E
E1
b
e
c
SEE VIEW A
GAUGE PLANE
SEATING PLANE
L
VIEW A
TO-263-5
S
Y
M
B
O
L
MILLIMETERS
INCHES
MIN.
MAX.
4.83
0.25
0.99
0.74
MIN.
MAX.
0.190
0.010
0.039
0.029
0.065
0.380
0.354
0.450
0.354
A
4.06
0.160
0.000
0.020
0.015
0.045
0.330
0.236
0.380
0.245
0.00
0.51
0.38
A1
b
c
c2
1.14
8.38
6.00
9.65
6.22
1.65
9.65
9.00
11.43
9.00
D
D1
E
E1
e
1.70 BSC
0.067 BSC
0.575
0.070
0.625
0.110
0.066
8o
14.61
1.78
15.88
2.79
1.68
8o
H
L
L1
0
0o
0o
Note : Follow from JEDEC TO-263 BB.
Copyright ã ANPEC Electronics Corp.
12
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Rev. B.5 - Mar., 2008
APL1581
Packaging Information
TO-252-5
E
A
c2
E1
b3
c
b
e
SEE VIEW A
SEATING PLANE
GAUGE PLANE
L
VIEW A
TO-252-5
S
Y
M
B
O
L
MILLIMETERS
MIN.
INCHES
MAX.
2.39
0.13
0.89
5.46
MIN.
MAX.
0.094
0.005
0.035
0.215
0.024
0.035
0.245
A
2.18
0.086
A1
b
0.020
0.170
0.018
0.018
0.210
0.180
0.250
0.150
0.50
4.32
b3
c
0.46
0.46
5.33
4.57
6.35
3.81
0.61
0.89
6.22
6.00
6.73
c2
D
D1
E
0.236
0.265
E1
e
6.00
0.236
1.27 BSC
0.050 BSC
0.370
0.055
0.035
0.410
0.070
0.080
9.40
1.40
0.89
10.41
1.78
H
L
L3
0
2.03
8
8
0
0
Copyright ã ANPEC Electronics Corp.
13
www.anpec.com.tw
Rev. B.5 - Mar., 2008
APL1581
Packaging Information
SOP-8-P
D
SEE VIEW
A
D1
THERMAL
PAD
e
b
c
GAUGE PLANE
SEATING PLANE
L
VIEW A
SOP-8P
S
Y
M
B
O
L
MILLIMETERS
INCHES
MIN.
MAX.
1.60
MIN.
MAX.
0.063
0.006
A
0.000
0.049
0.012
0.007
0.15
A1
A2
b
0.00
1.25
0.31
0.17
0.020
0.010
0.51
0.25
c
D
0.189
0.098
0.197
0.138
4.80
2.25
5.80
3.80
2.00
5.00
3.50
6.20
4.00
3.00
D1
E
0.228
0.150
0.079
0.244
0.157
0.118
E1
E2
e
1.27 BSC
0.050 BSC
0.010
0.016
0o
0.020
0.050
8o
0.25
0.40
0o
0.50
1.27
8o
h
L
0
Note : 1. Follow JEDEC MS-012 BA.
2. Dimension "D" does not include mold flash, protrusions
or gate burrs. Mold flash, protrusion or gate burrs shall not
exceed 6 mil per side .
3. Dimension "E" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
Copyright ã ANPEC Electronics Corp.
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www.anpec.com.tw
Rev. B.5 - Mar., 2008
APL1581
Carrier Tape & Reel Dimensions
P0
P2
P1
OD0
A
K0
A0
A
OD1
B
B
SECTION A-A
SECTION B-B
d
T1
Application
TO-263-5
A
H
T1
C
d
D
W
E1
F
24.4+2.00 13.0+0.50
-0.00 -0.20
381.0±2.00 60 MIN.
P0 P1
1.5 MIN. 20.2 MIN. 24.0±0.30 1.75±0.10 11.5±0.10
P2 D0
D1
T
A0
10.8±0.20 16.1±0.20 5.2±0.20
E1
B0
K0
1.5+0.10
-0.00
0.6+0.00
-0.40
4.0±0.10 16.0±0.10 2.0±0.10
T1
1.5 MIN.
Application
TO-252-5
A
H
C
d
D
W
F
16.4+2.00 13.0+0.50
330.0±2.00 50 MIN.
P0 P1
4.0±0.10 8.0±0.10
1.5 MIN. 20.2 MIN. 16.0±0.30 1.75±0.10 7.50±0.05
-0.00
P2
-0.20
D0
1.5+0.10
-0.00
D1
1.5 MIN.
d
T
A0
6.80±0.20
W
B0
10.40±
0.20
K0
2.50±0.20
F
0.6+0.00
-0.40
2.0±0.05
Application
SOP-8-P
A
H
T1
C
D
E1
12.4+2.00 13.0+0.50
330.0±2.00 50 MIN.
P0 P1
4.0±0.10 8.0±0.10
1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05
-0.00
P2
2.0±0.05
-0.20
D0
D1
T
A0
B0
K0
1.5+0.10
-0.00
0.6+0.00
-0.40
1.5 MIN.
6.40±0.20 5.20±0.20 2.10±0.20
(mm)
Copyright ã ANPEC Electronics Corp.
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www.anpec.com.tw
Rev. B.5 - Mar., 2008
APL1581
Devices Per Unit
Package Type
TO-252-5
Unit
Quantity
2500
Tape & Reel
Tape & Reel
Tape & Reel
TO-263-5
1000
SOP-8-P
2500
Reflow Condition (IR/Convection or VPR Reflow)
tp
TP
Critical Zone
TL to TP
Ramp-up
TL
tL
Tsmax
Tsmin
Ramp-down
ts
Preheat
25
°
t 25 C to Peak
Time
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TST
ESD
Method
MIL-STD-883D-2003
MIL-STD-883D-1005.7
JESD-22-B, A102
MIL-STD-883D-1011.9
MIL-STD-883D-3015.7
JESD 78
Description
245°C, 5 sec
1000 Hrs Bias @125°C
168 Hrs, 100%RH, 121°C
-65°C~150°C, 200 Cycles
VHBM > 2KV, VMM > 200V
10ms, 1tr > 100mA
Latch-Up
Copyright ã ANPEC Electronics Corp.
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Rev. B.5 - Mar., 2008
APL1581
Classification Reflow Profiles
Profile Feature
Average ramp-up rate
(TL to TP)
Sn-Pb Eutectic Assembly
Pb-Free Assembly
3°C/second max.
3°C/second max.
Preheat
100°C
150°C
60-120 seconds
150°C
200°C
60-180 seconds
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (min to max) (ts)
Time maintained above:
- Temperature (TL)
183°C
60-150 seconds
217°C
60-150 seconds
- Time (tL)
Peak/Classification Temperature (Tp)
See table 1
See table 2
Time within 5°C of actual
Peak Temperature (tp)
10-30 seconds
20-40 seconds
Ramp-down Rate
6°C/second max.
6°C/second max.
6 minutes max.
8 minutes max.
Time 25°C to Peak Temperature
Note: All temperatures refer to topside of the package. Measured on the body surface.
Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures
Volume mm3
350
Volume mm3
Package Thickness
<350
<2.5 mm
³ 2.5 mm
240 +0/-5°C
225 +0/-5°C
225 +0/-5°C
225 +0/-5°C
Table 2. Pb-free Process – Package Classification Reflow Temperatures
Volume mm3
<350
Volume mm3
Volume mm3
>2000
Package Thickness
350-2000
<1.6 mm
1.6 mm – 2.5 mm
³ 2.5 mm
260 +0°C*
260 +0°C*
250 +0°C*
260 +0°C*
250 +0°C*
245 +0°C*
260 +0°C*
245 +0°C*
245 +0°C*
* Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated
classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL
level.
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright ã ANPEC Electronics Corp.
17
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Rev. B.5 - Mar., 2008
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