APL3205BQBI-TRG [ANPEC]
Li+ Charger Protection IC; Li +电池充电器保护IC
| 型号： | APL3205BQBI-TRG |
| 厂家： | 
ANPEC ELECTRONICS COROPRATION |
| 描述： | Li+ Charger Protection IC |
| 文件： | 总20页 (文件大小：465K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APL3205A/B
Li+ Charger Protection IC
Features
General Description
·
·
·
Input Over-Voltage Protection
The APL3205A/B provide completed Li+ charger protec-
tions against over-voltage, over-current, and battery over-
voltage. The IC is designed to monitor input voltage, in-
put current, and battery voltage. When any of the moni-
tored parameters are over the threshold, the IC removes
the power from the charging system by turning off an in-
ternal switch. All protections also have deglitch time
against false triggering due to voltage spikes or current
transients. The APL3205A/B also provide over-tempera-
ture protection, a FAULT output pin to indicate the fault
conditions, and the EN pin to allow the system to disable
the IC.
Programmable Input Over-Current Protection
Battery Over-Voltage Protection
·
·
Over-Temperature Protection
High Immunityof False Triggering
·
·
·
·
·
High Accuracy Protection Thresholds
Fault Status Indication
EnableInput
Available in TDFN2x2-8 Package
Lead Free and Green Devices Available
(RoHS Compliant)
Pin Configuration
Applications
·
·
·
Smart Phones and PDAs
Digital Still Cameras
Portable Devices
IN 1
GND 2
8 OUT
7 ILIM
6 BAT
5 EN
PSW 3
FAULT 4
TDFN2x2-8 (Top View)
Simplified Application Circuit
5V Adapter or USB
Charger Input
IN
OUT
APL3205A/B
EN
FAULT
PSW
Charger Output
and System
ILIM
BAT
GND
Li+
Battery
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright ã ANPEC Electronics Corp.
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Rev. A.2 - May., 2009
APL3205A/B
Ordering and Marking Information
Package Code
APL3205A
QB : TDFN2x2-8
APL3205B
Operating Ambient Temperature Range
Assembly Material
I : -40 to 85 oC
Handling Code
Handling Code
Temperature Range
Package Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
L05A
X
APL3205A QB:
X - Date Code
X - Date Code
L05B
X
APL3205B QB:
Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish;
which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-
020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and
halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed
1500ppm by weight).
Absolute Maximum Ratings (Note 1)
Symbol
Parameter
Rating
-0.3 to 30
-0.3 to 7
Unit
V
VIN
IN Input Voltage (IN pin to GND)
VOUT, VBAT
OUT, BAT Pins to GND Voltage
V
VILIM, VFAULT, VEN , VPSW
-0.3 to 7
V
ILIM, FAULT, EN, PSW, Pins to GND Voltage
OUT Output Current
IOUT
TJ
2
150
A
Maximum Junction Temperature
Storage Temperature Range
oC
oC
oC
TSTG
TSDR
-65 to 150
260
Maximum Lead Soldering Temperature,10 Seconds
Note 1 : Stresses beyond the absolute maximum rating may damage the device and exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Thermal Characteristics
Symbol
Parameter
Typical Value
Unit
Junction to Ambient Thermal Resistance in Free Air
80
qJA
°C/W
TDFN2x2-8
Recommended Operating Conditions
Symbol
Parameter
Range
4.5 to 5.5
0 to 1.5
Unit
V
VIN
IN Input Voltage
IOUT
TJ
OUT Output Current
Junction Temperature
Ambient Temperature
A
-40 to 125
-40 to 85
°C
°C
TA
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Rev. A.2 - May., 2009
APL3205A/B
Electrical Characteristics
,
Refer to the typical application circuit. These specifications apply over VIN=5V, TA= -40~85°C unless otherwise specified. Typical
values are at TA=25°C.
APL3205A/B
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
POWER-ON-RESET (POR) AND SUPPLY CURRENT
IN POR Threshold
IN POR Hysteresis
2.5
-
2.8
-
V
VPOR
VIN rising
-
-
-
-
230
250
100
8
mV
EN = Low
350
150
-
IN Supply Current
ICC
mA
EN = High
Input Power-On Blanking Time
ms
TB(IN)
VIN rising to VOUT rising
INTERNAL POWER SWITCH AND OUT DISCHARGE RESISTANCE
Power Switch On Resistance
OUT Discharge Resistance
-
-
250
500
450
-
IOUT = 0.5A
VOUT = 3V
mW
W
INPUT OVER-VOLTAGE PROTECTION (OVP)
5.67
5.85
6.80
200
-
6.00
APL3205A, VIN rising
APL3205B, VIN rising
Input OVP Threshold
V
VOVP
6.60
7.00
Input OVP Recovery Hysteresis
Input OVP Propagation Delay
Input OVP Recovery Time
-
-
-
-
1
-
mV
ms
8
ms
TON(OVP)
OVER-CURRENT PROTECTION (OCP)
OCP Threshold
930
1000
-
1200
mA
%
IOCP
RILIM = 25kW
OCP Threshold Accuracy
OCP Blanking Time
OCP Recovery Time
-10
+10
IOCP = 300mA to 1500mA
-
-
176
64
-
-
TB(OCP)
ms
ms
TON(OCP)
BATTERY OVER-VOLTAGE PROTECTION
Battery OVP Threshold
Battery OVP Hysteresis
BAT Pin Leakage Current
Battery OVP Blanking Time
4.30
4.35
270
-
4.4
-
V
VBOVP
VBAT rising
-
-
-
mV
nA
ms
20
-
IBAT
VBAT = 4.4V
176
TB(BOVP)
EN LOGIC LEVELS
EN Input Logic High
1.4
-
-
-
0.4
-
V
V
EN Input Logic Low
EN Internal Pull-Low Resistor
-
-
500
kW
FAULT LOGIC LEVELS AND DELAY TIME
FAULT Output Low Voltage
-
-
V
Sink 5mA current
VFAULT = 5V
-
-
0.4
1
FAULT Pin Leakage Current
mA
OVER-TEMPERATURE PROTECTION (OTP)
Over-Temperature Threshold
Over-Temperature Hysteresis
-
-
140
20
-
-
TOTP
°C
°C
PSW LOGIC LEVELS
PSW Output Low Threshold
100
50
mV
mV
VIN rising, VOUT - VBAT
VIN falling, VOUT - VBAT
50
20
150
80
PSW Output High Threshold
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Rev. A.2 - May., 2009
APL3205A/B
Electrical Characteristics (Cont.)
,
Refer to the typical application circuit. These specifications apply over VIN=5V, TA= -40~85°C unless otherwise specified. Typical
values are at TA=25°C.
APL3205A/B
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
PSW LOGIC LEVELS (CONT.)
PSW Source Current
2.5
5
mA
mA
ms
VPSW = 2.5V
-
-
-
-
-
-
PSW Sink Current
VPSW = 2.5V
1
TD(PSW)
PSW Low Delay Time
VIN rising, VOUT - VBAT
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Rev. A.2 - May., 2009
APL3205A/B
Typical Operating Characteristics
Input OVP Threshold vs. Junction
Temperature
Input OVP Threshold vs. Junction
Temperature
6.00
7.00
6.95
6.90
6.85
6.80
6.75
6.70
6.65
6.60
6.55
6.50
APL3205A
APL3205B
5.95
5.90
VIN Increasing
5.85
VIN Increasing
5.80
5.75
5.70
VIN Decreasing
VIN Decreasing
5.65
5.60
5.55
-50
-25
0
25
50
75
100 125
-50
-50
-50
-25
0
25
50
75
100 125
Junction Temperature (oC)
Junction Temperature (oC)
Battery OVP Threshold vs.
Junction Temperature
OCP Threshold vs. Junction
Temperature
4.40
4.35
4.30
4.25
4.20
4.15
4.10
4.05
4.00
1200
1150
1100
1050
1000
950
VBAT Increasing
900
VBAT Decreasing
850
800
-50
-25
0
25
50
75
100 125
-25
0
25
50
75
100 125
Junction Temperature (oC)
Junction Temperature (oC)
IN Supply Current vs. Junction
Temperature
POR Threshold vs. Junction
Temperature
2.80
2.70
2.60
2.50
2.40
2.30
2.20
150
125
100
75
VIN Increasing
EN = high
VIN Decreasing
50
-25
0
25
50
75
100 125
-50
-25
0
25
50
75
100 125
Junction Temperature (oC)
Junction Temperature (oC)
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Rev. A.2 - May., 2009
APL3205A/B
Typical Operating Characteristics (Cont.)
Power Switch On Resistance vs.
Input Voltage
Power Switch On Resistance vs.
Junction Temperature
0.35
0.30
0.25
0.20
0.15
0.10
400
350
300
250
200
150
-50
-25
0
25
50
75
100 125
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
Junction Temperature (oC)
Input Voltage, VIN (V)
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Rev. A.2 - May., 2009
APL3205A/B
Operating Waveforms
Refer to the typical application circuit. The test condition is VIN=5V, TA= 25oC unless otherwise specified.
OVP at Power On
Normal Power On
VIN = 0 to 12V
VIN
VIN = 0 to 5V
VIN
1
VOUT
1
2
3
VOUT
2
3
IOUT
VFAULT
COUT =1mF, CIN =1mF, ROUT = 10W
CH1: VIN, 10V/Div, DC
CH2: VOUT, 2V/Div, DC
CH3: VFAULT, 5V/Div, DC
TIME: 2ms/Div
COUT =1mF, CIN =1mF, ROUT = 10W
CH1: VIN, 5V/Div, DC
CH2: VOUT, 2V/Div, DC
CH3: IOUT, 0.5A/Div, DC
TIME: 2ms/Div
Input Over-Voltage Protection
Input Over-Voltage Protection
APL3205A
APL3205B
VIN
VIN
1
1
VOUT
VOUT
3
2
3
2
VFAULT
VFAULT
COUT = 1mF, CIN=1mF, ROUT=50W
COUT= 1mF, CIN=1mF, ROUT=50W
CH1: VIN, 5V/Div, AC
CH2: VOUT, 2V/Div, DC
CH3: VFAULT, 5V/Div, DC
CH1: VIN, 5V/Div, AC
CH2: VOUT, 2V/Div, DC
CH3: VFAULT, 5V/Div, DC
TIME:20m
s/Div
TIME:20m
s/Div
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Rev. A.2 - May., 2009
APL3205A/B
Operating Waveforms (Cont.)
Refer to the typical application circuit. The test condition is VIN=5V, TA= 25oC unless otherwise specified.
Recovery from Input OVP
Battery Over-Voltage Protection
APL3205B
VBAT
VIN
1
1
2
3
VOUT
VOUT
2
3
VFAULT
VFAULT
VBAT = 3.6V to 4.4V to 3.6V, ROUT=33.3W
VIN = 12V to 5V
=1m
F, CIN =1mF
COUT
COUT = 1mF, CIN=1mF, ROUT=50W
CH1: VIN, 5V/Div, AC
CH2: VOUT, 5V/Div, DC
CH3: VFAULT, 5V/Div, DC
TIME: 2ms/Div
CH1: VBAT, 2V/Div, DC
CH2: VOUT, 2V/Div, DC
CH3: VFAULT, 5V/Div, DC
TIME: 5ms/Div
Recovery from Battery OVP
Battery Over-Voltage Protection
VBAT
VBAT
1
VOUT
1
2
3
VOUT
2
3
VFAULT
VFAULT
VBAT = 4.4V to 3.6V, ROUT=33.3W
COUT =1mF, CIN =1mF
CH1: VBAT, 2V/Div, DC
CH2: VOUT, 2V/Div, DC
CH3: VFAULT, 5V/Div, DC
TIME: 50ms/Div
VBAT = 3.6V to 4.4V, ROUT=33.3W
COUT=1mF, CIN =1mF
CH1: VBAT, 2V/Div, DC
CH2: VOUT, 2V/Div, DC
CH3: VFAULT, 5V/Div, DC
TIME: 50m
s/Div
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Rev. A.2 - May., 2009
APL3205A/B
Operating Waveforms (Cont.)
Refer to the typical application circuit. The test condition is VIN=5V, TA= 25oC unless otherwise specified.
Over-Current Protection
Over-Current Protection
VIN
IOUT
1
1
2
VOUT
VOUT
2
3
IOUT
3
4
VFAULT
VFAULT
COUT =1mF, CIN =1mF, IOUT = 0.5A to 1.2A
CH1: IOUT, 0.5A/Div, DC
CH2: VOUT, 2V/Div, DC
CH3: VFAULT, 5V/Div, DC
TIME: 50ms/Div
COUT=1mF, CIN=1mF, ROUT= 2.5W
CH1: VIN, 5V/Div, DC
CH2: VOUT, 5V/Div, DC
CH3: IOUT, 0.5A/Div, DC
CH4: VFAULT, 5V/Div, DC
TIME: 200ms/Div
PSW Output Timing
PSW Output Timing
VIN = 5V to 0V
VBAT = 3.8V
VIN = 0V to 5V
VBAT = 3.8V
VOUT
VOUT
VBAT
VBAT
VPSW
VPSW
1,2,3
1,2,3
COUT =1mF, CIN =1mF
CH1: VBAT, 1V/Div, DC
CH2: VOUT, 1V/Div, DC
CH3: VPSW, 2V/Div, DC
TIME: 200ms/Div
COUT =1mF, CIN =1mF
CH1: VBAT, 1V/Div, DC
CH2: VOUT, 1V/Div, DC
CH3: VPSW, 2V/Div, DC
TIME: 5m s/Div
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Rev. A.2 - May., 2009
APL3205A/B
Pin Description
PIN
FUNCTION
NO.
NAME
1
IN
Power Supply Input.
Ground.
2
3
GND
PSW
PSW is an active high output that drives the external PMOS (see Application Circuit).
Fault Indication Pin. This pin goes low when input OVP, OCP, or battery OVP is detected.
Enable Input. Pull this pin to high to disable the device and pull this pin to low to enable device.
4
5
FAULT
EN
6
7
8
-
BAT
Battery OVP Sense Pin. Connect to positive terminal of battery through a resistor.
Over-current Protection Setting Pin. Connect a resistor to the GND to set the over-current threshold.
Output Voltage Pin. The output voltage follows the input voltage when no fault is detected.
Exposed Thermal Pad. Must be electrically connected to the GND pin.
ILIM
OUT
EP
Block Diagram
IN
OUT
ILIM
POR
Charge
Pump
1.2V
1V
Gate Driver and
Control Logic
0.5V
BAT
FAULT
PSW
OTP
VOUT
VBAT +0.1V
EN
GND
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Rev. A.2 - May., 2009
APL3205A/B
Typical Application Circuit
5V Adapter/
USB
1
8
CHRIN
IN
OUT
1mF
1uF
GTDRV
APL3205A/B
50K
5
4
EN
MTK PMU
3
6
GPIO
VIO
50K
50K
PSW
BAT
FAULT
MCU
APM2805QA
200K
ISENS
25K
0.2
7
ILIM
GND
VBAT
Li+
Battery
2
Figure 1. The Typical Protection Circuit for Charger Systems.
5V Adapter/
USB
8
1
IN
OUT
CHRIN
1mF
1uF
APL3205A/B
GTDRV
50K
5
4
EN
3
6
MTK PMU
GPIO
VIO
50K
50K
PSW
BAT
FAULT
MCU
ISENS
APM2103QA
200K
25K
7
0.2
ILIM
GND
VBAT
Li+
Battery
2
Figure 2. Use the PSW pin to drive an external P-Channel MOSFET T for Charger Systems.
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APL3205A/B
Function Description
Power-Up
The APL3205A/B have a built-in power-on-reset circuit to
keep the output shuting off until internal circuitry is oper-
ating properly. The POR circuit has hysteresis and a de-
glitch feature, therefore, it will typically ignore undershoot
transients on the input. When input voltage exceeds the
POR threshold and after 8ms blanking time, the output
voltage starts a soft-start to reduce the inrush current.
the internal power FET is turned off. When the BP voltage
returns below the battery OVP threshold minus the
hysteresis, the FET is turned on again. The APL3205A/B
have a built-in counter. When the total count of battery
OVP fault reaches 16, the FET is turned off permanently,
requiring either a VIN POR or EN re-enable again to restart.
Over-Temperature Protection
When the junction temperature exceeds 140oC, the inter-
nal thermal sense circuit turns off the power FET and
allows the device to cool down. When the device’s junc-
tion temperature cools by 20oC, the internal thermal sense
circuit will enable the device, resulting in a pulsed output
during continuous thermal protection. Thermal protec-
tion is designed to protect the IC in the event of over tem-
perature conditions. For normal operation, the junction
temperature cannot exceed TJ=+125 oC.
Input Over-Voltage Protection (OVP)
The input voltage is monitored by the internal OVP circuit.
When the input voltage rises above the input OVP
threshold, the internal FET will be turned off within 1ms to
protect connected system on OUT pin. When the input
voltage returns below the input OVP threshold minus the
hysteresis, the FET is turned on again after 8ms recovery
time. The input OVP circuit has a 200mV hysteresis and
a recovery time of TON(OVP) to provide noise immunity
against transient conditions.
FAULTOutput
Over-Current Protection (OCP)
The APL3205A/B provide an open-drain output to indi-
cate that a fault has occurred. When any of input OVP,
OCP, battery OVP, is detected, the FAULT goes low to
indicate that a fault has occurred. Since the FAULT pin is
an open-drain output, connecting a resistor to a pull high
voltage is necessary.
The output current is monitored by the internal OCP circuit.
When the output current reaches the OCP threshold, the
device limits the output current at OCP threshold level. If
the OCP condition continues for a blanking time of TB(OCP)
,
the internal power FET is turned off. After the recovery
time of TON(OCP), the FET will be turned on again and the
output current is monitored again. The APL3205A/B have
a built-in counter. When the total count of OCP fault
reaches 16, the FET is turned off permanently, requiring
either a VIN POR or EN re-enable again to restart. The
OCP threshold is programmed by a resistor RILIM con-
nected from ILIM pin to the GND. The OCP threshold is
calculated by the following equation:
Enable/Shutdown
Pulling the EN pin voltage above 1.4V disables the de-
vice and pulling EN pin voltage below 0.4V enables the
device. The EN pin has an internal pull-down resistor
and can be left floating. When the IC is latched off due to
the total count of OCP or battery OVP reaches 16, disable
and re-enable the device with the EN pin can clear the
counter.
KILIM
IOCP =
RILIM
PSW Output
where
The APL3205A/B provide an active high output to drive the
external P-channel MOSFET. When VOUT > VBAT + 100mV,
the PSW pin is pulled low, and turns on the external P-
KILIM=25000AW
Battery Over-Voltage-Protection
channel MOSFET for battery charge. When VOUT < VBAT
+
50mV, the PSW pin is pulled high, and turns off the exter-
nal P-channel MOSFET, which prevents the battery volt-
age from supplying to OUT pin and IN pin (see Applica-
tion Circuit).
The APL3205A/B monitor the BAT pin voltage for battery
over-voltage protection. The battery OVP threshold is in-
ternally set to 4.35V. When the BAT pin voltage exceeds
the battery OVP threshold for a blanking time of TB(BOVP)
,
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Rev. A.2 - May., 2009
APL3205A/B
Function Description (Cont.)
VOVP
VPOR
VIN
VOUT
VFAULT
TB(IN)
TON(OVP)
Figure3. OVP Timing Chart
VOUT
OCP
Threshold
Count 13
times
IOUT
VFAULT
Total count 16
times IC is
latched off
TB(OCP)
TON(OCP)
TB(OCP)
TB(OCP)
Figure 4. OCP Timing Chart
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Rev. A.2 - May., 2009
APL3205A/B
Function Description (Cont.)
VBOVP
VBOVP
VBAT
VBOVP
Count 13
times
VOUT
VFAULT
Total count 16
times IC is
TB(BOVP)
TB(BOVP)
TB(BOVP)
latched off
Figure 5. Battery OVP Timing Chart
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Rev. A.2 - May., 2009
APL3205A/B
Application Information
RBAT Selection
RUP
FAULT
Connect the BAT pin to the positive terminal of battery
through a resistor RBAT for battery OVP function. The RBAT
limits the current flowing from BAT to battery in case of
BAT pin is shortened to VIN pin under a failure mode. The
recommended value of RBAT is 100kW. In the worse case
of an IC failure, the current flowing from the BAT pin to the
battery is:
VIO
RFAULT
GPIO
GPIO
REN
MCU
EN
RBAT
BAT
(30V-3V)/ 100kW =270mA
where the 30V is the maximum IN voltage and the 3V is
the minimum battery voltage. The current is so small that
can be absorbed by the charger system.
Li+ Battery
Figure 6. RUP, RFAULT, REN and RBAT
The disadvantage with the large RBAT is that the error of
the battery OVP threshold will be increased. The addi-
tional error is the voltage drop across the RBAT because
of the BAT bias current. When RBAT is 100kW, the worse-
case additional error is 100kWx20nA=2mV, which is ac-
ceptable in most applications.
Capacitor Selection
The input capacitor is for decoupling and prevents the
input voltage from overshooting to dangerous levels. In
the AC adapter hot plug-in applications or load current
step-down transient, the input voltage has a transient
spike due to the parasitic inductance of the input cable. A
25V, X5R, dielectric ceramic capacitor with a value be-
tween 1mF and 4.7mF placed close to the IN pin is
recommended.
REN Selection
For the same reason as the BAT pin case, the EN pin
should be connected to the MCU GPIO pin through a
resistor. The value of the REN is dependent on the IO
voltage of the MCU.
The output capacitor is for output voltage decoupling, and
also can be as the input capacitor of the charging circuit.
At least, a 1mF, 10V, X5R capacitor is recommended.
Since the IO voltage is divided by REN and EN internal pull
low resistor for EN voltage. It has to be ensured that the
EN voltage is above the EN logic high voltage when the
GPIO output of the MCU is high.
Layout Consideration
In some failure modes, a high voltage may be applied to
the device. Make sure that the clearance constraint of the
PCB layout must satisfy the design rule for high voltage.
The exposed pad of the TDFN2x2-8 performs the func-
tion of channeling heat away. It is recommended that
connect the exposed pad to a large copper ground plane
on the backside of the circuit board through several ther-
mal vias to improve heat dissipation.
FAULTOutput
Since the FAULT pin is an open-drain output, connecting
a resistor RUP to a pull high voltage is necessary. It is also
recommended that connect the FAULT to the MCU GPIO
through a resistor RFAULT. The RFAULT prevents damage to
the MCU under a failure mode. The recommended value
of the resistors should be between 10kW and 100kW.
The input and output capacitors should be placed close
to the IC. RILIM also should be placed close to the IC.
The high current traces like input trace and output trace
must be wide and short.
Copyright ã ANPEC Electronics Corp.
15
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Rev. A.2 - May., 2009
APL3205A/B
Package Information
TDFN2x2-8
A
D
D2
A1
A3
Pin 1 Corner
e
S
Y
TDFN2x2-8
M
B
O
MILLIMETERS
INCHES
MIN.
MAX.
MIN.
MAX.
0.031
0.002
L
A
0.70
0.00
0.80
0.05
0.028
0.000
A1
A3
b
0.20 REF
0.008 REF
0.007
0.075
0.039
0.075
0.024
0.012
0.083
0.063
0.083
0.039
0.18
1.90
0.30
2.10
D
D2
E
1.00
1.90
0.60
1.60
2.10
E2
e
1.00
0.50 BSC
0.020 BSC
0.012
0.018
L
0.30
0.45
Note : 1. Follow from JEDEC MO-229 WCCD-3.
Copyright ã ANPEC Electronics Corp.
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www.anpec.com.tw
Rev. A.2 - May., 2009
APL3205A/B
Carrier Tape & Reel Dimensions
P0
P2
P1
OD0
A
K0
A0
A
OD1
B
B
SECTION A-A
SECTION B-B
d
T1
Application
TDFN2x2-8
A
H
T1
8.4+2.00 13.0+0.50
-0.00 -0.20
P2 D0
C
d
D
W
E1
F
3.50±0.05
K0
178.0±2.00 50 MIN.
1.5 MIN.
D1
20.2 MIN.
8.0±0.20 1.75±0.10
P0
P1
T
A0
B0
1.5+0.10
-0.00
0.6+0.00
-0.4
4.0±0.10
4.0±0.10
2.0±0.05
1.5 MIN.
3.35 MIN
3.35 MIN 1.30±0.20
(mm)
Devices Per Unit
Package Type
Unit
Tape & Reel
Quantity
TDFN2x2-8
3000
Copyright ã ANPEC Electronics Corp.
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Rev. A.2 - May., 2009
APL3205A/B
Taping Direction Information
TDFN2x2-8
USER DIRECTION OF FEED
Classification Profile
Copyright ã ANPEC Electronics Corp.
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www.anpec.com.tw
Rev. A.2 - May., 2009
APL3205A/B
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
Preheat & Soak
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
Temperature min (Tsmin
)
Temperature max (Tsmax
)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
3 °C/second max.
3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL)
183 °C
60-150 seconds
217 °C
60-150 seconds
Peak package body Temperature
(Tp)*
See Classification Temp in table 1
20** seconds
See Classification Temp in table 2
30** seconds
Time (tP)** within 5°C of the specified
classification temperature (Tc)
Average ramp-down rate (Tp to Tsmax
)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Volume mm3
350
Package
Thickness
<2.5 mm
³ 2.5 mm
Volume mm3
<350
235 °C
220 °C
220 °C
220 °C
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
Volume mm3
Volume mm3
350-2000
260 °C
Volume mm3
<350
260 °C
260 °C
250 °C
>2000
260 °C
245 °C
245 °C
1.6 mm – 2.5 mm
³ 2.5 mm
250 °C
245 °C
Reliability Test Program
Test item
SOLDERABILITY
HOLT
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
Description
5 Sec, 245°C
1000 Hrs, Bias @ 125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV, VMM≧200V
10ms, 1tr≧100mA
PCT
TCT
ESD
Latch-Up
MIL-STD-883-3015.7
JESD 78
Copyright ã ANPEC Electronics Corp.
19
www.anpec.com.tw
Rev. A.2 - May., 2009
APL3205A/B
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright ã ANPEC Electronics Corp.
Rev. A.2 - May., 2009
20
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