APL78L05-EC-TU [ANPEC]
Three-Terminal Low Current Positive Voltage Regulator; 三端低电流正电压稳压器
| 型号： | APL78L05-EC-TU |
| 厂家： | 
ANPEC ELECTRONICS COROPRATION |
| 描述： | Three-Terminal Low Current Positive Voltage Regulator |
| 文件： | 总14页 (文件大小：146K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APL78L05/12
Three-Terminal Low Current Positive Voltage Regulator
Features
General Description
This series of fixed-voltage monolithic integrated-cir-
cuit voltage regulators is designed for a wide range
of applications. These applications include on-card
regulation for elimination of noise and distribution
problems associated with single-point regulation. In
addition, they can be used with power-pass elements
to make high-current voltage regulators. Each of
•
•
•
•
•
•
•
•
•
3-Ternimal Regulators
Maximum Input Voltage : 30V
Output Voltages of 5V,12V
Output Current Up to 100mA
No External Components
Internal Thermal Overload Protection
Internal Short-Circuit Limiting
these regulators can deliver up to 100mA of output
current. The internal limiting and ternal shutdown fea-
tures of these regulators make them essentially im-
mune to overload. When used as a replacement for
a Zener diode-resistor combination, an effective im-
provement in output impedance can be obtained to-
gether with lower-bias current.
Output Voltage Offered in 4% tolerance
SOP-8, SOT-89 and TO-92 Packages.
Applications
Pin Description
•
•
Battery-Powered Circuitry
1
2
3
4
8
7
6
5
V
OUT
V
IN
3
2
1
IN
V
Post Regulator for Switching Power Supply
GND
GND
NC
GND
GND
NC
GND
OUT
V
TO-92 (Top View)
SOP-8 (Top View)
1
2
3
OUT
V
IN
V
GND
Ordering and Marking Information
SOT-89 (Front View)
P a c k a g e C o d e
: T O -9 2
T e m p . R a n g e
A P L 7 8 L 0 5 /1 2 -
E
K
: S O P -8
D : S O T -8 9
L e a d F re e C o d e
H a n d lin g C o d e
T e m p . R a n g e
P a c k a g e C o d e
°
C
C
: 0 to 7 0
H a n d lin g C o d e
T U : T u b e
T R : T a p e
B o x
L e a d F re e C o d e
&
R e e l
P B : P la s tic B a g
T B : T a p e
&
L
: L e a d F re e D e v ic e
B la n k : O rig in a l D e v ic e
A P L
A P L 7 8 L 0 5 /1 2
X X X X X
7 8 L 0 5 /1 2
X X X X X
A P L 7 8 L 0 5 /1 2
E
:
X X X X X
- D a te C o d e
A P L 7 8 L 0 5 /1 2 D /K
:
X X X X X
- D a te C o d e
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to
obtain the latest version of relevant information to verify before placing orders.
Copyright ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
1
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APL78L05/12
Absolute Maximum Ratings
Symbol
Parameter
Rating
Unit
VIN
TJ
Input Voltage
30
VDC
Operating Junction Temperature Range
Control Section
°C
0 to 125
0 to 150
Power Transistor
TSTG
Storage Temperature Range
-65 to +150
°C
Thermal Resistance from Junction to Ambient in Free Air
θJA
SOP-8
SOT-89/TO-92
160
180
°C/W
Electrical Characteristics
VIN=10V, IOUT=40mA, TJ=25°C, CIN=0.33µF, COUT=0.1µF, unless otherwise specified
APL78L05
Typ.
Symbol
Parameter
Output Voltage
Test Condition
Unit
Min.
Max.
VO
4.8
5.0
5.2
Vdc
Vdc
1.0mA≤IOUT≤40mA
7.0Vdc≤VIN≤20Vdc
VO
Output Voltage (0° to +125°C)
4.75
5
5.25
VIN=10V, 1.0mA≤IOUT≤40mA
7.0Vdc≤VIN≤20Vdc
8.0Vdc≤VIN≤20Vdc
1.0mA≤IOUT≤100mA
1.0mA≤IOUT≤40mA
29
26
9
150
100
60
Regline Line Regulation
Regload Load Regulation
mV
mV
mA
mA
Vdc
5
30
IB
Quiescent Current
2.8
6.0
0.15
0.08
1.9
1.5
0.1
8.0Vdc≤VIN≤20Vdc
1.0mA≤IOUT≤40mA
IOUT=100mA
Quiescent Current Change
∆ IB
VIN-VO Dropout Voltage
APL78L12
Typ.
Symbol
Parameter
Test Condition
Unit
Min.
Max.
VO
Output Voltage
11.5
12
12.5
Vdc
1.0mA≤IOUT≤40mA
VO
Output Voltage (0° to +125°C)
11.4
12
12.6
Vdc
14Vdc≤VIN≤27Vdc
VIN=19V, 1.0mA≤IOUT≤40mA
Regline Line Regulation
Regload Load Regulation
250
100
50
mV
mV
mA
mA
Vdc
14.5Vdc≤VIN≤27Vdc
1.0mA≤IOUT≤100mA
1.0mA≤IOUT≤40mA
IB
Quiescent Current
6.5
1.5
16Vdc≤VIN≤27Vdc
1.0mA ≤IOUT≤40mA
IOUT=100mA
Quiescent Current Change
∆ IB
VIN-VO Dropout Voltage
1.9
Copyright ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
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APL78L05/12
Application Circuit
V IN
A P L 7 8 L 0 5 /1 2
V O U T
C O U T =
C in =
0 .1 µ F
0 .3 3 µ F
Note1 : A common ground is required between the input and the output voltage. The input voltage must
remain typically 2V above the output voltage even during the low point on the input ripple voltage.
Note2 : Cin is required if regulator is located an appreciable distance from power supply filter.
Note3 : COUT is not needed for stability; however, it does improve transient response.
Copyright ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
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APL78L05/12
Typical Characteristics
Output Voltage vs. Input Voltage
Dropout Voltage vs. Junction Temperature
APL78L05
APL78L05
8
7
6
5
4
3
2
1
0
2.25
2
IO=70mA
1.75
IO=1mA
IO=40mA
1.5
1.25
1
IO=1mA
IO=40mA
IO=100mA
Dropout of Regulation is
defined as when
∆Vo=1% of Vo
0
2
4
6
8
10
0
25
50
75
100
125
Input Voltage (V)
Junction Temperature (°C)
Quiescent Current vs. Ambient Temperature
Quiescent Current vs. Input Voltage
APL78L05
APL78L05
3 .5
3
3.0
No Load
VIN=10V
IO=40mA
2.8
2.6
2.4
2.2
2 .5
2
1 .5
1
0 .5
0
0
25
50
75
100
125
0
5
1 0
1 5
2 0
2 5
3 0
3 5
Ambient Temperature (°C)
Input Voltage (V)
Copyright ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
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APL78L05/12
Typical Characteristics (Cont.)
Quiescent Current vs. Output Current
Dropout Voltage vs. Output Current
APL78L05
APL78L05
3
1.9
1.85
1.8
VIN=10V
2.5
2
1.5
1
1.75
1.7
Dropout of
Regulation is
defined as when
∆Vo=1% of Vo
0.5
0
1.65
1.6
0
20
40
60
80
100
0
20
40
60
80
100
Output Current (mA)
Output Current (mA)
PSRR vs. Frequency
Load-Transient Response
APL78L05
APL78L05
+0
C
=0.1uF
OUT
VIN=10V
IOUT=10mA
-10
-20
-30
-40
-50
-60
V(100mv/div)
OUT
IOUT=10mA~80mA
-70
-80
10
100
1k
10k
100k
Frequency (Hz)
Time (20µs/div)
Copyright ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
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APL78L05/12
Typical Characteristics (Cont.)
Maximum Power Dissipation vs.
Line Transient Response
Ambient Temperature
APL78L05
APL78L05
TO-92 Type Package
No Heat Sink
1300
1100
900
700
500
300
100
VIN=9.5V~10.5V
COUT=0.1µF
IOUT=10mA
VOUT=10(mV/div)
25
50
75
100
125
150
Time (100us/div)
Ambient Temperature (°C)
Region of Stable ESR vs.
Output Current
Output Voltage vs.
Ambient Temperature
APL78L05
APL78L05
5.02
10
1
VIN=10V
IO=40mA
COUT=0.1uF
5.015
5.01
5.005
5
Stable Region
0.1
0.01
Untested
40 60
4.995
0
25
50
75
100
125
0
20
80
100
Ambient Temperature (°C)
Output Current(mA)
Copyright ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
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APL78L05/12
Typical Characteristics
The APL78L05/12 Series of fixed voltage regulators Figure 1. Current Regulator
are designed with Thermal Overload Protection that
Input
APL78L05
shuts down the circuit when subjected to an exces-
sive power overload condition. Internal Short Circuit
Protection limits the maximum current the circuit will
pass.
R
Constant
Current to
Grounded
Load
0.33µF
lO
In many low current applications, compensation ca- The APL78L00 regulators can also be used as a cur-
pacitors are not required. However, it is recom- rent source when connected as above. In order to
mended that the regulator input be bypassed with a minimize dissipation the APL78L05 is chosen in this
capacitor if the regulator is connected to the power application. Resistor R determines the current as
supply filter with long wire lengths, or if the output follows :
5.0V
load capacitance is large. The input bypass capaci-
tor should be selected to provide good high-frequency
characteristics to insure stable operation under all
load conditions. A 0.33µF or larger tantalum, mylar,
or other capacitor having low internal impedance at
high frequencies should be chosen. The bypass ca-
pacitor should be mounted with the shortest possible
leads directly across the regulators input terminals.
Good construction techniques should be used to mini-
mize ground loops and lead resistance drops since
the regulator has no external sense lead. Bypassing
the output is also recommended.
IO =
+ IB
R
IB =3.8mA over line and load changes
For example, a 100mA current source would require
R to be a 50Ω, 1/2W resistor and the output voltage
compliance would be the input voltage less 7V.
Figure 2. ±15V Tracking Voltage Regulator
+V
O
+20V
APL78L15
0.33µF
10K
10K
2
3
7
6
MC1741
4
0.33µF
MPSA70
6.5
20V
-V
O
MPSU55
Figure 3. Positive and Negative Regulator
+VO
+VI
APL78LXX
0.1µF
0.1µF
0.33µF
-VI
APL79LXX
0.33µF
-VO
Copyright ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
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APL78L05/12
Packaging Information
SOP-8 pin ( Reference JEDEC Registration MS-012)
E
H
e1
e2
D
A1
A
1
L
0.004max.
Millimeters
Inches
Dim
Min.
Max.
Min.
Max.
0.069
0.010
0.197
0.157
0.244
0.050
0.020
A
A1
D
1.35
0.10
4.80
3.80
5.80
0.40
0.33
1.75
0.25
5.00
4.00
6.20
1.27
0.51
0.053
0.004
0.189
0.150
0.228
0.016
0.013
E
H
L
e1
e2
1.27BSC
0.50BSC
1
8
8
°
φ
°
Copyright ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
8
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APL78L05/12
Package Information
TO-92
3
2
1
J
e
D
e1
S
L1
b2
b
S
Q
L2
E
A
L
SEATING PLANE
M i l l i m e t e r s
I n c h e s
D i m
M i n .
4 . 5 8
0 . 4 1
0 . 4 1
4 . 9 6
3 . 9 4
2 . 4 2
1 . 1 5
3 . 4 3
1 2 . 7 0
M a x .
5 . 3 3
0 . 5 3
0 . 4 8
5 . 2 0
4 . 1 9
2 . 6 6
1 . 3 9
M i n .
M a x .
0 . 2 1 0
0 . 0 2 1
0 . 0 1 9
0 . 2 0 5
0 . 1 6 5
0 . 1 0 5
0 . 0 5 5
A
φ b
φ b 2
φ D
E
0 . 1 7 0
0 . 1 6 0
0 . 1 6 0
0 . 1 7 5
0 . 1 2 5
0 . 0 9 5
0 . 0 4 5
0 . 1 3 5
0 . 5 0 0
e
e 1
J
L
L 1
L 2
Q
1 . 2 7
2 . 6 6
0 . 0 5 0
0 . 1 0 5
6 . 3 5
2 . 9 3
2 . 4 2
0 . 2 5 0
0 . 1 1 5
0 . 0 8 0
S
Copyright ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
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APL78L05/12
Package Information
SOT-89 (Reference EIAJ ED-7500A Reg stration SC-62)
D
D1
a
E
H
1
2
3
L
C
B1
B
e
e1
A
a
Millimeters
Inches
Dim
Min.
1.40
0.40
0.35
0.35
4.40
1.35
Max.
1.60
0.56
0.48
0.44
4.60
1.83
Min.
Max.
0.063
0.022
0.019
0.017
0.181
0.072
A
B
B1
C
D
D1
e
e1
E
H
0.055
0.016
0.014
0.014
0.173
0.053
1.50 BSC
3.00 BSC
0.059 BSC
0.118 BSC
2.29
3.75
0.80
2.60
4.25
1.20
0.090
0.148
0.031
0.102
0.167
0.047
L
10
10
°
α
°
Copyright ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
10
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APL78L05/12
Physical Specifications
Terminal Material
Lead Solderability
Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn
Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition (IR/Convection or VPR Reflow)
tp
TP
Critical Zone
TL to TP
Ramp-up
TL
tL
Tsmax
Tsmin
Ramp-down
ts
Preheat
25
°
t 25 C to Peak
Time
Classificatin Reflow Profiles
Profile Feature
Average ramp-up rate
(TL to TP)
Sn-Pb Eutectic Assembly
Pb-Free Assembly
3°C/second max.
3°C/second max.
Preheat
100°C
150°C
60-120 seconds
150°C
200°C
60-180 seconds
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (min to max) (ts)
Time maintained above:
- Temperature (TL)
183°C
60-150 seconds
217°C
60-150 seconds
- Time (tL)
Peak/Classificatioon Temperature (Tp)
See table 1
See table 2
Time within 5°C of actual
Peak Temperature (tp)
10-30 seconds
20-40 seconds
Ramp-down Rate
6°C/second max.
6°C/second max.
6 minutes max.
8 minutes max.
Time 25°C to Peak Temperature
Notes: All temperatures refer to topside of the package .Measured on the body surface.
Copyright ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
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APL78L05/12
Classificatin Reflow Profiles(Cont.)
Table 1. SnPb Entectic Process – Package Peak Reflow Temperatures
Package Thickness
Volume mm3
<350
Volume mm3
≥350
<2.5 mm
≥2.5 mm
240 +0/-5°C
225 +0/-5°C
225 +0/-5°C
225 +0/-5°C
Table 2. Pb-free Process – Package Classification Reflow Temperatures
Package Thickness
Volume mm3
<350
Volume mm3
350-2000
Volume mm3
>2000
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
260 +0°C*
260 +0°C*
250 +0°C*
260 +0°C*
250 +0°C*
245 +0°C*
260 +0°C*
245 +0°C*
245 +0°C*
*Tolerance: The device manufacturer/supplier shall assure process compatibility up to and
including the stated classification temperature (this means Peak reflow temperature +0°C.
For example 260°C+0°C) at the rated MSL level.
Reliability test program
Test item
SOLDERABILITY
HOLT
PCT
TST
Method
MIL-STD-883D-2003
MIL-STD-883D-1005.7
JESD-22-B, A102
MIL-STD-883D-1011.9
MIL-STD-883D-3015.7
JESD 78
Description
245 C , 5 SEC
°
1000 Hrs Bias @ 125 C
°
168 Hrs, 100 % RH , 121 C
°
-65 C ~ 150 C, 200 Cycles
VHBM > 2KV, VMM > 200V
10ms , Itr > 100mA
°
°
ESD
Latch-Up
Carrier Tape & Reel Dimensions
t
D
P
Po
E
F
P1
Bo
W
Ao
D1
Ko
Copyright ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
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APL78L05/12
Carrier Tape & Reel Dimensions(Cont.)
T2
J
C
A
B
T1
A
330±1
F
B
62 ± 1.5
D
C
J
T1
2 + 0.5 12.4 +0.2
Po P1
T2
2± 0.2
Ao
W
P
E
Application
SOP-8
12.75 +
0.1 5
12 + 0.3
- 0.1
8± 0.1 1.75± 0.1
Ko
D1
Bo
t
1.55+ 0.25
5.5 ± 0.1 1.55±0.1
4.0 ± 0.1 2.0 ± 0.1 6.4 ± 0.1 5.2± 0.1 2.1± 0.1 0.3±0.013
(mm)
H2A H2
D2
H2 H2
A0
M
H3
H4
H
W2
L
L1
W1
H1
W
D
F1F2
P1
T2
T
T1
D1
P
P2
40
Box
Dimensions
205
C2
C1
B2
B0
B1
C0
A3
330
T3
T4
A2
A1
UNIT : mm
Copyright ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
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APL78L05/12
Carrier Tape & Reel Dimensions(Cont.)
A
3.18~12
C2
A1
A2
A3
B0
B1
B2
C0
5.8
P2
C1
3.8
T
Application
TO-92
90±1
76±1
30±1
90±1
31±1
76±1
H3
H4
L
L1
P
P1
7.8
27.0 MAX 20.0 MAX 11.0 MAX 2.5 MIN 12.7±0.2 6.35±0.4 50.8±0.5 0.55 MAX
T1
T2
W
W1
W2
T3
15
T4
1.42 MAX 0.36~0.68
1.7
17.5~19
5.0~7.0 0.5 MAX
(mm)
Cover Tape Dimensions
Application
SOP- 8
Carrier Width
12
Cover Tape Width
Devices Per Reel
9.3
5.0~7.0
2500
2000
TO-92
17.5~19
Customer Service
Anpec Electronics Corp.
Head Office :
5F, No. 2 Li-Hsin Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369
Copyright ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
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