APW7057KC-TR [ANPEC]
High Power Step-Down Synchronous DC/DC Controller; 高功率降压型同步DC / DC控制器
| 型号： | APW7057KC-TR |
| 厂家： | 
ANPEC ELECTRONICS COROPRATION |
| 描述： | High Power Step-Down Synchronous DC/DC Controller |
| 文件： | 总14页 (文件大小：155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APW7057
High Power Step-Down Synchronous DC/DC Controller
Features
General Description
•
Operates from +5V Input
The APW7057 is a 300kHz constant frequency volt-
age mode synchronous switching controller that drives
external N-channel MOSFETs. When the input sup-
ply drops close to output, the upper MOSFET remains
on, achieving 100% duty cycle. Internal loop compen-
sation is optimized for fast transient response, elimi-
nating external compensation network. The precision
0.8V reference makes this part suitable for a wide va-
riety of low voltage applications. Soft start is internally
set to 2ms, limiting the input in-rush current and pre-
venting the output from overshoot during powering up.
The APW7057 has over current and short circuit
protections. Over current protection is achieved by
monitoring the voltage drop across the high side
MOSFET, eliminating the need for a current sens-
ing resistor and short circuit condition is detected
through the FB pin. If either fault conditions occur,
the APW7057 would initiate the soft start cycle. After
three cycles and if the fault condition persists, the
controller will be shut down. To restart the controller,
either recycle the VCC supply or momentarily pull the
OSCSET pin below 1.25V.
•
0.8V Internal Reference Voltage
- ±1.5% Accuracy Over Line, Load and Temp.
0.8V to VCC Output Range
Full Duty Cycle Range
•
•
- 0% to 100%
•
•
Internal Loop Compensation
Internal Soft Start
- Typical 2ms
•
Programmable Over-Current Protection
- Lossless Sensing Using MOSFET RDS (ON)
Under-Voltage Protection
Drives External N-Channel MOSFETs
Shutdown Control
•
•
•
•
Small SOP-8 Package
Applications
The APW7057 can be shutdown by pulling the OCSET
pin below 1.25V. In shutdown, both gate drive signals
will be low. The controller is available in a small SOP-
8 package.
•
•
•
•
•
•
•
Motherboard
Graphics Cards
Cable or DSL Modems, Set Top Boxes
DSP Supplies
Memory Supplies
Pinouts
5V Input DC-DC Regulators
Distributed Power Supplies
PHASE
OCSET
1
2
3
4
BOOT
8
7
UGATE
6
5
GND
FB
LGATE
VCC
SOP-8 (Top View )
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
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ANPEC Electronics Corp.
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Rev. A.3 - Oct., 2003
APW7057
Ordering and Marking Information
Package Code
APW7057
K : SOP-8
Operating Junction Temp. Range
°
Handling Code
Temp. Range
Package Code
C : 0 to 70 C
Handling Code
TU : Tube
TR : Tape & Reel
APW7057
XXXXX
APW7057 K :
XXXXX - Date Code
Block Diagram
VCC
BOOT
Shutdown
UnderVoltage
Lockout
OCSET
IOCSET
40uA
OC
Comparator
UVLO
Soft-Start
and Fault
Logic
OCP
PHASE
UGATE
0.5V
UVP
Soft-Start
Inhibit
PWM
Gate
Control
COMP
FB
-
VCC
+
+
Error
Amplifier
-
V
REF
LGATE
GND
0.8V
OSC
F
Oscillator
300kHz
F i g u r G Figure 1.
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Rev. A.3 - Oct., 2003
APW7057
Typical Application
R3
2.2
C3
1uF
V
IN
+5V
5
+
C2
1000uF x2
C1
1uF
D1
C7
R4
VCC
1N4148
470pF
8.2k
1
2
8
BOOT
7
OCSET
C4
0.1uF
Q3
Q1
Q2
UGATE
PHASE
L1
3.3uH
VOUT
Shutdown
+
+2.5V/10A
U1
APW7057
LGATE
C5
1000uF x2
4
6
FB
GND
3
R1
5.1k
R2
2.4k
C6
0.1uF
Q1: APM2014N UC
Q2: APM2014N UC
Q3: APM2300A AC
C2: 1000uF/10V, ESR = 25mΩ
C5: 1000uF/6.3V, ESR = 25mΩ
FigurGFigure 2.
Absolute Maximum Ratings
Symbol
Parameter
VCC Supply Voltage (VCC to GND)
BOOT Supply Voltage (BOOT to GND)
PHASE, OCSET to GND Input Voltage
FB to GND Input Voltage
Rating
-0.3 ~ 7
-0.3 ~ 15
-0.3 ~ 12
CC
Unit
V
CC
V
BOOT
V
V
V
-0.3 ~ V +0.3
V
Maximum Junction Temperature
Storage Temperature
125
-65 ~ 150
300
oC
oC
oC
kV
STG
T
SDR
T
Maximum Soldering Temperature, 10 Seconds
Minimum ESD Rating
ESD
V
±2
Thermal Characteristics
Symbol
Parameter
Junction-to-Ambient Resistance in free air (SOP-8)
Value
Unit
θJA
160
oC/W
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Rev. A.3 - Oct., 2003
APW7057
Recommended Operating Conditions
Symbol
VCC
VOUT
VIN
Parameter
Range
5%
Unit
V
VCC Supply Voltage
5
±
Output Voltage of the Switching Regulator (Note)
Input Voltage of the Switching Regulator (Note)
Ambient Temperature
0.8 ~ VCC
3.3 ~ VCC
0 ~ 70
V
V
TA
oC
oC
TJ
Junction Temperature
0 ~ 125
Note : Refer to the typical application circuit
Electrical Characteristics
Unless otherwise specified, these specifications apply over VCC=5V, VBOOT=12V and TA= 0~70 oC. Typical
values are at TA=25oC.
APW7057
Unit
Symbol
Parameter
Test Conditions
Min Typ Max
SUPPLY CURRENT
VCC Nominal Supply
Current
IVCC
2.1
2.1
mA
mA
UGATE and LGATE Open
UGATE Open
BOOT Nominal Supply
Current
IBOOT
Under Voltage Lockout(UVLO)
Rising VCC Threshold
Falling VCC Threshold
OSCILLATOR
4.0
3.8
4.2
4.0
4.4
4.2
V
V
FOSC
Free Running Frequency
Ramp Upper Threshold
Ramp Lower Threshold
Ramp Amplitude
250
300
2.85
0.95
1.9
340
kHz
V
V
VP-P
VOSC
∆
REFERENCE VOLTAGE
VREF Reference Voltage
0.8
V
Reference Voltage
Accuracy
-1.5
+1.5
%
ERROR AMPLIFIER
DC Gain
75
10
1
dB
Hz
FP
FZ
First Pole Frequency
First Zero Frequency
UGATE Duty Range
FB Input Current
kHz
%
0
100
0.1
A
µ
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Rev. A.3 - Oct., 2003
APW7057
Electrical Characteristics (Cont.)
Unless otherwise specified, these specifications apply over VCC=5V, VBOOT=12V and TA= 0~70 oC. Typical
values are at TA=25oC.
APW7057
Symbol
Parameter
Test Conditions
Unit
Min Typ Max
PWM CONTROLLER GATE DRIVERS
UAGTE
UGATE
LGATE
UGATE Source
UGATE Sink
LGATE Source
LGATE Sink
D
V
V
V
V
=1V
0.6
7.3
0.6
1.8
50
A
Ω
=1V
=1V
=1V
A
LGATE
Ω
T
Dead Time
nS
PROTECTION
OCSET
I
OCSET
OCSET Sink Current
V
=4.5V
34
40
46
µA
FB
UV
FB Under-Voltage Level
FB falling
0.5
V
FB Under-Voltage
Hysteresis
15
mV
SOFT-START AND SHUTDOWN
SS
T
Soft-Start Interval
2
mS
V
OCSET
Shutdown Threshold
V
Falling
1.25
OCSET Shutdown
Hysteresis
20
mV
Functional Pin Description
BOOT (Pin 1)
LGATE (Pin 4)
This pin provides the supply voltage to the high side
MOSFET driver. A voltage no greater than 13V can
be connected to this pin as a supply to the driver.
For driving logic level N-channel MOSEFT, a boot-
strap circuit can be use to create a suitable driver’s
supply.
This pin provides the gate drive signal for the low
side MOSFET.
VCC (Pin 5)
This is the main bias supply for the controller and
its low side MOSFET driver. Must be closely
decoupled to GND (Pin 3). DO NOT apply a
voltage greater than 5.5V to this pin.
UGATE (Pin 2)
This pin provides gate drive for the high-side
MOSFET.
GND (Pin 3)
FB (Pin 6)
Signal and power ground for the IC. All voltage lev-
els are measured with respect to this pin. Tie this
pin to the ground plane through the lowest imped-
ance connection available.
This pin is the inverting input of the error amplifier
and it receives the feedback voltage from an exter-
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APW7057
Functional Pin Description
nal resistive divider across the output (VOUT). The the over current limit. An internally generated 40uA
output voltage is determined by:
current source will flow through this resistor, creat-
ing a voltage drop. This voltage will be compared
with the voltage across the high side MOSFET. The
threshold of the over current limit is therefore given
by:
ROUT
RGND
VOUT = 0.8V(1+
)
where ROUT is the resistor connected between VOUT
and FB while RGND is the resistor connected from FB
to GND.
40uA x ROCSET
IOI =
RDS(ON)
OCSET (Pin 7)
An over current condition will cycle the soft start
function. After three consecutive cycles and if the
fault condition persists, the controller will be shut
down. To restart the controller, either recycle the VCC
supply or momentarily pull the OSCSET pin below
1.25V.
This pin serves two functions: as a shutdown con-
trol and for setting the over current limit threshold.
Pulling this pin below 1.25V shuts the controller
down, forcing the UGATE and LGATE signals to be
at 0V. A soft start cycle will be initiated upon the re-
lease of this pin.
A resistor (Rocset) connected between this pin and
the drain of the high side MOSFET will determine
PHASE (Pin 8)
This pin is connected to the source of the high-side
MOSFET and is used to monitor the voltage drop
across the high-side MOSFET for over-current
protection.
Typical Characteristics
Switching Frequency vs. Junction Temperature
Reference Voltage vs. Junction Temperature
350
340
330
320
310
300
290
280
270
260
250
0.812
0.808
0.804
0.800
0.796
0.792
0.788
-50
-25
0
25
50
75
100 125 150
-50 -25
0
25
50
75 100 125 150
Junction Temperature (oC)
Junction Temperature (°C)
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Rev. A.3 - Oct., 2003
APW7057
Typical Characteristics (Cont.)
OCSET Current vs. Junction Temperature
46
45
44
43
42
41
40
39
38
37
36
35
34
-50
-25
0
25
50
75
100 125 150
Junction Temperature (oC)
Operating Waveforms (Refer to the typical application circuit)
1. Load Transient Response : IOUT = 0A -> 10A -> 0A
- IOUT slew rate = Ó 10A/µS
IOUT = 0A -> 10A
IOUT = 0A -> 10A -> 0A
IOUT = 10A -> 0A
VOUT
VOUT
VOUT
VUGATE
VUGATE
10A
IOUT
IOUT
IOUT
0A
Ch1 : VOUT, 100mV/Div, DC,
Offset = 2.50V
Ch1 : VOUT, 100mV/Div, DC,
Offset = 2.50V
Ch1 : VOUT, 100mV/Div, DC,
Offset = 2.50V
Ch2 : VUGATE, 10V/Div, DC
Ax1 : IOUT, 5A/Div
Time : 10µS/Div
Ax1 : IOUT, 5A/Div
Time : 100µS/Div
BW = 20MHz
Ch2 : VUGATE, 10V/Div, DC
Ax1 : IOUT, 5A/Div
Time : 10µS/Div
BW = 20MHz
BW = 20MHz
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Rev. A.3 - Oct., 2003
APW7057
Operating Waveforms (Refer to the typical application circuit)
2. UGATE and LGATE
UGATE Rising
UGATE Falling
IOUT=10A
IOUT=10A
VUGATE
VUGATE
VLGATE
VLGATE
Ch1 : VUGATE, 2V/Div, DC
Time : 125nS/Div
Ch2 : VLGATE, 2V/Div, DC
BW = 500MHz
Ch1 : VUGATE, 2V/Div, DC
Time : 125nS/Div
Ch2 : VLGATE, 2V/Div, DC
BW = 500MHz
3. Powering ON / OFF
Soft-start at Powering ON
Powering OFF
VIN
VIN
VOUT
VOUT
Ch1 : VIN, 2V/Div, DC
Time : 5mS/Div
Ch2 : VOUT, 1V/Div, DC
BW = 20MHz
Ch1 : VIN, 2V/Div, DC
Time : 1mS/Div
Ch2 : VOUT, 1V/Div, DC
BW = 20MHz
4. Short-Circuit Protection
Under-Voltage (UVP)
UVP
and Over-Current Protection (OCP)
OCP
OCP
Ch1 : VOUT, 1V/Div, DC
Ax1 : IOUT, 10A/Div
Time : 1mS/Div
VOUT
BW = 20MHz
IOUT
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Rev. A.3 - Oct., 2003
APW7057
Application Information
Component Selection Guidelines
∆VOUT = IRIPPLE x ESR
Output Capacitor Selection
where Fs is the switching frequency of the regulator.
The selection of COUT is determined by the required
effective series resistance (ESR) and voltage rating
rather than the actual capacitance requirement. There-
fore select high performance low ESR capacitors that
are intended for switching regulator applications. In
some applications, multiple capacitors have to be
paralled to achieve the desired ESR value. If tantalum
capacitors are used, make sure they are surge tested
by the manufactures. If in doubt, consult the capaci-
tors manufacturer.
There is a tradeoff exists between the inductor’s ripple
current and the regulator load transient response time
A smaller inductor will give the regulator a faster load
transient response at the expense of higher ripple cur-
rent and vice versa. The maximum ripple current oc-
curs at the maximum input voltage. A good starting
point is to choose the ripple current to be approxi-
mately 30% of the maximum output current.
Once the inductance value has been chosen, select
an inductor that is capable of carrying the required
peak current without going into saturation. In some
type of inductors, especially core that is make of
ferrite, the ripple current will increase abruptly when it
saturates. This will result in a larger output ripple
voltage.
Input Capacitor Selection
The input capacitor is chosen based on the voltage
rating and the RMS current rating. For reliable
operation, select the capacitor voltage rating to be at
least 1.3 times higher than the maximum input voltage.
The maximum RMS current rating requirement is ap-
proximately IOUT/2 , where IOUT is the load current.
During power up, the input capacitors have to handle
large amount of surge current. If tantalum capacitors
are used, make sure they are surge tested by the
manufactures. If in doubt, consult the capacitors
manufacturer.
MOSFET Selection
The selection of the N-channel power MOSFETs are
determined by the RDS(ON), reverse transfer capacitance
(CRSS) and maximum output current requirement.The
losses in the MOSFETs have two components: con-
duction loss and transition loss. For the upper and
lower MOSFET, the losses are approximately given
by the following :
For high frequency decoupling, a ceramic capacitor
between 0.1uF to 1uF can be connected between VCC
and ground pin.
PUPPER = Iout2(1+ TC)(RDS(ON))D + (0.5)(Iout)(VIN)(tsw)FS
PLOWER = Iout2(1+ TC)(RDS(ON))(1-D)
Inductor Selection
The inductance of the inductor is determined by the
output voltage requirement. The larger the inductance,
the lower the inductor’s current ripple. This will trans-
late into lower output ripple voltage. The ripple current
where IOUT is the load current
TC is the temperature dependency of RDS(ON)
FS is the switching frequency
tsw is the switching interval
and ripple voltage can be approximated by:
F
i
VIN - VOUT
Fs x L
VOUT
VIN
x
IRIPPLE
=
D is the duty cycle
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Rev. A.3 - Oct., 2003
APW7057
Application Information
single point grounding. Figure 4 illustrates the layout,
with bold lines indicating high current paths. Compo-
nents along the bold lines should be placed close
together. Below is a checklist for your layout:
Note that both MOSFETs have conduction losses while
the upper MOSFET include an additional transition
loss.The switching internal, tsw, is a function of the
reverse transfer capacitance CRSS. Figure 3 illustrates
the switching waveform internal of the MOSFET.
The (1+TC) term is to factor in the temperature depen-
dency of the RDS(ON) and can be extracted from the
“RDS(ON) vs Temperature” curve of the power MOSFET.
• Keep the switching nodes (UGATE, LGATE and
PHASE) away from sensitive small signal nodes
since these nodes are fast moving signals. There
fore keep traces to these nodes as short as
possible.
Layout Considerations
• Decoupling capacitor CIN provides the bulk capaci
tance and needs to be placed close to the IC since
it will provide the MOSFET drivers transient current
requirement.
In high power switching regulator, a correct layout is
important to ensure proper operation of the regulator.
In general, interconnecting impedances should be mini-
mized by using short, wide printed circuit traces. Sig-
nal and power grounds are to be kept separate and
finally combined using ground plane construction or
• The ground return of CIN must return to the combine
COUT (-) terminal.
• Capacitor CBOOT should be connected as close to
the BOOT and PHASE pins as possible.
V DS
V
IN
CHF
CIN
5
VCC
+
1
BOOT
4
LGATE
APW7057
2
8
COUT
Q1
UGATE
Q2
+
PHASE
L1
VOUT
t
Time
sw
Figure 4. Recommended Layout Diagram
Figure 3. Switching waveform across MOSFET
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Rev. A.3 - Oct., 2003
APW7057
Packaging Information
SOP-8 pin ( Reference JEDEC Registration MS-012)
E
H
e1
e2
D
A1
A
1
L
0.004max.
Millimeters
Inches
Dim
Min.
Max.
1.75
0.25
5.00
4.00
6.20
1.27
0.51
Min.
Max.
0.069
0.010
0.197
0.157
0.244
0.050
0.020
A
A1
D
1.35
0.10
4.80
3.80
5.80
0.40
0.33
0.053
0.004
0.189
0.150
0.228
0.016
0.013
E
H
L
e1
e2
1.27BSC
0.50BSC
1
8
8
°
φ
°
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Rev. A.3 - Oct., 2003
APW7057
Physical Specifications
Terminal Material
Lead Solderability
Packaging
Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb
Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
2500 devices per reel
Reflow Condition (IR/Convection or VPR Reflow)
Reference JEDEC Standard J-STD-020A APRIL 1999
Peak temperature
°
183 C
Pre-heat temperature
Time
Classification Reflow Profiles
Convection or IR/
Convection
VPR
°
±
°
°
Average ramp-up rate(183 C to Peak)
3 C/second max.
120 seconds max.
60 ~ 150 seconds
10 ~ 20 seconds
10 C /second max.
°
25 C)
Preheat temperature 125
°
C
Temperature maintained above 183
Time within 5 C of actual peak temperature
Peak temperature range
°
60 seconds
° °
215~ 219 C or 235 +5/-0 C
°
°
220 +5/-0 C or 235 +5/-0 C
Ramp-down rate
°
°
6 C /second max.
10 C /second max.
°
6 minutes max.
Time 25 C to peak temperature
Package Reflow Conditions
pkg. thickness < 2.5mm and pkg.
volume <
pkg. thickness < 2.5mm and
pkg. thickness
and all bags
≥ 2.5mm
≥
pkg. volume
350 mm
°
°
C
Convection 220 +5/-0 C
Convection 235 +5/-0
°
°
C
VPR 215-219 C
VPR 235 +5/-0
IR/Convection 235 +5/-0 C
°
°
IR/Convection 220 +5/-0 C
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Rev. A.3 - Oct., 2003
APW7057
Reliability test program
Test item
SOLDERABILITY
HOLT
PCT
TST
Method
Description
MIL-STD-883D-2003
MIL-STD-883D-1005.7
JESD-22-B, A102
MIL-STD-883D-1011.9
MIL-STD-883D-3015.7
JESD 78
245 C , 5 SEC
°
1000 Hrs Bias @ 125 C
°
168 Hrs, 100 % RH , 121 C
°
-65 C ~ 150 C, 200 Cycles
VHBM > 2KV, VMM > 200V
10ms , Itr > 100mA
°
°
ESD
Latch-Up
Carrier Tape & Reel Dimension
t
D
P
Po
E
P1
Bo
F
W
Ao
D1
Ko
T2
J
C
A
B
T1
A
B
C
J
T1
T2
W
12 + 0.3
- 0.1
P
E
Application
SOP-8
12.75 +
0.1 5
2 + 0.5 12.4 +0.2
330 1
62 1.5
2 0.2
±
8 0.1 1.75 0.1
±
±
±
±
F
D
D1
Po P1
Ao
Bo
Ko
t
1.55+ 0.25
5.5 0.1 1.55 0.1
4.0 0.1 2.0 0.1 6.4 0.1 5.2 0.1 2.1 0.1 0.3 0.013
± ± ± ± ± ±
±
±
(mm)
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Rev. A.3 - Oct., 2003
APW7057
Cover Tape Dimensions
Application
SOP- 8
Carrier Width
Cover Tape Width
Devices Per Reel
12
9.3
2500
Customer Service
Anpec Electronics Corp.
Head Office :
5F, No. 2 Li-Hsin Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369
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Rev. A.3 - Oct., 2003
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