APW7064 [ANPEC]
Synchronous Buck PWM Controller; 同步降压PWM控制器
| 型号： | APW7064 |
| 厂家： | 
ANPEC ELECTRONICS COROPRATION |
| 描述： | Synchronous Buck PWM Controller |
| 文件： | 总19页 (文件大小：388K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APW7064
Synchronous Buck PWM Controller
Features
General Description
The APW7064 uses fixed 200kHz switching frequency,
voltage mode, synchronous PWM controller which drives
dual N-channel MOSFETs. The device integrates the
control, monitoring and protection functions into a single
package, provides one controlled power output with
under-voltage protection.
·
·
Single 12V Power Supply Required
Fast Transient Response
- 0~90% Duty Ratio
·
·
1.2V Reference with 1% Accuracy
Shutdown Function by Controlling COMP Pin
Voltage
The APW7064 provides excellent regulation for output
load variation. The internal 1.2V temperature-compensated
reference voltage is designed to meet the requirement
of low output voltage applications. An built-in digital soft-
start with fixed soft-start interval prevents the output voltage
from overshoot as well as limiting the input current.
The APW7064 with excellent protection functions: POR
and UVP. The Power-On-Reset (POR) circuit can monitor
VCC supply voltage exceeds its threshold voltage while
the controller is running, and a built-in digital soft-start
provides output with controlled voltage rise. The Under-
Voltage Protection (UVP) monitors the voltage of FB pin
for short-circuit protection. When the VFB is less than
50% of VREF (0.6V), the controller will shutdown the IC
directly.
·
·
·
·
·
·
Internal Soft-Start (5.1ms) Function
Voltage Mode PWM Control Design
Under-Voltage Protection
200kHz Fixed Switching Frequency
SOP-8P Package
Lead Free and Green Devices Available
(RoHS Compliant)
Applications
·
·
·
Graphics Card
Mother Board
SMPS
Pin Configuration
Typical Application Circuit
BOOT 1
UGATE 2
GND 3
8 PHASE
7 COMP
12V
VIN
6 FB
LGATE 4
5 VCC
SOP-8P
APW7064
VOUT
L
APW7064
= Thermal Pad
(connected to GND plane for better heat dissipation)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
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Rev. A.3 - Aug., 2009
APW7064
Ordering and Marking Information
Package Code
KA : SOP-8P
APW7064
Temperature Range
Assembly Material
Handling Code
E : -20 to 70 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
Temperature Range
Package Code
APW7064
XXXXX
XXXXX - Date Code
APW7064 KA :
Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings (Note 1)
Symbol
VCC
Parameter
Rating
Unit
V
VCC to GND
-0.3 to +16
-0.3 to +16
VBOOT
BOOT to PHASE
V
UGATE to PHASE <400ns pulse width
>400ns pulse width
-5 to VBOOT +5
-0.3 to VBOOT +0.3
VUGATE
VLGATE
VPHASE
V
V
V
LGATE to PGND
PHASE to GND
COMP, FB to GND
<400ns pulse width
>400ns pulse width
-5 to VCC+5
-0.3 to VCC+0.3
<200ns pulse width
>200ns pulse width
-10 to +30
-2 to 16
VCOMP, VFB
TJ
-0.3 to +7
-20 ~ 150
-65 ~ 150
260
Junction Temperature Range
°C
°C
°C
TSTG
Storage Temperature
TSDR
Maximum Lead Soldering Temperature, 10 Seconds
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristics
Symbol
Parameter
Typical Value
Unit
Junction-to-Ambient Resistance in Free Air
80
oC/W
qJA
SOP-8P
Note 2: qJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Recommended Operating Conditions
Symbol
VCC
Parameter
Rating
10.8 to 13.2
1.2 to 5
Unit
V
VCC Supply Voltage
VOUT
VIN
Converter Output Voltage
Converter Input Voltage
V
2.9 to 13.2
V
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APW7064
Recommended Operating Conditions (Cont.)
Symbol
Parameter
Rating
0 to 30
Unit
A
IOUT
Converter Output Current
Ambient Temperature Range
Junction Temperature Range
TA
-20 to 70
-20 to 125
°C
°C
TJ
Electrical Characteristics
Unless otherwise specified, these specifications apply over VCC = 12V, and TA =-20 ~ 70°C. Typical values are at TA = 25°C.
APW7064
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
SUPPLY CURRENT
IVCC
VCC Nominal Supply Current
VCC Shutdown Supply Current
UGATE and LGATE Open
UGATE, LGATE = GND
-
-
5
1
10
2
mA
mA
POWER-ON-RESET
Rising VCC Threshold
9
7.5
-
9.5
8
10
8.5
-
V
V
V
V
Falling VCC Threshold
COMP Shutdown Threshold
COMP Shutdown Hysteresis
1.2
0.1
-
-
OSCILLATOR
FOSC
Free Running Frequency
Ramp Amplitude
170
-
200
1.6
230
-
kHz
VP-P
DVOSC
REFERENCE VOLTAGE
VREF Reference Voltage
Accuracy
ERROR AMPLIFIER
Measured at FB Pin
-
1.2
-
-
V
-1.0
+1.0
%
TA =-20~70°C
Gain
Open Loop Gain
RL=10k, CL=10pF (Note 3)
RL=10k, CL=10pF (Note 3)
RL=10k, CL=10pF (Note 3)
VFB = 0.8V (Note 3)
-
-
-
-
-
-
-
-
88
15
6
-
-
dB
MHz
V/ms
mA
GBWP Open Loop Bandwidth
SR
Slew Rate
-
FB Input Current
COMP High Voltage
COMP Low Voltage
COMP Source Current
COMP Sink Current
0.1
5.5
0
1
-
VCOMP
VCOMP
ICOMP
ICOMP
V
-
V
VCOMP=2V
VCOMP=2V
5
-
mA
mA
5
-
GATE DRIVERS
IUGATE
IUGATE
ILGATE
ILGATE
Upper Gate Source Current
-
-
-
-
-
-
-
2.6
1.05
4.9
1.4
2
-
A
A
VBOOT = 12V, VUGATE -VPHASE = 2V
VBOOT = 12V, VUGATE -VPHASE = 2V
Upper Gate Sink Current
Lower Gate Source Current
Lower Gate Sink Current
-
-
A
VCC = 12V, VLGATE = 2V
VCC = 12V, VLGATE = 2V
-
A
RUGATE Upper Gate Source Impedance
RUGATE Upper Gate Sink Impedance
RLGATE Lower Gate Source Impedance
VBOOT = 12V, IUGATE = 0.1A
VBOOT = 12V, IUGATE = 0.1A
VCC = 12V, ILGATE = 0.1A
3
W
W
W
1.6
1.3
2.4
1.95
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APW7064
Electrical Characteristics (Cont.)
Unless otherwise specified, these specifications apply over VCC = 12V, and TA =-20 ~ 70°C. Typical values are at TA = 25°C.
APW7064
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
GATE DRIVERS (CONT.)
RLGATE Lower Gate Sink Impedance
TD Dead Time
PROTECTIONS
VCC = 12V, ILGATE = 0.1A
-
-
1.25
20
1.88
-
W
ns
VUVP
Under-Voltage Threshold Trip Point
Percent of VREF
45
50
55
6
%
SOFT-START
TSS
Soft-Start Interval
4.4
5.1
ms
Note 3: Guaranteed by design.
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APW7064
Typical Operating Characteristics
UGATE Source Current vs. UGATE Voltage
UGATE Sink Current vs. UGATE Voltage
3.5
3
VBOOT =12V
VPHASE=2V
VBOOT =12V
VPHASE=2V
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
0
2
4
6
8
10
12
0
2
4
6
8
10
12
UGATE Voltage (V)
UGATE Voltage (V)
LGATE Source Current vs. LGATE Voltage
LGATE Sink Current vs. LGATE Voltage
3.5
3
6
VCC=12V
VCC=12V
5
2.5
2
4
3
2
1
0
1.5
1
0.5
0
0
2
4
6
8
10
12
0
2
4
6
8
10
12
LGATE Voltage (V)
LGATE Voltage (V)
Switching Frequency vs. Junction Temperature
Reference Voltage vs. Junction Temperature
206
1.204
VCC=12V
VCC=12V
1.202
203
1.2
1.198
1.196
1.194
1.192
1.19
200
197
194
191
188
185
1.188
-40 -20
0
20
40
60
80 100 120
40
60
80
100 120
-40 -20
0
20
Junction Temperature (°C)
Junction Temperature (°C)
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APW7064
Operating Waveforms
Power On
Power Off
VCC=12V, VIN=12V
VOUT=3.3V, L=1uH
VCC=12V, VIN=12V
VOUT=3.3V, L=1uH
1
2
1
2
3
4
3
4
CH1: VCC (5V/div)
CH2: VFB (1V/div)
CH3: VOUT (2V/div)
CH4: UGATE (20Vdiv)
Time: 10ms/div
CH1: VCC (5V/div)
CH2: VFB (1V/div)
CH3: VOUT (2V/div)
CH4: UGATE (20Vdiv)
Time: 10ms/div
EN(EN=VCC)
Shutdown(EN=GND)
VCC=12V, VIN=12V
VOUT=3.3V, L=1uH
VCC=12V, VIN=12V
VOUT=3.3V, L=1uH
1
2
1
2
3
4
3
4
CH1: VCOMP (1V/div)
CH2: VOUT (2V/div)
CH3: UGATE (20V/div)
CH4: LGATE (10Vdiv)
Time: 5ms/div
CH1: VCOMP (1V/div)
CH2: VOUT (2V/div)
CH3: UGATE (20V/div)
CH4: LGATE (10Vdiv)
Time: 5ms/div
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APW7064
Operating Waveforms (Cont.)
UGATE Rising
UGATE Falling
VCC=12V, VIN=12V
VOUT=3.3V, L=1uH
VCC=12V, VIN=12V
VOUT=3.3V, L=1uH
1
1
2
3
2
3
CH1: UGATE (20V/div)
CH2: LGATE (5V/div)
CH3: VPHASE (10V/div)
Time: 50ns/div
CH1: UGATE (20V/div)
CH2: LGATE (5V/div)
CH3: VPHASE (10V/div)
Time: 50ns/div
Load Transient Response
Under Voltage Protection
VCC=12V, VIN=12V
VOUT=3.3V, L=1uH
VCC=12V, VIN=12V
VOUT=3.3V, L=1uH
1
2
1
3
4
2
CH1: VOUT (200mV/div)
CH2: IOUT (5A/div)
Time: 1ms/div
CH1: IOUT(10A/div)
CH2: VFB (1V/div)
CH3: UGATE (20V/div)
CH4: LGATE(10V/div)
Time: 1ms/div
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APW7064
Operating Waveforms (Cont.)
Short Test
VCC=12V, VIN=12V
VOUT=3.3V, L=1uH
1
2
3
CH1: VOUT (2V/div)
CH2: UGATE (20V/div)
CH3: LGATE (10V/div)
Time: 2ms/div
Pin Description
PIN
FUNCTION
NO.
NAME
A bootstrap circuit with a diode connected to VCC is used to create a voltage suitable to drive a logic-level
N-channel MOSFET.
1
BOOT
Connect this pin to the high-side N-channel MOSFET gate. This pin provides gate drive for the high-side
MOSFET.
2
3
4
UGATE
GND
The GND terminal provides return path for the IC bias current and the low-side MOSFET driver pull-low
current. Connect the pin to the system ground via very low impedance layout on PCBs.
Connect this pin to the low-side N-channel MOSFET gate. This pin provides gate drive for the low-side
MOSFET.
LGATE
Connect this pin to a 12V supply voltage. This pin provides bias supply for the control circuitry and the
low-side MOSFET driver. The voltage at this pin is monitored for the Power-On-Reset (POR) purpose. It is
recommended that a decoupling capacitor (1 to 10mF) be connected to GND for noise decoupling.
5
VCC
This pin is the inverting input of the internal error amplifier. Connect this pin to the output (VOUT) of the
converter via an external resistor divider for closed-loop operation. The output voltage set by the resistor
divider is determined using the following formula:
æ
ROUT ö
6
FB
VOUT = 1.2´ ç1+
÷
÷
ç
è
RGND ø
where ROUT is the resistor connected from VOUT to FB, and RGND is the resistor connected from FB to GND.
The FB pin is also monitored for under voltage events.
This pin is the output of PWM error amplifier. It is used to set the compensation components. In addition, if
the pin is pulled below 1.2V, it will disable the device.
7
8
COMP
PHASE This pin is the return path for the upper gate driver. Connect this pin to the upper MOSFET source.
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APW7064
Block Diagram
VCC
GND
BOOT
Power-On
Reset
UGATE
Digital
Soft-Start
PHASE
U.V.P
50%VREF
Comparator
:
2
Error
Amp
PWM
Comparator
Gate
Control
LGATE
VREF
Sawtooth
Wave
Oscillator
FOSC
200kHz
FB
COMP
Typical Application Circuit
1N4148
12V
(12V)
VIN
1mH
10R
1mF
10mF
2200mFx2
100mF
5
1
VCC
BOOT
0.1mF
Q1
APM2509
4.5mH
2
8
UGATE
PHASE
VOUT
(3.3V)
Q3
7
6
2N7002
ON/OFF
COMP
FB
Q2
APM2506
4
2200mFx2
LGATE
10nF
6.8K
1nF
GND
3
4.7K
2.67K
10nF 1.5K
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APW7064
Function Description
Power-On-Reset (POR)
Voltage (V)
VFB
The Power-On-Reset (POR) function of APW7064 continually
monitors the input supply voltage (VCC) and the COMP
pin. The supply voltage (VCC) must exceed its rising POR
threshold voltage. The POR function initiates soft-start
operation after VCC and COMP voltages exceed their
POR thresholds. For operation with a single +12V power
source, VIN and VCC are equivalent and the +12V power
source must exceed the rising VCC threshold. The POR
function inhibits operation at disabled status (VCOMP is
less than 1.2V). With both input supplies above their
POR thresholds, the device initiates a soft-start interval.
18.75mV
16/FOSC
Time
Figure 2.The Controlled Stepped FB Voltage During Soft-
Start
Shutdown and Enable
Soft-Start
Pulling the COMP voltage to GND by an open drain
transistor, shown in typical application circuit,
shutdown the APW7064 PWM controller. In shutdown
mode, the UGATE and LGATE turn off and pull to PHASE
and GND respectively.
The APW7064 has a built-in digital soft-start to control
the output voltage rise and limit the current surge during
the start-up. In Figure 1, when VCC exceeds rising POR
threshold voltage, it will delay 1024/Fosc seconds and
then begin soft-start. During soft-start, an internal ramp
connected to the one of the positive inputs of the Gm
amplifier rises up from 0V to 2V to replace the reference
voltage (1.2V) until the ramp voltage reaches the reference
voltage. The soft-start interval is decided by the oscillator
frequency (200kHz). The formulation is given by:
Tdelay = t2 - t1 = 1024/FOSC = 5.1ms
Under Voltage Protection
The FB pin is monitored during converter operation by
the internal Under Voltage (UV) comparator. If the FB
voltage drops below 50% of the reference voltage (50%
of 1.2V = 0.6V), a fault signal is internally generated, and
the device turns off both high-side and low-side MOSFET
and the converter’s output is latched to be floating.
Tsoft- start = t3 - t2 = 1024/FOSC = 5.1ms
Figure 2. shows more detail of the FB voltage ramp. The
FB voltage soft-start ramp is formed with many small
steps of voltage. The voltage of one step is about 18.75mV
in VFB, and the period of one step is about 16/FOSC. This
method provides a controlled voltage rise and prevents
the large peak current to charge output capacitor.
Voltage (V)
VCC
VOUT
Time
t2 t3
t1
Figure 1.Soft-Start Interval
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APW7064
Application Information
multiple capacitors have to be parallel to achieve the
desired ESR value. A small decoupling capacitor in
parallel for bypassing the noise is also recommended,
and the voltage rating of the output capacitors also must
be considered. If tantalum capacitors are used, make
sure they are surge tested by the manufactures. If in doubt,
consult the capacitors manufacturer.
Output Voltage Selection
The output voltage can be programmed with a resistive
divider. Use 1% or better resistors for the resistive divider
is recommended. The FB pin is the inverter input of the
error amplifier, and the reference voltage is 1.2V. The
output voltage is determined by:
æ
ç
è
ö
÷
÷
ø
ROUT
RGND
ç
VOUT = 1.2´ 1+
Input Capacitor Selection
Where ROUT is the resistor connected from VOUT to FB and
RGND is the resistor connected from FB to GND.
The input capacitor is chosen based on the voltage rating
and the RMS current rating. For reliable operation, select
the capacitor voltage rating to be at least 1.3 times higher
than the maximum input voltage. The maximum RMS
current rating requirement is approximately IOUT/2,
where IOUT is the load current. During power up, the input
capacitors have to handle large amount of surge current.
If tantalum capacitors are used, make sure they are surge
tested by the manufactures. If in doubt, consult the
capacitors manufacturer. For high frequency decoupling,
a ceramic capacitor 1mF can be connected between the
drain of upper MOSFET and the source of lower MOSFET.
Output Inductor Selection
The inductor value determines the inductor ripple current
and affects the load transient response. Higher inductor
value reduces the inductor’s ripple current and induces
lower output ripple voltage. The ripple current and ripple
voltage can be approximated by:
V - VOUT VOUT
IN
IRIPPLE
=
´
FS ´ L
DVOUT = IRIPPLE ´ ESR
V
IN
where FS is the switching frequency of the regulator.
MOSFET Selection
Although increase of the inductor value reduces the ripple
current and voltage, a tradeoff will exist between the
inductor’s ripple current and the regulator load transient
response time.
The selection of the N-channel power MOSFETs are
determined by the RDS(ON), reverse transfer capacitance
(CRSS) and maximum output current requirement. There
are two components of loss in the MOSFETs: conduction
loss and transition loss. For the upper and lower
MOSFET, the losses are approximately given by the
following:
A smaller inductor will give the regulator a faster load
transient response at the expense of higher ripple current.
The maximum ripple current occurs at the maximum
input voltage. A good starting point is to choose the
ripple current to be approximately 30% of the maximum
output current. Once the inductance value has been
chosen, select an inductor that is capable of carrying
the required peak current without going into saturation.
In some types of inductors, especially core that is
made of ferrite, the ripple current will increase abruptly
when it saturates. This will result in a larger output ripple
voltage.
PUPPER =IOUT 2(1+ TC )(RDS(ON) )D + (0.5)( IOUT )(V )( tSW )FS
IN
P
LOWER =IOUT2(1+ TC)(RDS(ON))(1-D)
Where IOUT is the load current
TC is the temperature dependency of RDS(ON)
FS is the switching frequency
tSW is the switching interval
D is the duty cycle
Note that both MOSFETs have conduction loss while the
upper MOSFET include an additional transition loss. The
switching internal, tSW, is the function of the reverse trans-
fer capacitance CRSS. The (1+TC) term is to factor in
the temperature dependency of the RDS(ON) and can be
extracted from the “RDS(ON) vs Temperature” curve of the
power MOSFET.
Output Capacitor Selection
Higher capacitor value and lower ESR reduce the output
ripple and the load transient drop. Therefore, selecting
high performance low ESR capacitors is intended for
switching regulator applications. In some applications,
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APW7064
Application Information (Cont.)
PWM Compensation
The PWM modulator is shown in Figure 5. The input is
the output of the error amplifier and the output is the
PHASE node. The transfer function of the PWM modulator
is given by:
The output LC filter of a step down converter introduces
a double pole, which contributes with -40dB/decade gain
slope and 180 degrees phase shift in the control loop. A
compensation network among COMP, FB, and VOUT
should be added. The compensation network is shown
in Figure 6. The output LC filter consists of the output
inductor and output capacitors. The transfer function of
V
IN
GAINPWM
=
DVOSC
VIN
Driver
OSC
PWM
Comparator
the LC filter is given by:
ΔVOSC
1+ s´ ESR´ COUT
s2 ´ L´ COUT + s´ ESR´ COUT +1
GAINLC
=
PHASE
Output of
Error Amplifier
The poles and zero of this transfer functions are:
1
F
=
LC
Driver
Figure 5. The PWM Modulator
2´ p ´ L´ COUT
1
F
=
ESR
The compensation network is shown in Figure 6. It
provides a close loop transfer function with the highest
zero crossover frequency and sufficient phase margin.
The transfer function of error amplifier is given by:
2´ p ´ ESR´ COUT
The FLC is the double poles of the LC filter, and FESR is the
zero introduced by the ESR of the output capacitor.
VPHASE
L
VOUT
1
1
æ
ö
// R2 +
ç
÷
VCOMP
VOUT
sC1
sC2
è
ø
GAINAMP
=
=
1
æ
ö
R1// R3 +
ç
÷
ø
COUT
ESR
sC3
è
æ
ö
1
1
æ
ö
ç
´ s +
÷
÷
s +
ç
è
÷
ç
R2´ C2
(
R1+ R3
)
´ C3
R1+ R3
ø
è
ø
=
´
C1+ C2
1
R1´ R3´ C1
æ
ö æ
´ s +
÷ ç
ø è
ö
s s +
ç
÷
R2´ C1´ C2
R3´ C3
è
ø
Figure 3. The Output LC Filter
The poles and zeros of the transfer function are:
1
FLC
FZ1
=
2´ p ´ R2´ C2
1
-40dB/dec
FZ2
=
2´ p ´
(
R1+ R3
)
´ C3
1
F
=
=
P1
C1´ C2
æ
ö
÷
ø
2´ p ´ R2´
ç
FESR
C1+ C2
è
1
F
P2
2´ p ´ R3´ C3
-20dB/dec
C1
C
R3
3
R2
C2
VOUT
Frequency(Hz)
FB
VCOMP
R1
Figure 4. The LC Filter GAIN and Frequency
VREF
Figure 6. Compensation Network
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Copyright ã ANPEC Electronics Corp.
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Rev. A.3 - Aug., 2009
APW7064
Application Information (Cont.)
PWM Compensation (Cont.)
The closed loop gain of the converter can be written as:
GAINLC X GAINPWM X GAINAMP
FZ1 FZ2 FP1
FP2
Figure 7. shows the asymptotic plot of the closed loop
converter gain, and the following guidelines will help to
design the compensation network. Using the below
guidelines should give a compensation similar to the
curve plotted. A stable closed loop has a -20dB/ decade
slope and a phase margin greater than 45 degree.
Compensation
Gain
20log
(R2/R1)
20log
(VIN/ΔVOSC
)
1.Choose a value for R1, usually between 1K and 5K.
2.Select the desired zero crossover frequency
FLC
Converter
Gain
FESR
FO :(1/5 ~1/10) XFS > FO > F
ESR
PWM & Filter
Gain
Use the following equation to calculate R2:
DVOSC FO
Frequency(Hz)
Figure 7. Converter Gain and Frequency
R2 =
´
´ R1
V
F
LC
IN
3.Place the first zero FZ1 before the output LC filter double
pole frequency FLC.
FZ1 =0.75 X F
LC
Calculate the C2 by the equation:
1
C2 =
2´ p ´ R2´ FLC ´ 0.75
4.Set the pole at the ESR zero frequency FESR
=F
:
F
P1
ESR
Calculate the C1 by the equation:
C2
C1=
2´ p ´ R2´ C2´ FESR - 1
5.Set the second pole FP2 at the half of the switching
frequency and also set the second zero FZ2 at the output
LC filter double pole FLC. The compensation gain should
not exceed the error amplifier open loop gain, check the
compensation gain at FP2 with the capabilities of the
error amplifier.
FP2 = 0.5 X FS
FZ2 =F
LC
Combine the two equations will get the following component
calculations:
R1
R3 =
FS
- 1
2´ F
LC
1
C3 =
p ´ R3´ FS
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Rev. A.3 - Aug., 2009
APW7064
Layout Consideration
In any high switching frequency converter, a correct layout
is important to ensure proper operation of the regulator.
With power devices switching at 200kHz,the resulting
current transient will cause voltage spike across the
interconnecting impedance and parasitic circuit
elements. As an example, consider the turn-off transition
of the PWM MOSFET. Before turn-off, the MOSFET is
carrying the full load current. During turn-off, current stops
flowing in the MOSFET and is free-wheeling by the lower
MOSFET and parasitic diode. Any parasitic inductance
of the circuit generates a large voltage spike during the
switching interval. In general, using short, wide printed
circuit traces should minimize interconnecting impedances
and the magnitude of voltage spike. And signal and power
grounds are to be kept separate till combined using
ground plane construction or single point grounding.
Figure 8. illustrates the layout, with bold lines indicating
high current paths; these traces must be short and wide.
Components along the bold lines should be placed lose
together. Below is a checklist for your layout:
- The drain of the MOSFETs (VIN and PHASE nodes)
should be a large plane for heat sinking.
APW7064
VIN
VCC
BOOT
L
O
A
UGATE
D
PHASE
LGATE
VOUT
Figure 8. Layout Guidelines
- Keep the switching nodes (UGATE, LGATE, and
PHASE) away from sensitive small signal nodes
since these nodes are fast moving signals. Therefore,
keep traces to these nodes as short as possible.
- The traces from the gate drivers to the MOSFETs
(UGATE and LGATE) should be short and wide.
- Place the source of the high-side MOSFET and the
drain of the low-side MOSFET as close as possible.
Minimizing the impedance with wide layout plane
between the two pads reduces the voltage bounce of
the node.
- Decoupling capacitor, compensation component,
the resistor dividers, and boot capacitors should
be close their pins. (For example, place the
decoupling ceramic capacitor near the drain of the
high-side MOSFET as close as possible. The bulk
capacitors are also placed near the drain).
- The input capacitor should be near the drain of the
upper MOSFET; the output capacitor should be near
the loads. The input capacitor GND should be close
to the output capacitor GND and the lower MOSFET
GND.
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Rev. A.3 - Aug., 2009
APW7064
Package Information
SOP-8P
D
SEE VIEW A
D1
THERMAL
PAD
c
b
e
GAUGE PLANE
SEATING PLANE
L
VIEW A
SOP-8P
S
Y
M
B
O
L
MILLIMETERS
INCHES
MIN.
MAX.
1.60
MIN.
MAX.
0.063
0.006
A
0.000
0.049
0.012
0.007
0.189
0.098
0.228
0.150
0.079
0.15
A1
A2
0.00
1.25
0.31
0.17
4.80
2.50
5.80
3.80
2.00
b
0.020
0.010
0.197
0.138
0.244
0.157
0.118
0.51
0.25
5.00
3.50
6.20
4.00
3.00
c
D
D1
E
E1
E2
e
h
L
1.27 BSC
0.050 BSC
0.010
0.016
0oC
0.020
0.050
8oC
0.25
0.40
0.50
1.27
8oC
0oC
0
Note : 1. Followed from JEDEC MS-012 BA.
2. Dimension "D" does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side .
3. Dimension "E" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
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Rev. A.3 - Aug., 2009
APW7064
Carrier Tape & Reel Dimensions
P0
P2
P1
OD0
A
K0
A0
A
OD1
B
B
SECTION A-A
SECTION B-B
d
T1
Application
SOP-8P
A
H
T1
12.4+2.00 13.0+0.50
-0.00 -0.20
P2 D0
C
d
D
W
E1
F
330.0±2.00 50 MIN.
1.5 MIN.
D1
20.2 MIN. 12.0±0.30 1.75±0.10
5.5±0.05
K0
P0
P1
T
A0
B0
1.5+0.10
-0.00
0.6+0.00
-0.40
4.0±0.10
8.0±0.10
2.0±0.05
1.5 MIN.
6.40±0.20 5.20±0.20 2.10±0.20
(mm)
Devices Per Unit
Package Type
SOP-8P
Unit
Quantity
2500
Tape & Reel
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Rev. A.3 - Aug., 2009
APW7064
Taping Direction Information
SOP-8P
USER DIRECTION OF FEED
Classification Profile
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Rev. A.3 - Aug., 2009
APW7064
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
Preheat & Soak
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
Temperature min (Tsmin
)
Temperature max (Tsmax
)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
3 °C/second max.
3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL)
183 °C
60-150 seconds
217 °C
60-150 seconds
Peak package body Temperature
(Tp)*
See Classification Temp in table 1
20** seconds
See Classification Temp in table 2
30** seconds
Time (tP)** within 5°C of the specified
classification temperature (Tc)
Average ramp-down rate (Tp to Tsmax
)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Volume mm3
350
Package
Thickness
<2.5 mm
³ 2.5 mm
Volume mm3
<350
235 °C
220 °C
220 °C
220 °C
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
Volume mm3
Volume mm3
350-2000
260 °C
Volume mm3
<350
260 °C
260 °C
250 °C
>2000
260 °C
245 °C
245 °C
1.6 mm – 2.5 mm
³ 2.5 mm
250 °C
245 °C
Reliability Test Program
Test item
SOLDERABILITY
HOLT
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
Description
5 Sec, 245°C
1000 Hrs, Bias @ 125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
PCT
TCT
HBM
MM
VMM≧200V
10ms, 1tr≧100mA
Latch-Up
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Rev. A.3 - Aug., 2009
APW7064
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright ã ANPEC Electronics Corp.
Rev. A.3 - Aug., 2009
19
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