APW7067NQAE-TUL [ANPEC]
Synchronous Buck PWM and Linear Controller; 同步降压PWM和线性控制器
| 型号： | APW7067NQAE-TUL |
| 厂家： | 
ANPEC ELECTRONICS COROPRATION |
| 描述： | Synchronous Buck PWM and Linear Controller |
| 文件： | 总27页 (文件大小：1591K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APW7067N
Synchronous Buck PWM and Linear Controller
General Description
Features
The APW7067N integrates synchronous buck PWM
and linear controller, as well as monitoring and pro-
tection functions into a single package. The synchro-
nous PWM controller drives dual N-channel MOSFETs,
which provides one controlled power output with under-
·
Provided Two Regulated Voltages
- Synchronous Buck Converter
- Linear Regulator
·
·
Single 12V Power Supply Required
Excellent Both Output Voltage Regulation
- 0.8V Internal Reference
voltage and over-current protections. Linear controller
drives an external N-channel MOSFET with under-volt-
age protection.
- ±1% Over Line Voltage and Temperature
Integrated Soft-Start for PWM and Linear Outputs
Programmable FrequencyRange
from 150 kHz to 1000kHz
TheAPW7067N provides excellent regulation for output
load variation. An internal 0.8V temperature-compensated
reference voltage is designed to meet the requirement
of low output voltage applications. The switching
frequency is adjustable from 150kHz to 1000kHz.
·
·
·
·
·
Voltage Mode PWM Control Design and
Up to 89% (Typ.) Duty Cycle
The APW7067N with excellent protection functions:
POR, OCP and UVP. The Power-On Reset (POR)
circuit can monitor VCC12 supply voltage exceeds
its threshold voltage while the controller is running,
and a built-in digital soft-start provides both outputs
with controlled rising voltage. The Over-Current Protection
(OCP) monitors the output current by using the voltage
drop across the lower MOSFET’s RDS(ON), comparing
with internal VOCP (0.25V), eliminating the need for a
current sensing resister. When the output current
reaches the trip point, the controller will shutdown the
IC directly, and latch the converter’s output. The
Under-Voltage Protection (UVP) monitors the voltages
of FB and FBL pins for short-circuit protection. When
the VFB or VFBL is less than 50% of VREF, the controller
will shutdown the IC directly.
Under-Voltage Protection for PWM and Linear
Output
Over-Current Protection for PWM Output
- Sense Low-Side MOSFET’s RDS(ON)
SOP-14, QSOP-16 and QFN-16 packages
Lead FreeAvailable (RoHS Compliant)
·
·
Applications
·
Graphic Cards
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright ã ANPEC Electronics Corp.
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Rev. A.1 - Jun., 2006
APW7067N
Pinouts
16 15 14 13
BOOT
FS_DIS
COMP
FB
UGATE
PHASE
PGND
LGATE
NC
BOOT
FS_DIS
COMP
FB
UGATE
PHASE
PGND
LGATE
NC
1
2
3
4
5
6
7
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
COMP
1
2
12
11
PGND
Metal
GND Pad
(Bottom)
FB
LGATE
DRIVE
FBL
DRIVE
FBL
DRIVE
3
4
10
9
NC
NC
NC
NC
GND
VCC12
GND
VCC12
VCC12
FBL
8
GND
5
6
7
8
SOP-14
TOP VIEW
QSOP-16
TOP VIEW
QFN-16
TOP VIEW
Ordering and Marking Information
Package Code
K : SOP - 14 M : QSOP - 16
Temp. Range
E : -20 to 70 C
Handling Code
TU : Tube
APW7067N
QA : QFN - 16
Lead Free Code
Handling Code
Temp. Range
Package Code
°
TR : Tape & Reel
TY : Tray (for QFN only)
Lead Free Code
L : Lead Free Device
Blank : Original Device
APW7067N
XXXXX
APW7067N K :
APW7067N M :
APW7067N Q :
XXXXX - Date Code
XXXXX - Date Code
XXXXX - Date Code
APW7067N
XXXXX
APW7067N
XXXXX
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate
termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldering
operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C
for MSL classification at lead-free peak reflow temperature.
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Rev. A.1 - Jun., 2006
APW7067N
Block Diagram
VCC12
Power-On
Reset
Regulator
BOOT
GND
Sense Low Side
UGATE
PHASE
VREF
(0.8V)
10V
O.C.P
Comparator
U.V.P
Comparator
Soft Start
and
Fault Logic
VOCP
0.25V
50%VREF
:
2
Gate Control
LGATE
PGND
Error
Amp 1
PWM
Comparator
U.V.P
Comparator
FBL
10V
:
2
50%VREF
DRIVE
VREF
Error
Amp 2
Oscillator
FS_DIS
Sawtooth
wave
VREF
FB
COMP
Absolute Maximum Ratings
Symbol
VCC12
BOOT
Parameter
Rating
Unit
V
VCC12 to GND
-0.3 to +16
-0.3 to +16
BOOT to PHASE
V
UGATE to PHASE <400ns pulse width
>400ns pulse width
-5 to BOOT+5
-0.3 to BOOT+0.3
UGATE
LGATE
V
V
LGATE to PGND <400ns pulse width
>400ns pulse width
-5 to VCC12+5
-0.3 to VCC12+0.3
PHASE to GND
<400ns pulse width
>400ns pulse width
-5 to +21
-0.3 to 16
PHASE
DRIVE
V
V
V
DRIVE to GND
12
FB, FBL, COMP,
FS_DIS
FB, FBL, COMP, FS_DIS to GND
-0.3 to 7
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Rev. A.1 - Jun., 2006
APW7067N
Absolute Maximum Ratings (Cont.)
Symbol
Parameter
Rating
Unit
PGND
TJ
PGND to GND
-0.3 to +0.3
-20 to +150
-65 ~ 150
300
V
Junction Temperature Range
Storage Temperature
°C
°C
°C
KV
TSTG
TSDR
VESD
Soldering Temperature (10 Seconds)
Minimum ESD Rating
±2
NOTE1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
NOTE2: The device is ESD sensitive. Handling precautions are recommended.
Recommended Operating Conditions
Symbol
VCC12
VIN1
Parameter
Rating
10.8 to 13.2
2.9 to 13.2
0.9 to 5
Unit
V
IC Supply Voltage
Converter Input Voltage
Converter Output Voltage
Converter Output Current
Linear Output Current
V
VOUT1
IOUT1
IOUT2
TA
V
0 to 30
A
0 to 3
A
Ambient Temperature Range
Junction Temperature Range
-20 to 70
-20 to 125
°C
°C
TJ
Electrical Characteristics
Unless otherwise specified, these specifications apply over VCC12 = 12V, and TA =-20 ~ 70°C. Typical values
are at TA= 25°C.
APW7067N
Symbol
Parameter
Test Conditions
Unit
Min
Typ
Max
INPUT SUPPLY CURRENT
VCC12 Supply Current
(Shutdown mode)
ICC12
UGATE, LGATE and DRIVE open;
FS_DIS = GND
4
6
mA
mA
UGATE, LGATE and DRIVE open;
FOSC = 600kHz
VCC12 Supply Current
16
24
POWER-ON RESET
Rising VCC12 Threshold
Falling VCC12 Threshold
7.7
7.2
7.9
7.4
8.1
7.6
V
V
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Rev. A.1 - Jun., 2006
APW7067N
Electrical Characteristics (Cont.)
Unless otherwise specified, these specifications apply over VCC12 = 12V, and TA =-20 ~ 70°C. Typical values
are at TA= 25°C.
APW7067N
Symbol
Parameter
Test Conditions
Unit
Min
Typ Max
OSCILLATOR
Accuracy
-15
255
510
+15
%
kHz
kHz
V
FOSC Oscillator Frequency
FOSC Oscillator Frequency
VOSC Ramp Amplitude
Duty Maximum Duty Cycle
REFERENCE
RFS_DIS = 110k ohms
300
600
1.5
89
345
690
RFS_DIS = 47k ohms
(nominal 1.2V to 2.7V) (NOTE3)
%
VREF Reference Voltage
for Error Amp1 and Amp2
0.792 0.80 0.808
V
%
%
%
+1
1
Reference Voltage Tolerance
-1
PWM Load Regulation
Linear Load Regulation
IOUT1 = 0 to 10A
IOUT2 = 0 to 3A
1
PWM ERROR AMPLIFIER
Gain Open Loop Gain
RL = 10k, CL = 10pF (NOTE3)
RL = 10k, CL = 10pF (NOTE3)
RL = 10k, CL = 10pF (NOTE3)
VFB = 0.8V
93
20
8
dB
MHz
V/us
uA
GBWP Open Loop Bandwidth
SR
Slew Rate
FB Input Current
0.1
5
1
VCOMP COMP High Voltage
VCOMP COMP Low Voltage
ICOMP COMP Source Current
V
0
V
COMP = 2V
COMP = 2V
12
12
mA
mA
ICOMP COMP Sink Current
GATE DRIVERS
IUGATE Upper Gate Source Current
2.5
2
A
A
BOOT = 12V,
UGATE-PHASE = 2V
IUGATE Upper Gate Sink Current
ILGATE Lower Gate Source Current
ILGATE Lower Gate Sink Current
2.5
3.5
A
VCC12 = 12V, LGATE = 2V
A
RUGATE Upper Gate Source Impedance BOOT = 12V, IUGATE = 0.1A
RUGATE Upper Gate Sink Impedance BOOT = 12V, IUGATE = 0.1A
RLGATE Lower Gate Source Impedance VCC12 = 12V, ILGATE = 0.1A
2.25 3.375
0.7 1.05
2.25 3.375
W
W
W
W
nS
RLGATE Lower Gate Sink Impedance
TD Dead Time
VCC12 = 12V, ILGATE = 0.1A
0.4
20
0.6
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Rev. A.1 - Jun., 2006
APW7067N
Electrical Characteristics (Cont.)
Unless otherwise specified, these specifications apply over VCC12 = 12V, and TA =-20 ~ 70°C. Typical values
are at TA= 25°C.
APW7067N
Symbol
Parameter
Test Conditions
Unit
Min
Typ Max
LINEAR REGULATOR
Open Loop Gain
RL = 10k, CL = 10pF (NOTE3)
RL = 10k, CL = 10pF (NOTE3)
RL = 10k, CL = 10pF (NOTE3)
VFBL= 0.8V
dB
MHz
V/us
uA
Gain
GBWP
SR
70
19
6
Open Loop Bandwidth
Slew Rate
FBL Input Current
DRIVE High Voltage
DRIVE Low Voltage
DRIVE Source Current
DRIVE Sink Current
0.1
10
0
1
V
VDRIVE
VDRIVE
IDRIVE
IDRIVE
V
DRIVE = 5V
DRIVE = 5V
mA
mA
4
3
PROTECTION
FB Under Voltage Protection
Trip Point
VFB-UV
Percent of VREF
Percent of VREF
50
%
%
FBL Under Voltage Protection
Trip Point
VFBL-UV
50
230
250
270 mV
VOCP OCP Voltage
SOFT START
FOSC = 600kHz
FOSC = 300kHz
2.1
4.2
ms
ms
TSS
Internal Soft-Start Interval (NOTE3)
NOTE3:Guaranteed by design.
Typical Application Circuit
C1
2.2nF
VIN1
12V
Q3
ON/OFF
CIN1
470uFx2
2N7002
R2
C2
Q1
APM2509
0.01uF
3.9K
L
VOUT1
1.2V
R1
C4
VOUT1
1uH
1.5K
0.1uF
R3
C3
22nF
UGATE
22W
1
2
3
4
5
6
7
14
13
12
11
10
9
BOOT
FS_DIS
COMP
FB
RFS_DIS
COUT1
470uFx2
PHASE
PGND
RGND1
3K
VIN2
3.3V
C6
2.2nF
Q2
LGATE
NC
APM2506
CIN2
12V
Q4
APM3055
470uF
R6
2.2W
DRIVE
FBL
C5
R5
R7
NC
2.2W
VCC12
8
GND
R4
VOUT2
2.5V
C7
1uF
2.5K
APW7067N
COUT2
470uF
RGND2
1.17K
* C5, R5 for specific application
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Rev. A.1 - Jun., 2006
APW7067N
Function Pin Descriptions
VCC12
- downed immediately.
Power supply input pin. Connect a nominal 12V power UGATE
supplyto this pin. The power-on reset function monitors
This pin is the gate driver for the upper MOSFET of
the input voltage at this pin. It is recommended that a
decoupling capacitor (1 to 10mF) be connected toGND
for noise decoupling.
PWM output.
LGATE
This pin is the gate driver for the lower MOSFET of
PWM output.
BOOT
This pin provides the bootstrap voltage to the upper
gate driver for driving the N-channel MOSFET. An
external capacitor from PHASE to BOOT, an internal
diode, and the power supplyvaltage VCC12, generates
thebootstrap voltagefor theupper gatediver (UGATE).
DRIVE
This pin drives the gate of an external N-channel
MOSFET for linear regulator. It is also used to set the
compensation for some specific applications, for
example, with low values of output capacitance and
ESR.
PHASE
This pin is the return path for the upper gate driver.
Connect this pin to the upper MOSFET source, and
connect a capacitor to BOOT for the bootstrap voltage.
This pin is also used to monitor the voltage drop across
the lower MOSFET for over-current protection.
FBL
This pin is the inverting input of the linear regulator
error amplifier. It is used to set the output voltage.
This pin is also monitored for under-voltage protection,
when theFBL voltage is under 50% of reference voltage
(0.4V), both outputs will be shutdown immediately.
GND
This pin is the signal ground pin. Connect theGNDpin
to a good ground plane.
FS_DIS
This pin be allowed to adjust the switching frequency.
Connect a resistor from FS_DIS pin to the ground to
increase the switching frequency. This pin also provides
shutdown function, use an open drain logic signal to
pull this pin low to disable both outputs, leave open to
enable both outputs.
PGND
This pin is the power ground pin for the lower gate
driver. It should be tied to GND pin on the board.
COMP
This pin is the output of PWM error amplifier. It is
used to set the compensation components.
FB
ThispinistheinvertinginputofthePWMerror amplifier.
It is used to set the output voltage and the compensation
components. This pin is also monitored for under-
voltage protection, when the FB voltage is under 50%
of reference voltage (0.4V), both outputs will be shut
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Rev. A.1 - Jun., 2006
APW7067N
Typical Characteristics
PowerOff
Power On
VCC12=12V,Vin1=12V,Vin2=3.3V
VCC12=12V,Vin1=12V,Vin2=3.3V
Vo1=1.2V,Vo2=2.5V,L=1uH
Vo1=1.2V,Vo2=2.5V,L=1uH
CH1
CH2
CH3
CH1
CH2
CH3
CH1: VCC12 (10V/div)
CH2: Vo1 (1V/div)
CH3: Vo2 (2V/div)
Time: 5ms/div
CH1: VCC12 (10V/div)
CH2: Vo1 (1V/div)
CH3: Vo2 (2V/div)
Time: 5ms/div
EN
Shutdown(FS_DIS=GND)
VCC12=12V,Vin1=12V,Vin2=3.3V
Vo1=1.2V,Vo2=2.5V,L=1uH
Vcc12=12V,Vin1=12V,Vin2=3.3V
Vo1=1.2V,Vo2=2.5V,L=1uH
CH1
CH2
CH1
CH2
CH3
CH4
CH3
CH4
CH1: FS_DIS (1V/div)
CH2:Drive (5V/div)
CH3: Vo1 (1V/div)
CH4: Vo2 (2V/div)
Time: 5ms/div
CH1: FS_DIS (1V/div)
CH2:Drive (5V/div)
CH3: Vo1 (1V/div)
CH4: Vo2 (2V/div)
Time: 5ms/div
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Rev. A.1 - Jun., 2006
APW7067N
Typical Characteristics
(Cont.)
UGATE Falling
UGATE Rising
Vcc12=12V,Vin1=12V, Vo1=1.2V
Vcc12=12V,Vin1=12V,Vo1=1.2V
CH1
CH1
CH2
CH3
CH2
CH3
CH1: Ug (20V/div)
CH1: Ug (20V/div)
CH2: Phase (10V/div)
CH3: Lg (10V/div)
Time: 50ns/div
CH2: Phase (10V/div)
CH3: Lg (10V/div)
Time: 50ns/div
UVP_PWM Controller(FB< 0.4V)
UVP_Linear Regulator(FBL< 0.4V)
VCC12=12V,Vin1=12V
VCC12=12V,Vin2=3.3V
Vo2=2.5V,Io2=3A
Vo1=1.2V,L=1uH,Io1=10A
CH1
CH1
CH2
CH3
CH2
CH3
CH4
CH1: FB (1V/div)
CH2: Vo1 (1V/div)
CH3: Ug (20V/div)
CH4: COMP (5V/div)
Time: 50us/div
CH1: FBL (1V/div)
CH2:Drive (5V/div)
CH3: Vo2 (2V/div)
Time: 100us/div
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Rev. A.1 - Jun., 2006
APW7067N
Typical Characteristics
(Cont.)
Load Transient Response(PWM Controller)
- VCC12=12V, Vin1=12V, Vo1=2V, Fosc=300KHz
- Io1 slew rate= ± 10 A/us
Io1=0Aà10Aà0A
Io1=10Aà0A
Io1=0Aà10A
CH1
CH1
CH1
CH2
CH3
CH2
CH3
CH2
CH3
CH1: Vo1 (100mV/div,AC)
CH2: Ug (20V/div)
CH1: Vo1 (100mV/div,AC)
CH2: Ug (20V/div)
CH1: Vo1 (100mV/div,AC)
CH2: Ug (20V/div)
CH3: Io1(10A/div)
CH3: Io1(10A/div)
CH3: Io1(10A/div)
Time: 20us/div
Time: 50us/div
Time: 20us/div
Load Transient Response(Linear Regulator)
- VCC12=12V, Vin2=3.3V, Vo2=2.5V
- Io2 slew rate= ± 3A/us
Io2=0Aà3Aà0A
Io2=3Aà0A
Io2=0Aà3A
CH1
CH1
CH1
CH2
CH2
CH2
CH1: Vo2 (100mV/div,AC)
CH2: Io2(2A/div)
CH1: Vo2 (100mV/div,AC)
CH2: Io2(2A/div)
CH1: Vo2 (100mV/div,AC)
CH2: Io2(2A/div)
Time: 1us/div
Time: 10us/div
Time: 1us/div
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Rev. A.1 - Jun., 2006
APW7067N
Typical Characteristics
(Cont.)
Short Test after Power Ready
Over Current Protection
VCC12=12V, Vin1=12V,
Vo1=1.2V, L=1uH,
Co=470uH*2,
VCC12=12V, Vin1=12V,
Vo1=1.2V, L=1uH,
Co=470uH*2,
L_Side_Rds(on)=17mΩ
L_Side_Rds(on)=17mΩ
CH1
CH1
CH2
CH3
CH2
CH3
CH4
CH4
CH1: Vo1 (1V/div)
CH2:Drive (5V/div)
CH3: Ug (20V/div)
CH4: IL (10A/div)
Time: 50us/div
CH1: Vo1 (1V/div)
CH2:Drive (5V/div)
CH3: Ug (20V/div)
CH4: IL (10A/div)
Time: 50us/div
Short Test before Power On
VREF vs. Junction Temperature
0.804
0.8035
0.803
VCC12=12V, Vin1=12V,Vo1=1.2V, L=1uH,
Co=470uH*2, L_Side_Rds(on)=17mΩ
CH1
CH2
0.8025
0.802
VREF
0.8015
0.801
CH3
CH4
0.8005
-40
-20
0
20
40
60
80
100 120
CH1: VCC12 (10V/div)
CH2: Vo1 (1V/div)
CH3: Ug (20V/div)
CH4: IL (10A/div)
Time: 2ms/div
JunctionTemperature (°C)
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Rev. A.1 - Jun., 2006
APW7067N
Typical Characteristics
(Cont.)
UGATE Source Current vs. UGATE Voltage
UGATE Sink Current vs. UGATE Voltage
3
3.5
3
2.5
2
2.5
VBOOT=12V
Phase=0V
VBOOT=12V
Phase=0V
2
1.5
1
1.5
1
0.5
0
0.5
0
0
0.5
1
1.5
2
2.5
3
0
2
4
6
8
10
12
UGATE Voltage (V)
UGATE Voltage (V)
LGATE Sink Current vs. LGATE Voltage
LGATE Source Current vs. LGATE Voltage
7
6
5
4
3
2
1
0
3
2.5
VCC=12V
VCC=12V
2
1.5
1
0.5
0
0
2
4
6
8
10
12
0
1
2
3
4
LGATE Voltage (V)
LGATE Voltage(V)
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Rev. A.1 - Jun., 2006
APW7067N
Function Descriptions
Voltage(V)
Power On Reset (POR)
The Power-On Reset (POR) function ofAPW7067N
continually monitors the input supply voltage (VCC12),
ensures the supply voltage exceed its rising POR
threshold voltage. The POR function initiates soft-start
interval operation while VCC12 voltages exceed their
POR threshold and inhibits operation under disabled
status.
VCC12
POR
VOUT1
VOUT2
Soft-Start
Figure 1. shows the soft-start interval. When VCC12
reaches the rising POR threshold voltage, the internal
reference voltage is controlled to follow a voltage pro-
portional to the soft-start voltage. The soft-start inter-
val is variable by the oscillator frequency. The formu-
lation is given by:
t0
t1
t2
Time
Figure 1. Soft-Start Interval
Voltage(V)
1
FB
TSS = D(t2 - t1) =
´ 1280
FOSC
Figure 2. shows more detail of the FB and FBL voltage
ramps. The FB and FBL voltage soft-start ramps are
formed with many small steps of voltage. The voltage
of one step is about 20mV in FB and FBL, and the
period of one step is about 32/FOSC. This method
provides a controlled voltage rise and prevents the
large peak current to charge the output capacitors.
The FB voltage compares the FBLvoltage to shift to an
earlier time the establishment as Figure2. The voltage
estabilishment time difference for FB and FBL is
variable by the oscillator. The formulation is given by:
FBL
20mV
32/Fosc
32/Fosc
20mV
Time
t3
t4
Figure 2. The Controlled Stepped FB and
FBL Voltage during Soft-Start
Over-Current Protection
The over-current protection monitors the output current
by using the voltage drop across the lower MOSFET’s
RDS(ON) and this voltage drop will be compared with the
internal0.25Vreferencevoltage. Whenthevoltagedrop
across the lower MOSFET’s RDS(ON) is larger than 0.25V,
an over-current condition is detected, the controller
will shutdown the IC directly, and latch the converter's
output.
1
1
D(t4 - t3) =
´ 320 = ´ TSS
FOSC
4
Copyright ã ANPEC Electronics Corp.
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Rev. A.1 - Jun., 2006
APW7067N
Function Descriptions
Over-Current Protection (Cont.)
shutdown the APW7067N PWM controller. In shut-
down mode, the UGATE and LGATE turn off and pull
to PHASE and GND respectively.
The threshold of the over current limit is given by:
VOCP (0.25V)
ILIMIT
=
Switching Frequency
RDS(ON)
(
Low _Side
)
The APW7067N provides the adjustable oscillator
switching frequency . The switching frequency is de-
termined by the value of RFS_DIS (from FS_DIS pin to
For the over-current is never occurred in the normal
operating load range; the variation of all parameters in
the above equation should be determined.
GND), the adjustable range from150kHz to 1000kHz .
Figure 3. shows how to select the resistor for the
desired frequency. If the IC is operated in higher
- The MOSFET’s RDS(ON) is varied by temperature
and gate to source voltage, the user should deter
mine the maximum RDS(ON) in manufacture’s
datasheet.
frequencies (ex. 600 kHz or above), the slope of
the curve is steep, and a small change in resis-
tance will have a big effect on the frequency. At
lower frequencies, the slope of the curve is much
less steep, even a large change in resistor value
doesn’t change the frequency too much. Figure 4.
shows more detail for the higher frequency and
Figure5. shows the lower frequency.
- The minimum VOCP should be used in the above
equation.
- Note that the ILIMIT is the current flow through the
lower MOSFET; ILIMIT must be greater than maximum
output current add the half of inductor ripple current.
Under Voltage Protection
1600
1400
1200
1000
800
600
400
200
0
The FB and FBL pin are monitored during converter
operation by their own Under Voltage (UV) comparator.
If the FB or FBL voltage drop below 50% of the
reference voltage (50% of 0.8V = 0.4V), a fault signal
is internally generated, and the device turns off both
high-side and low-side MOSFET and the converter’s
output is latched to be floating.
Shutdown and Enable
Pulling the FS_DIS voltage to GND by an open drain
transistor, shown in typical application circuit,
0
100
200
300
400
R ( K
500
600
700
800
)
W
Figure 3. Oscillator Frequency vs. R
FS-DIS
Copyright ã ANPEC Electronics Corp.
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Rev. A.1 - Jun., 2006
APW7067N
Function Descriptions (Conts)
Switching Frequency (Cont.)
500
1200
450
400
1000
350
300
250
800
600
400
200
150
100
50
150
250
350
450
R(K Ω)
550
650
750
0
10
20
30
40
50
60
70
80
R (K Ω)
Figure 4. Oscillator Frequency vs.R
(High Frequency)
Figure 5. Oscillator Frequency vs.R
(Low Frequency)
FS-DIS
FS-DIS
Application Information
Where R4 is the resistor connected from VOUT2 to
FBL and RGND2 is the resistor connected from FBL to
GND.
Output Voltage Selection
TheoutputvoltageofPWMconvertercanbeprogrammed
with a resistive divider. Use 1% or better resistors for
the resistive divider is recommended. The FB pin is
the inverter input of the error amplifier, and the reference
voltage is 0.8V. The output voltage is determined by:
Linear Regulator Input/Output Capacitor Selection
The input capacitor is chosen based on its voltage
rating. Under load transient condition, the input
capacitor will momentarily supply the required transient
current. The output capacitor for the linear regulator is
chosen to minimize any droop during load transient
condition. In addition, the capacitor is chosen based
on its voltage rating.
æ
ö
÷
÷
ø
R1
ç
VOUT1 = 0.8 ´ 1+
ç
è
RGND1
Where R1 is the resistor connected from VOUT1 to FB
and RGND1 is the resistor connected from FB to GND.
Linear Regulator Input/Output MOSFET Selection
The linear regulator output voltage VOUT2 is also set by
means of an external resistor divider. The FBL pin is
the inverter input of the error amplifier, and the reference
voltage is 0.8V. The output voltage is determined by:
The maximum DRIVE voltage is about 10V when
VCC12 is equal 12V. Since this pin drives an external
N-channel MOSFET, therefore the maximum output
voltage of the linear regulator is dependent upon the
VGS.
æ
ö
÷
÷
ø
R4
ç
VOUT2 = 0.8 ´ 1+
ç
è
RGND2
VOUT2MAX = 10 - VGS
Copyright ã ANPEC Electronics Corp.
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Rev. A.1 - Jun., 2006
APW7067N
Application Information (Conts)
Another criterion is its efficiency of heat removal. The
power dissipated by the MOSFET is given by:
PHASE
L
OUTPUT1
Pd = IOUT2 x (VIN2 – VOUT2
)
COUT1
Where IOUT2 is the maximum load current, VOUT2 is the
nominal output voltage.
ESR
In some applications, heatsink might be required to
help maintain the junction temperature of the MOSFET
below its maximum rating.
Figure 6. The Output LC Filter
FLC
Linear Regulator Compensation Selection
-40dB/dec
The linear regulator is stable over all loads current.
However, thetransientresponsecanbefurtherenhanced
by connecting a RC network between the FBL and
DRIVE pin. Depending on the output capacitance and
load current of the application, the value of this RC
network is then varied.
FESR
-20dB/dec
PWM Compensation
Frequency(Hz)
The output LC filter of a step down converter introduces
a double pole, which contributes with -40dB/decade
gain slope and 180 degrees phase shift in the control
loop. A compensation network among COMP, FB and
VOUT1 should be added. The compensation network is
shown in Fig. 9. The output LC filter consists of the
output inductor and output capacitors. The transfer
function of the LC filter is given by:
Figure 7. The LC Filter GAIN and Frequency
The PWM modulator is shown in Figure 8. The input
is the output of the error amplifier and the output is the
PHASE node. The transfer function of the PWM
modulator is given by:
V
IN
GAINPWM
=
DVOSC
VIN1
1+ s´ ESR´ COUT1
s2 ´ L´ COUT1 + s´ ESR´ COUT1 +1
Driver
GAINLC
=
OSC
PWM
Comparator
ΔVOSC
The poles and zero of this transfer functions are:
1
PHASE
Output of
Error Amplifier
FLC
=
2 ´ p ´ L ´ COUT1
Driver
1
FESR
=
Figure 8. The PWM Modulator
2 ´ p ´ ESR ´ COUT1
The compensation network is shown in Figure 9. It
provides a close loop transfer function with the highest
zero crossover frequency and sufficient phase margin.
The FLC is the double poles of the LC filter, and FESR is
the zero introduced by the ESR of the output capacitor.
Copyright ã ANPEC Electronics Corp.
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Rev. A.1 - Jun., 2006
APW7067N
Application Information (Cont.)
PWM Compensation (Cont.)
1.Choose a value for R1, usually between 1K and 5K.
The transfer function of error amplifier is given by:
2.Select the desired zero crossover frequency FO:
(1/5 ~ 1/10) X FS >FO>FESR
1
1
æ
ö
÷
// R2+
ç
VCOMP
VOUT1
sC1
sC2
è
ø
GAINAMP
=
=
1
æ
ö
R1// R3 +
ç
÷
sC3
Use the following equation to calculate R2:
è
ø
æ
ö
1
1
æ
ö
÷
DVOSC
FO
s +
´ çs +
÷
÷
ç
ç
R2 =
´
´ R1
R2 ´ C2
(
R1+ R3
)
´ C3
R1+ R3
è
ø
è
ø
VIN
FLC
=
´
C1+ C2
1
R1´ R3 ´ C1
æ
ö æ
ö
s s +
´
s +
ç
÷ ç
÷
R2 ´ C1´ C2
R3 ´ C3
è
ø è
ø
3.Place the first zero FZ1 before the output LC filter
double pole frequency FLC.
The poles and zeros of the transfer function are:
1
FZ1 = 0.75 X FLC
FZ1
FZ2
FP1
=
2 ´ p ´ R2 ´ C2
Calculate the C2 by the equation:
1
1
=
C2 =
2 ´ p ´
(
R1 + R3 ´ C3
)
2 ´ p ´ R2 ´ FLC ´ 0.75
1
=
4.Set the pole at the ESR zero frequency FESR
FP1 = FESR
:
C1´ C2
æ
ö
÷
2´ p ´ R2 ´
ç
C1+ C2
è
ø
1
FP2
=
Calculate the C1 by the equation:
2 ´ p ´ R3 ´ C3
C2
C1 =
C1
2 ´ p ´ R2 ´ C2 ´ FESR - 1
R3
C3
R2
C2
5.Set the second pole FP2 at the half of the switching
frequency and also set the second zero FZ2 at the
output LC filter double pole FLC. The compensation
gain should not exceed the error amplifier open loop
gain, check the compensation gain at FP2 with the
capabilities of the error amplifier.
VOUT1
FB
VCOMP
R1
VREF
Figure 9. Compensation Network
The closed loop gain of the converter can be written
FP2 = 0.5 X FS
FZ2 = FLC
as:
GAINLC X GAINPWM X GAINAMP
Combine the two equations will get the following
component calculations:
Figure 10. shows the asymptotic plot of the closed
loop converter gain, and the following guidelines will
help to design the compensation network. Using the
below guidelines should give a compensation similar
to the curve plotted. A stable closed loop has a -20dB/
decade slope and a phase margin greater than 45
degree.
R1
R3 =
FS
- 1
2 ´ FLC
1
C3 =
p ´ R3 ´ FS
Copyright ã ANPEC Electronics Corp.
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Rev. A.1 - Jun., 2006
APW7067N
Application Information (Cont.)
PWM Compensation (Cont.)
starting point is to choose the ripple current to be
approximately 30% of the maximum output current.
Once the inductance value has been chosen, select
an inductor that is capable of carrying the required
peak current without going into saturation. In some
types of inductors, especially core that is made of
ferrite, the ripple current will increase abruptly when it
saturates. This will result in a larger output ripple
voltage.
FZ1 FZ2 FP1
FP2
Compensation
Gain
20log
(R2/R1)
20log
(VIN/ΔVOSC)
FLC
Output Capacitor Selection
FESR
Converter
Gain
Higher capacitor value and lower ESR reduce the
output ripple and the load transient drop. Therefore,
selecting high performance low ESR capacitors is
intended for switching regulator applications. In some
applications, multiple capacitors have to be parallel to
achieve the desired ESR value. A small decoupling
capacitor in parallel for bypassing the noise is also
recommended, and the voltage rating of the output
capacitors also must be considered. If tantalum
capacitors are used, make sure they are surge tested
by the manufactures. If in doubt, consult the capacitors
manufacturer.
PWM & Filter
Gain
Frequency(Hz)
Figure 10. Converter Gain and Frequency
Output Inductor Selection
The inductor value determines the inductor ripple
current and affects the load transient response. Higher
inductor value reduces the inductor’s ripple current and
induces lower output ripple voltage. The ripple current
and ripple voltage can be approximated by:
V
IN1 - VOUT1 VOUT1
IRIPPLE
=
´
FS ´ L
DVOUT1 = IRIPPLE ´ ESR
V
IN1
Input Capacitor Selection
The input capacitor is chosen based on the voltage
rating and the RMS current rating. For reliable
operation, select the capacitor voltage rating to be at
least 1.3 times higher than the maximum input voltage.
The maximum RMS current rating requirement is
approximately IOUT1/2, where IOUT1 is the load current.
During power up, the input capacitors have to handle
large amount of surge current. If tantalum capacitors
are used, make sure they are surge tested by the
manufactures. If in doubt, consult the capacitors
manufacturer. For high frequency decoupling, a ceramic
capacitor 1uF can be connected between the drain of
upper MOSFET and the source of lower MOSFET.
where Fs is the switching frequency of the regulator.
Although increase of the inductor value and frequency
reduces the ripple current and voltage, a tradeoff will
exist between the inductor’s ripple current and the
regulator load transient response time.
A smaller inductor will give the regulator a faster load
transient response at the expense of higher ripple
current. Increasing the switching frequency (FS) also
reduces the ripple current and voltage, but it will
increase the switching loss of the MOSFET and the
power dissipation of the converter. The maximum ripple
current occurs at the maximum input voltage. A good
Copyright ã ANPEC Electronics Corp.
18
www.anpec.com.tw
Rev. A.1 - Jun., 2006
APW7067N
Application Information (Cont.)
MOSFET Selection
The selection of the N-channel power MOSFETs are traces should minimize interconnecting imped-
determined by the RDS(ON), reverse transfer capacitance ances and the magnitude of voltage spike. And signal
(CRSS) and maximum output current requirement. There and power grounds are to be kept separate till
are two components of loss in the MOSFETs: combined using ground plane construction or single
conduction loss and transition loss. For the upper point grounding. Figure 11. illustrates the layout, with
and lower MOSFET, the losses are approximately bold lines indicating high current paths; these traces
given by the following:
must be short and wide. Components along the bold
lines should be placed lose together. Below is a
checklist for your layout:
PUPPER = IOUT1 (1+ TC)(RDS(ON))D + (0.5)( IOUT1)(V )( tSW)FS
IN1
PLOWER = IOUT1 (1+ TC)(RDS(ON))(1-D)
- The metal plate of the bottom of the packages
(QFN-16) must be soldered to the PCB and con-
nected to the GND plane on the backside through
several thermal vias.
Where IOUT1 is the load current
TC is the temperature dependency of RDS(ON)
FS is the switching frequency
tSW is the switching interval
- Keep the switching nodes (UGATE, LGATE and
PHASE) away from sensitive small signal nodes
since these nodes are fast moving signals.
Therefore, keep traces to these nodes as short as
possible.
D is the duty cycle
Note that both MOSFETs have conduction loss while
the upper MOSFET include an additional transition
loss. The switching internal, tSW, is a function of the
reverse transfer capacitance CRSS. The (1+TC) term is
to factor in the temperature dependency of the RDS(ON)
and can be extracted from the “R DS(ON) vs Temperature”
curve of the power MOSFET.
- The traces from the gate drivers to the MOSFETs
(UG, LG, DRIVE) should be short and wide.
- Place the source of the high-side MOSFET and
the drain of the low-side MOSFET as close as
possible. Minimizing the impedance with wide
layout plane between the two pads reduces the
voltage bounce of the node.
Layout Considerations
In any high switching frequency converter, a correct
layout is important to ensure proper operation of the
regulator. With power devices switching at 300KHz or
above, the resulting current transient will cause voltage
spike across the interconnecting impedance and
parasitic circuit elements. As an example, consider
the turn-off transition of the PWM MOSFET. Before
turn-off, the MOSFET is carrying the full load current.
During turn-off, current stops flowing in the MOSFET
and is free-wheeling by the lower MOSFET and
parasitic diode. Any parasitic inductance of the circuit
generates a large voltage spike during the switching
interval. In general, using short, wide printed circuit
- Decoupling capacitor, compensation component,
the resistor dividers and boot capacitors should
be close their pins. (For example, place the
decoupling ceramic capacitor near the drain of
the high-side MOSFET as close as possible. The
bulk capacitors are also placed near the drain).
- The input capacitor should be near the drain of
the upper MOSFET; the output capacitor should
be near the loads. The input capacitor GND should
be close to the output capacitor GND and the lower
Copyright ã ANPEC Electronics Corp.
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Rev. A.1 - Jun., 2006
APW7067N
Application Information (Cont.)
Layout Considerations (Cont.)
MOSFET GND.
- The drain of the MOSFETs (VIN1 and PHASE
nodes) should be a large plane for heat sinking.
APW7067N
VIN1
VCC12
VIN2
BOOT
L
O
A
D
DRIVE
UGATE
VOUT2
PHASE
FBL
L
O
LGATE
VOUT1
A
D
Figure 11. Layout Guidelines
Copyright ã ANPEC Electronics Corp.
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Rev. A.1 - Jun., 2006
APW7067N
Package Information
SOP – 14 (150mil)
C
D
A
GAUGE PLANE
SEATING PLANE
e
B
A1
L
Millimeters
Inches
Dim
Min.
1.477
0.102
0.331
0.191
8.558
3.82
Max.
Min.
0.058
0.004
0.013
0.0075
0.336
0.150
Max.
0.068
0.010
0.020
0.0098
0.344
0.157
A
A1
B
1.732
0.255
0.509
C
D
E
0.2496
8.762
3.999
e
1.274
0.050
H
L
5.808
0.382
0°
6.215
1.274
8°
0.228
0.015
0°
0.244
0.050
8°
q°
Copyright ã ANPEC Electronics Corp.
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Rev. A.1 - Jun., 2006
APW7067N
Package Information
QSOP-16
D
GAUGE
PLANE
E
E1
1
2
3
A
L
1
A1
b
e
Millimeters
Inches
Dim
Min.
1.35
0.10
0.20
4.80
5.79
3.81
Max.
1.75
0.25
0.30
5.00
6.20
3.99
Min.
0.053
0.004
0.008
0.189
0.228
0.150
Max.
A
A1
b
0.069
0.010
0.012
0.197
0.244
0.157
D
E
E1
e
0.635 TYP.
0.025 TYP.
0.41
1.27
L
0.016
0.050
f 1
0°
8°
0°
8°
Copyright ã ANPEC Electronics Corp.
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Rev. A.1 - Jun., 2006
APW7067N
Package Information
QFN-16
e
b
D
D2
Millimeters
Inches
Dim
Min.
0.76
0.00
0.57
Max.
0.84
0.04
0.63
Min.
0.030
0.00
Max.
0.033
0.0015
0.025
A
A1
A2
A3
D
0.022
0.20 REF.
0.650 BSC
0.008 REF.
0.0257BSC
3.90
3.90
0.25
2.05
2.05
4.10
4.10
0.35
2.15
2.15
0.154
0.154
0.010
0.081
0.081
0.161
0.161
0.014
0.085
0.085
E
b
D2
E2
e
L
0.50
0.60
0.002
0.024
Copyright ã ANPEC Electronics Corp.
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Rev. A.1 - Jun., 2006
APW7067N
Physical Specifications
Terminal Material
Lead Solderability
Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn
Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition (IR/Convection or VPR Reflow)
tp
TP
Critical Zone
TL to TP
Ramp-up
TL
tL
Tsmax
Tsmin
Ramp-down
ts
Preheat
25
°
t 25 C to Peak
Time
Classification Reflow Profiles
Profile Feature
Average ramp-up rate
(TL to TP)
Sn-Pb Eutectic Assembly
Pb-Free Assembly
3°C/second max.
3°C/second max.
Preheat
100°C
150°C
60-120 seconds
150°C
200°C
60-180 seconds
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (min to max) (ts)
Time maintained above:
- Temperature (TL)
183°C
60-150 seconds
217°C
60-150 seconds
- Time (tL)
Peak/Classificatioon Temperature (Tp)
See table 1
See table 2
Time within 5°C of actual
Peak Temperature (tp)
10-30 seconds
20-40 seconds
Ramp-down Rate
6°C/second max.
6°C/second max.
6 minutes max.
8 minutes max.
Time 25°C to Peak Temperature
Notes: All temperatures refer to topside of the package .Measured on the body surface.
Copyright ã ANPEC Electronics Corp.
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Rev. A.1 - Jun., 2006
APW7067N
Classification Reflow Profiles (Cont.)
Table 1. SnPb Entectic Process – Package Peak Reflow Temperatures
Package Thickness
Volume mm3
<350
Volume mm3
350
<2.5 mm
³ 2.5 mm
240 +0/-5°C
225 +0/-5°C
225 +0/-5°C
225 +0/-5°C
Table 2. Pb-free Process – Package Classification Reflow Temperatures
Package Thickness
Volume mm3
<350
Volume mm3
350-2000
Volume mm3
>2000
<1.6 mm
1.6 mm – 2.5 mm
³ 2.5 mm
260 +0°C*
260 +0°C*
250 +0°C*
260 +0°C*
250 +0°C*
245 +0°C*
260 +0°C*
245 +0°C*
245 +0°C*
*Tolerance: The device manufacturer/supplier shall assure process compatibility up to and
including the stated classification temperature (this means Peak reflow temperature +0°C.
For example 260°C+0°C) at the rated MSL level.
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TST
ESD
Method
MIL-STD-883D-2003
MIL-STD-883D-1005.7
JESD-22-B,A102
MIL-STD-883D-1011.9
MIL-STD-883D-3015.7
JESD 78
Description
245°C, 5 SEC
1000 Hrs Bias @125°C
168 Hrs, 100%RH, 121°C
-65°C~150°C, 200 Cycles
VHBM > 2KV, VMM > 200V
10ms, 1tr > 100mA
Latch-Up
Carrier Tape & Reel Dimensions
t
D
P
Po
E
F
P1
Bo
W
Ko
Ao
D1
Copyright ã ANPEC Electronics Corp.
25
www.anpec.com.tw
Rev. A.1 - Jun., 2006
APW7067N
Carrier Tape & Reel Dimensions (Cont.)
T2
J
C
A
B
T1
Application
A
B
C
J
T1
T2
W
P
8
t
E
13.0 + 0.5
- 0.2
330REF 100REF
2 ± 0.5 16.5REF 2.5 ± 025 16.0 ± 0.3
1.75
SOP-14
(150mil)
F
D
D1
Po
P1
Ao
Ko
7.5
4.0
2.0
6.5
T2
2.10
W
f 0.50 + 0.1 f 1.50 (MIN)
0.3±0.05
Application
QSOP- 16
A
B
C
J
T1
P
E
330 ± 1 62 +1.5 12.75+ 0.15 2 ± 0.5 12.4 ± 0.2
D1 Po P1
2 ± 0.2
12± 0. 3
8± 0.1 1.75±0.1
Ko
F
D
Ao
Bo
t
5.5± 1 1.55 +0.1 1.55+ 0.25 4.0 ± 0.1 2.0 ± 0.1 6.4 ± 0.1 5.2± 0. 1 2.1± 0.1 0.3±0.013
(mm)
4x4 Shipping Tray
Copyright ã ANPEC Electronics Corp.
26
www.anpec.com.tw
Rev. A.1 - Jun., 2006
APW7067N
4x4 Shipping Tray(Cont.)
Cover Tape Dimensions
Application
SOP- 14
Carrier Width
Cover Tape Width
Devices Per Reel
24
12
21.3
9.3
2500
2500
QSOP- 16
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369
Copyright ã ANPEC Electronics Corp.
Rev. A.1 - Jun., 2006
27
www.anpec.com.tw
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Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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