APW7088 [ANPEC]
Two-Phase Buck PWM Controller with Integrated MOSFET Drivers; 两相降压PWM控制器集成MOSFET驱动器
| 型号： | APW7088 |
| 厂家： | 
ANPEC ELECTRONICS COROPRATION |
| 描述： | Two-Phase Buck PWM Controller with Integrated MOSFET Drivers |
| 文件： | 总25页 (文件大小：576K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APW7088
Two-Phase Buck PWM Controller with Integrated MOSFET Drivers
Features
General Description
·
Voltage-Mode Operation with Current Sharing
The APW7088, two-phase PWM control IC, provides a
precision voltage regulation system for advanced graphic
microprocessors in graphics card applications. The inte-
gration of power MOSFET drivers into the controller IC
reduces the number of external parts for a cost and space
saving power management solution.
- Adjustable Feedback Compensation
- Fast Load Transient Response
·
·
Operate with 8V~13.2VCC Supply Voltage
Programmable 3-Bit DAC Reference
-±1.5% System Accuracy Over Temperature
Support Single- and Two-Phase Operations
5V Linear Regulator Output on 5VCC
The APW7088 uses a voltage-mode PWM architecture,
operating with fixed-frequency, to provides excellent load
transient response. The device uses the voltage across
the DCRs of the inductors for current sensing. Load line
voltage positioning (DROOP), channel-current balance
and over-current protection are accomplished through
continuous inductor DCR current sensing.
·
·
·
·
·
·
8~12V Gate Drivers with Internal Bootstrap Diode
Lossless Inductor DCR Current Sensing
Fixed 300kHz Operating Frequency Per Phase
Power-OK Indicator Output
- Regulated 1.5V on POK
The MODE pin programs single- or two- phase operation.
When IC operates in two-phase mode normally, it can
transfer two-phase mode to single phase mode at liberty.
Nevertheless, once operates in single-phase mode, the
operation mode is latched. It is required to toggle SS or
5VCC pin to reset the IC. Such feature of the MODE pin
makes the APW7088 ideally suitable for dual power input
applications, such as PCIE interfaced graphic cards.
·
·
·
·
·
·
·
·
Adjustable Over-Current Protection (OCP)
Accurate Load Line (DROOP) Programming
Adjustable Soft-Start
Over-Voltage Protection (OVP)
Under-Voltage Protection (UVP)
Over-Temperature Protection (OTP)
QFN4x4 24-Lead Package (QFN4x4-24)
Lead Free and Green Devices Available
(RoHS Compliant)
This control IC‘s protection features include a set of so-
phisticated over temperature, over-voltage, under-voltage,
and over-current protections. Over-voltage results in the
converter turning the lower MOSFETs on to clamp the
rising output voltage and protects the microprocessor.
The over-current protection level is set through external
resistors. The device also provides a power-on-reset func-
tion and a programmable soft-start to prevent wrong op-
eration and limit the input surge current during power-on
or start-up.
Simplified Application Circuit
VIN1
VID0
VID1
VID2
APW7088
VOUT
The APW7088 is available in a QFN4x4-24 package.
POK
Applications
VIN2
COMP
FB
·
·
Graphics Card GPU Core Power Supply
Motherboard Chipset or DDR SDRAM Core Power
Supply
·
On-Board High Power PWM Converter with Out-
put Current up to 60A
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright ã ANPEC Electronics Corp.
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Rev. A.4 - Feb., 2009
APW7088
Ordering and Marking Information
Package Code
QA : QFN4x4-24
APW7088
Operating Ambient Temperature Range
Assembly Material
Handling Code
°
E : -20 to 70 C
Handling Code
TR : Tape & Reel
Assembly Material
Temperature Range
Package Code
G : Halogen and Lead Free Device
APW7088 QA :
APW7088
XXXXX
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Pin Configuration
24 23 22 21 20 19
18
1
2
3
4
5
6
UGATE2
UGATE1
BOOT1
17 BOOT2
16 POK
15 VID1
14 SS
5VCC
AGND
MODE
CSP1
25
PGND
13
FB
7
8
9
10 11 12
4x4 QFN-24L
Top View
Absolute Maximum Ratings (Note 1)
Symbol
VCC
Parameter
VCC Supply Voltage (VCC to AGND)
Rating
-0.3 ~ 15
-0.3 ~ 15
Unit
V
VBOOT1/2
BOOT1/2 Voltage (BOOT1/2 to PHASE1/2)
UGATE1/2 Voltage (UGATE1/2 to PHASE1/2)
V
<200ns pulse width
>200ns pulse width
-5 ~ VBOOT1/2+5
V
V
V
V
-0.3 ~ VBOOT1/2+0.3
LGATE1/2 Voltage (LGATE1/2 to PGND)
PHASE1/2 Voltage (PHASE1/2 to PGND)
BOOT1/2 to AGND Voltage
<200ns pulse width
>200ns pulse width
-5 ~ VCC+5
-0.3 ~ VCC+0.3
<200ns pulse width
>200ns pulse width
-10 ~ 30
-2 ~ 15
<200ns pulse width
>200ns pulse width
-0.3 ~ 42
-0.3 ~ 30
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Rev. A.4 - Feb., 2009
APW7088
Absolute Maximum Ratings (Cont.) (Note 1)
Symbol
V5VCC
Parameter
5VCC Supply Voltage (5VCC to AGND, V5VCC < VCC +0.3V)
MODE to AGND Voltage
Rating
-0.3 ~ 7
-0.3 ~ 7
Unit
V
VMODE
V
Input Voltage (SS, FB, COMP, DROOP, CSP1/2, CSN1/2, VID0/1/2 to
AGND)
-0.3 ~ V5VCC +0.3
V
PGND to AGND Voltage
-0.3 ~ +0.3
Limited Internally
150
V
PDMAX
Maximum Power Dissipation
W
oC
oC
oC
Maximum Junction Temperature
Storage Temperature Range
TSTG
TSDR
-65 ~ 150
260
Maximum Soldering Temperature, 10 Seconds
Note 1: Stresses above those listed in “A bsolute Maximum Ratings” may cause permanent damage to the device.
Thermal Characteristics
Symbol
Parameter
Junction-to-Ambient Resistance (Note 2)
Junction-to-Case Resistance (Note 3)
Rating
Unit
45
7
qJA
°C/W
qJC
Note 2 : qJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of QFN4x4-24 is
soldered directly on the PCB.
Note 3: The case temperature is measured at the center of the exposed pad on the underside of the QFN4x4-24 package.
Recommended Operating Conditions (Note 4)
Symbol
Parameter
Range
8 ~ 13.2
5 ± 5%
Unit
V
VCC
VCC Supply Voltage
V5VCC
VOUT
VIN1
5VCC Supply Voltage (V5VCC < VCC +0.3V)
Converter Output Voltage
V
0.85 ~ 2.5
3.1 ~ 13.2
3.1 ~ 13.2
~ 60
V
PWM 1 Converter Input Voltage
PWM 2 Converter Input Voltage
Converter Output Current
V
VIN2
V
IOUT
A
TA
Ambient Temperature
-20 ~ 70
-20 ~ 125
0.8 ~ 15
0.8 ~ 15
oC
oC
mF
mF
TJ
Junction Temperature
Linear Regulator Output Capacitor
5VCC Linear Regulator Output Capacitor
CVCC
C5VCC
Note 4 : Refer to the typical application circuits.
Electrical Characteristics
°
Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=1.2V and TA= -20 ~ 70 C, unless otherwise
°
specified. Typical values are at TA=25 C. The V5VCC is supplied by the internal regulator.
APW7088
Typ.
Symbol
Parameter
Test Conditions
Unit
Min.
Max.
SUPPLY CURRENT
UGATEx and LGATEx Open,
VCC Nominal Supply Current
-
-
5
5
10
-
mA
mA
ICC
ISD
FB forced above regulation point
VCC Shutdown Supply
Current
SS=GND
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Rev. A.4 - Feb., 2009
APW7088
Electrical Characteristics (Cont.)
°
Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=1.2V and TA= -20 ~ 70 C, unless otherwise
°
specified. Typical values are at TA=25 C. The V5VCC is supplied by the internal regulator.
Symbol Parameter Test Conditions
POWER-ON-RESET (POR) AND OPERATION PHASE SELECTION
APW7088
Typ.
Unit
Min.
Max.
5VCC Rising Threshold Voltage
5VCC POR Hysteresis
4.2
0.4
4.5
0.58
0.8
-
4.8
0.76
0.83
+100
V
V
V5VCC_THR
MODE Rising Threshold Voltage
MODE Pin Input Current
VMODE Rising
0.77
-100
V
nA
IMODE
5VCC LINEAR REGULATOR
Output Voltage
Line Regulation
Load Regulation
Current-Limit
4.75
-20
5
-
5.25
20
V
VREG_5VCC
IO = 0A, VCC =8V
mV
mV
mA
IO = 0A, VCC = 8V ~ 13.2V
IO = 3mA, VCC > 8V
5VCC = GND
-200
20
-
200
-
30
REFERENCE VOLTAGE
TA=25oC
-1
-1.5
-100
1.2
-
-
-
+1
+1.5
+100
-
Accuracy
%
Over temperature
FB Pin Input Current
-
nA
V
IFB
VID0/1/2 Logic High Threshold
VID0/1/2 Logic Low Threshold
VID0/1/2 Pull-high Current
POK Output Voltage
-
-
0.5
-
V
-
1
1.5
-
mA
V
-
-
VPOK
IO = 0~3mA, TA=25oC
IO = 0~3mA, Over temperature
POK = GND
-2
-3
4
+2
+3
15
100
POK Accuracy
%
-
POK Current-Limit
8
70
mA
POK Pull-Low Resistance
-
IPOK = 5mA
W
ERROR AMPLIFIER
DC Gain
RL = 10kW to the ground
CL = 100pF, RL = 10kW to the ground
CL = 100pF, IO = ±400mA
IO = 1mA
-
85
20
8
-
dB
MHz
V/ms
V
Gain-Bandwidth Product
-
-
Slew Rate
-
2.7
-
-
-
Upper Clamp Voltage
Lower Clamp Voltage
COMP Pull-Low Resistance
3.0
-
IO = -1mA
0.1
-
V
In fault or shutdown condition
-
2
kW
OSCILLATOR
FOSC
Oscillator Frequency
255
-
300
1.5
88
345
kHz
V
Oscillator Sawtooth Amplitude
Maximum Duty Cycle
-
-
DVOSC1/2
85
%
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Rev. A.4 - Feb., 2009
APW7088
Electrical Characteristics (Cont.)
°
Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=1.2V and TA= -20 ~ 70 C, unless otherwise
°
specified. Typical values are at TA=25 C. The V5VCC is supplied by the internal regulator.
APW7088
Typ.
Symbol
Parameter
Test Conditions
Unit
Min.
Max.
MOSFET GATE DRIVERS
UGATE1/2 Source Current
VBOOT = 12V, VUGATE-VPHASE = 2V
VBOOT = 12V, VUGATE-VPHASE = 2V
VCC = 12V, VLGATE = 2V
-
-
-
-
-
-
-
-
-
2.6
1
-
A
A
UGATE1/2 Sink Current
LGATE1/2 Source Current
LGATE1/2 Sink Current
UGATE1/2 Source Resistance
UGATE1/2 Sink Resistance
LGATE1/2 Source Resistance
LGATE1/2 Sink Resistance
Dead-Time
-
2.6
1.4
2.5
2
-
-
A
VCC =12V, VLGATE = 2V
A
VBOOT = 12V, 100mA Source Current
VBOOT = 12V, 100mA Sink Current
VCC = 12V, 100mA Source Current
VCC = 12V, 100mA Sink Current
3.75
3
W
W
W
W
ns
2
3
1.4
30
2.1
-
TD
CURRENT SENSE AND DROOP FUNCTION
CSP1/2 Pin Input Current
-100
80
15
-
-
-
+100
nA
ICSP
Sourcing current
R CSN1/2 = 2kW,
-
-
CSN1/2 Maximum Output Current
ICSN
mA
Sinking current
-
Current Sense Amplifier Bandwidth
DROOP Output Current Accuracy
DROOP Accuracy
3
50
-
-
MHz
mA
-
-
RDROOP = 2kW, VDROOP =0.005V
DVFB = VDROOP/20, VDROOP=1V
-5
+5
mV
Current Difference Between
-10
-
+10
%
Channel1/2 and Average Current
SOFT-START AND ENABLE
Soft-Start Current Source
Flowing out of SS pin
8
-
10
3.2
10
12
-
ISS
mA
V
Soft-Start Complete Threshold
SS Pull-low Resistance
-
18
kW
POWER OK AND PROTECTIONS
Over-Current Trip Level
ICS1 + ICS2
110
40
-
120
50
140
60
-
mA
%
%
%
~ 2ms noise filter, VFB falling,
FB Under-Voltage Threshold
POK Lower Threshold
VUV
Percentage of VR at Error Amplifier
87.5
125
VPOK_L
FB Over-Voltage Threshold
and POK Upper Threshold
~ 2ms noise filter, VFB rising
VOV
,
115
135
VPOK_H
Percentage of VR at Error Amplifier
FB Over-Voltage Hysteresis
Over-Temperature Trip Level
Over-Temperature Hysteresis
-
-
-
60
150
50
80
-
mV
oC
oC
TJ rising
TOTR
-
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Rev. A.4 - Feb., 2009
APW7088
Typical Operating Characteristics
5VCC Line Regulation
5VCC Load Regulation
6
5
4
3
2
1
0
6
VCC=12V, VIN=12V
5
4
3
2
1
0
0
5
10
15
20 25
30
35
40
0
2
4
6
8
10
12
14
5VCC Load Current ,I5VCC (mA)
VCC Voltage,VCC (V)
Output Voltage Load Regulation
Output Voltage Line Regulation
0.857
0.855
0.853
0.851
0.857
0.855
0.853
0.851
0.849
0.847
0.845
0.843
0.841
VID0, VID1 and VID2 are high
VCC=12V, VIN=12V
VID0, VID1 and VID2 are high
0.849
0.847
0.845
0.843
0.841
5
6
7
8
9
10
11
12
13
0
10
20
30
40
50
VIN Voltage,VIN (V)
Output Current,IOUT (A)
Reference Voltage Accuracy Over
Temperature
Switching Frequency Over Temperature
330
320
310
0.863
0.860
0.857
0.854
0.851
0.849
0.846
0.843
0.840
0.837
VID0, VID1 and VID2 are high
300
290
280
270
-40 -20
0
20
40
60
80 100 120
-40 -20
0
20
40
60
80 100 120
Junction Temperature, TJ (oC)
Junction Temperature, TJ (oC)
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Rev. A.4 - Feb., 2009
APW7088
Operating Waveforms
Power On
Power Off
IOUT=10A
IOUT=10A
V5VCC
V5VCC
1
1
2
VCOMP
VCOMP
2
VSS
VSS
3
3
4
VOUT
VOUT
4
CH1: V5VCC (5V/div)
CH2: VCOMP (1V/div)
CH3: VSS (5V/div)
CH4: VOUT (1V/div)
Time: 5ms/div
CH1: V5VCC (5V/div)
CH2: VCOMP (1V/div)
CH3: VSS (5V/div)
CH4: VOUT (1V/div)
Time: 5ms/div
Enable by SS Pin
Shutdown by SS Pin
IOUT=10A
IOUT=10A
VSS
VSS
1
2
1
VCOMP
VCOMP
2
VOUT
VOUT
3
3
CH1: VSS (2V/div)
CH2: VCOMP (1V/div)
CH3: VOUT (1V/div)
Time: 10ms/div
CH1: VSS (2V/div)
CH2: VCOMP (1V/div)
CH3: VOUT (1V/div)
Time: 10ms/div
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Rev. A.4 - Feb., 2009
APW7088
Operating Waveforms (Cont.)
Power On Without VIN2 Voltage
Under-Voltage Protection (UVP)
VOUT
VFB
1
2
3
4
1
VPHASE1
VPHASE1
2
VPHASE2
VPHASE2
3
Vss
Vss
4
CH1: VOUT (1V/div)
CH2: VPHASE1 (10V/div)
CH3: VPHASE2 (2V/div)
CH4: VSS (2V/div)
Time: 5ms/div
CH1: VFB (500mV/div)
CH2: VPHASE1 (10V/div)
CH3: VPHASE2 (10V/div)
CH4: VSS (2V/div)
Time: 500ms/div
Load Transient , 0A==>40A
Load Transient , 40A==>0A
VPHASE1
VPHASE1
IPHASE2
VOUT
1
1
2
3
IPHASE2
2
VOUT
3
IOUT
RSEN=3kW
L=0.56mH
DCR=4mW
RSEN=3kW
L=0.56mH
DCR=4mW
IOUT
4
4
CH1: VPHASE1 (20V/div)
CH2: IPHASE2 (20A/div)
CH3: VOUT (AC, 200mV/div)
CH4: IOUT (10A/div)
CH1: VPHASE1 (20V/div)
CH2: IPHASE2(20A/div)
CH3: VOUT (AC, 200mV/div)
CH4: IOUT (10A/div)
Time: 20ms/div
Time: 20ms/div
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Rev. A.4 - Feb., 2009
APW7088
Operating Waveforms (Cont.)
OCP at Slow Slew IOUT
Short-Circuit Test After Power On
RSEN=1.5kW
L=0.56mH
DCR=4mW
RSEN=1.5kW
L=0.56mH
DCR=4mW
IL1
IL1
1
1
2
IL2
IL2
2
3
4
VSS
VSS
VOUT
3
4
VOUT
CH1: IL1 (10A/div)
CH2: IL2 (10A/div)
CH3: VSS (5V/div)
CH4: VOUT (1V/div)
Time: 5ms/div
CH1: IL1 (10A/div)
CH2: IL2 (10A/div)
CH3: VSS (5V/div)
CH4: VOUT (1V/div)
Time: 5ms/div
Short-Circuit Test Before Power On
OVP After Power On
VFB
RSEN=1.5kW
L=0.56mH
DCR=4mW
IL1
Pull-Up VFB > V OV
VSS
1
1
VLG1
2
3
IL2
VLG2
2
VSS
VOUT
3
4
4
CH1: VFB (500mV/div)
CH2: VSS (2V/div)
CH3: VLG1 (10V/div)
CH4: VLG2 (10V/div)
Time: 100ms/div
CH1: IL1 (10A/div)
CH2: IL2 (10A/div)
CH3: VSS (5V/div)
CH4: VOUT (1V/div)
Time: 5ms/div
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Rev. A.4 - Feb., 2009
APW7088
Pin Description
PIN
NAME
FUNCTION
High-side Gate Driver Output for channel 1. Connect this pin to the gate of high-side MOSFET.
This pin is monitored by the adaptive shoot-through protection circuitry to determine when the
high-side MOSFET has turned off.
1
UGATE1
Bootstrap Supply for the floating high-side gate driver of channel 1. Connect the Bootstrap
capacitor between the BOOT1 pin and the PHASE1 pin to form a bootstrap circuit. The bootstrap
capacitor provides the charge to turn on the high-side MOSFET. Typical values for CBOOT ranged
from 0.1mF to 1mF. Ensure that CBOOT is placed near the IC.
2
BOOT1
Internal Regulator Output. This is the output pin of the linear regulator, which is converting power
from VCC and provides output current up to 20 mA minimums for internal bias and external usage.
3
4
5VCC
AGND
Signal Ground for the IC. All voltage levels are measured with respect to this pin. Tie this pin to
ground island/plane through the lowest impedance connection available.
Operation Phase Selection Input. Pulling this pin lower than 0.64V sets two-phase operation with
both channels enabled. Pulling this pin higher than 0.8V sets single-phase operation with the
channel 2 disabled. Once operating in single-phase mode, the operation mode is latched. It is
required to toggle SS or 5VCC pin to reset the IC.
5
MODE
Positive Input of current sensing Amplifier for channel 1. This pin combined with CSN1 senses the
inductor current through an RC network.
6
7
8
9
CSP1
CSN1
CSN2
CSP2
Negative Input of current sensing amplifier for channel 1. This pin combined with CSP1 senses
the inductor current through an RC network.
Negative Input of current sensing amplifier for channel 2. This pin combined with CSP2 senses
the inductor current through an RC network.
Positive Input of current sensing Amplifier for Channel 2. This pin combined with CSN2 senses the
inductor current through an RC network.
Load Line (droop) Setting. Connect a resistor between this pin and AGND to set the droop. A
sourcing current, proportional to output current is present on the DROOP pin. The droop scale
factor is set by the resistors (connected with CSP1, CSP2, and DROOP), resistance of the output
inductors and the internal voltage divider with the ratio of 5%.
10
11
DROOP
VID0
This is one of the inputs for the internal DAC that provides the reference voltage for output
regulation. This pin responds to logic threshold. The APW7088 decodes the VID inputs to
establish the output voltage; see VID Tables for correspondence between DAC codes and output
voltage settings. This pin is internally pulled high at floating status.
Error Amplifier Output. Connect the compensation network between COMP, FB, and VOUT for Type
2 or Type 3 feedback compensation.
12
13
COMP
FB
Feedback Voltage. This pin is the inverting input to the error comparator. A resistor divider from
the output to AGND is used to set the regulation voltage.
Soft-start Current Output. Connect a capacitor from this pin to AGND to set the soft-start interval.
Pulling the voltage on this pin below 0.5V causes COMP to pull low and then shuts off the output.
14
15
16
SS
VID1
POK
One of DAC Inputs, same as VID0 and VID2.
Power OK and 1.5V Reference Output. This pin is a reference output used to indicate the status of
the voltages on SS pin and FB pin. POK provides 1.5V reference if VFB> 87.5% of reference (VR).
Bootstrap Supply for the floating high-side gate driver of channel 2. Connect the Bootstrap
capacitor between the BOOT2 pin and the PHASE2 pin to form a bootstrap circuit. The bootstrap
capacitor provides the charge to turn on the high-side MOSFET. Typical values for CBOOT range
from 0.1mF to 1mF. Ensure that CBOOT is placed near the IC.
17
18
BOOT2
High-side Gate Driver Output for Channel 2. Connect this pin to the gate of high-side MOSFET.
This pin is monitored by the adaptive shoot-through protection circuitry to determine when the
high-side MOSFET has turned off.
UGATE2
Switch Node for Channel 2. Connect this pin to the source of high-side MOSFET and the drain of
the low-side MOSFET. This pin is used as sink for UGATE2 driver. This pin is also monitored by
the adaptive shoot-through protection circuitry to determine when the high-side MOSFET has
turned off. An Schottky diode between this pin and ground is recommended to reduce negative
transient voltage that is common in a power supply system.
19
20
PHASE2
LGATE2
Low-side Gate Driver Output for Channel 2. Connect this pin to the gate of low-side MOSFET.
This pin is monitored by the adaptive shoot-through protection circuitry to determine when the
low-side MOSFET has turned off.
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APW7088
Pin Description (Cont.)
PIN
NAME
FUNCTION
21
VID2
One of DAC Inputs, same as VID0 and VID1.
Supply Voltage Input. This pin provides bias supply for the low-side gate drivers and the bootstrap
circuit for high-side drivers. This pin can receive a well-decoupled 8V~13.2V supply voltage.
Ensure that this pin is bypassed by a ceramic capacitor next to the pin.
Low-side Gate Driver Output for Channel 1. Connect this pin to the gate of low-side MOSFET.
This pin is monitored by the adaptive shoot-through protection circuitry to determine when the
low-side MOSFET has turned off.
22
23
VCC
LGATE1
Switch Node for Channel 1. Connect this pin to the source of high-side MOSFET and the drain of
the low-side MOSFET. This pin is used as sink for UGATT1 driver. This pin is also monitored by
the adaptive shoot-through protection circuitry to determine when the high-side MOSFET has
turned off. An Schottky diode between this pin and ground is recommended to reduce negative
transient voltage which is common in a power supply system.
24
25
PHASE1
PGND
Power Ground for the low-side gate drivers. Connect this pin to the source of low-side MOSFETs.
This pin is used as sink for LGATE1 and LGATE2 drivers.
Block Diagram
POK
VCC
5VCC
Linear
Regulator
5VCC
1.5V
Reference
VCC
87.5%
125%
50%
Power-on-
Reset
OV
UV
V5VCC
Over-Temperature
Protection
FB
PGND
MODE
Droop Control
DROOP
Control
Logic
Operation
Phase
Selection
VDROOP
VID0
VID1
VID2
-
3-Bit
DAC
3.6V
VR
+
VDAC
ISS
10mA
Error
Amplifier
Soft-Start
SS
300kHz
COMP
AGND
VOSC1
Oscillator
and
Sawtooth
VOSC2
VCC
VCC
BOOT2
UGATE2
PHASE2
BOOT1
PWM Signal Controller
UGATE1
PHASE1
VCC
VCC
LGATE2
LGATE1
120mA
OC
ICS1+ICS2
Current
Balance
CSN1
CSP1
ICS2
ICS1
CSN2
CSP2
Current
Sense
Current
Sense
ICS1+ICS2
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Rev. A.4 - Feb., 2009
APW7088
Typical Application Circuit
VIN
+12V
C4
10mF
2
BOOT1
5
MODE
Q1
1
UGATE1
PHASE1
L1
0.56mH
C5
0.1mF
24
VOUT
1.2V
22
3
VCC
DCR=4mW
C13
1mF
C6
1200mFx3
C7
Q2
23
25
47mFx2
LGATE1
PGND
5VCC
IOCP=45A
C14
1mF
Q1 : APM4350KPx1
Q2 : APM4354KPx2
14
APW7088
SS
C15
0.1mF
17
C8
10mF
BOOT2
C9
330mFx3
11
15
21
VID0
VID1
VID2
Q3
18
19
UGATE2
PHASE2
L2
0.56mH
C10
0.1mF
10
16
DROOP
POK
R11
2kW
DCR=4mW
Q4
20
LGATE2
C3
2.2nF
R5
1.5kW
6
7
CSP1
CSN1
PHASE1
PHASE2
C2
22nF
R4
2kW
12
13
COMP
FB
9
8
CSP2
CSN2
R7
1.5kW
R2
3.6kW
R3
51W
C12
0.1mF
C11
0.1mF
AGND
R1
1.5kW
R8
1.5kW
R6
1.5kW
4
C1
10nF
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Rev. A.4 - Feb., 2009
APW7088
Function Description
When soft-start is initiated, the internal 10mA current
source starts to charge the capacitor. When the soft-start
voltage across the soft-start capacitor reaches the en-
abled threshold about 0.8V (VSS_VT), the internal reference
starts to rise and follows the soft-start voltage with con-
verter operating at fixed 300kHz PWM switching
frequency. When output voltage rises up to 87.5% of
the regulation voltage, the power-ok is enabled. The soft-
start time (from the moment of enabling the IC to the
moment when VPOK goes high) can be expressed as
below :
5VCC Linear Regulator
5VCC is the output terminal of the internal 5V linear
regulator which regulates a 5V voltage on 5VCC by
controlling an internal bypass transistor between VCC
and 5VCC. The linear regulator powers the internal
control circuitry and is stable with a low-ESR ceramic
output capacitor. Bypass 5VCC to GND with a ceramic
capacitor of at least 1mF. Place the capacitor physically
close to the IC to provide good noise decoupling. The
linear regulator can also provide output current, up to
20mA, for external loads. The linear regulator with current-
limit protection can protect itself during over-load or short-
circuit conditions on 5VCC pin.
CSS ´ (VSS _ VT + VDAC´ 0.875)
TSS =
ISS
where
The 5VCC linear regulator stop regulating in Over-Tem-
perature Protection. When the junction temperature is
cooled by 50oC, the 5VCC linear regulator starts to regu-
late the output voltage again.
CSS= external soft-start capacitor
VSS_VT= internal soft start threshold voltage, is about
0.8V
VDAC= Internal digital VID programmable reference
voltage
5VCC Power-On-Reset (POR)
Figure 1 shows the power sequence. The APW7088
keeps monitoring the voltage on 5VCC pin to prevent
wrong logic operations which may occur when 5VCC
voltage is not high enough for the internal control cir-
cuitry to operate. The 5VCC POR has a rising thresh-
old of 4.6V (typical) with 0.58V of hysteresis. After the
5VCC voltage exceeds its rising Power-On-Reset
(POR) voltage threshold, the IC starts a start-up pro-
cess and then ramps up the output voltage to the setting
of output voltage. The 5VCC POR signal resets the
fault latch, set by the undervoltage or over-current event,
when the signal is at low level.
ISS= soft-start current=10mA
During soft-start stage, the under-voltage protection is
inhibited. However, the over-voltage and over-current pro-
tection functions are enabled. If the output capacitor has
residue voltage before startup, both lower and upper
MOSFETs are in off-state until the internal soft-start volt-
age equals the FB pin voltage. This will ensure the out-
put voltage starts from its existing voltage level.
Operation Phase Selection
The MODE pin programs single- or two- phase operation.
It has a typical value for rising threshold of 0.8V, VMODE_THR
,
with 0.16V of hysteresis (0.64V), VMODE_THF. When the MODE
pin voltage is higher than the VMODE_THR, the device oper-
ates in single-phase; when the MODE pin voltage is lower
than VMODE_THF and VIN2 supply voltage is above approxi-
mate 4V, the device operates in two-phase operation.
This function makes the APW7088 ideally suitable for
dual power input applications like PCIE interfaced graphic
cards.
Voltage(V)
VCC
VSS
V5VCC
5VCC
POR
VPOK
1.5V
The figure 2 shows the power sources of the two
channels. The input power of PWM1 converter is sup-
plied by PCIE bus power and the input power of PWM2
converter is supplied by an external power. If the input
power connector of PWM2 converter is not plugged into
VFB
VSS_VT
Time
Figure 1. Power Sequence
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Rev. A.4 - Feb., 2009
APW7088
Function Description (Cont.)
Operation Phase Selection (Cont.)
rent protection responds, the output voltage will fall
out of the required regulation range. The under-voltage
continually monitors the VFB voltage after soft-start is
completed. If a load step is strong enough to pull the
output voltage lower than the under-voltage threshold,
the IC shuts down converter’s output. Cycling the 5VCC
POR resets the fault latch and starts a start-up process.
The under-voltage threshold is 50% of the nominal out-
put voltage. The under-voltage comparator has a built-in
2ms noise filter to prevent the chips from wrong UVP
shutdown being caused by noise.
the socket before start-up, the internal VIN2 sensing circuit
can sense the absence of VIN2 and set the IC to operate in
single-phase mode with PWM2 disabled. When the IC
operates in two-phase mode, it can switch the operating
mode from two-phase to single-phase operation. Once
operating in single-phase mode, the operation mode is
latched. It is required to toggle SS or 5VCC pin to reset
the IC.
PCIE
+12V
VCC
Over-Current Protection (OCP)
PWM 1
converter
Figure 3 shows the circuit of sensing inductor current.
Connecting a series resistor (RS) and a capacitor (CS)
network in parallel with the inductor and measuring
the voltage (VC) across the capacitor can sense the in-
ductor current.
Operation
Phase
Selection
External
Power
MODE
VIN2
PHASE2
PWM 2
converter
4V
VIN2 sensing
circuit
VL
L
DCR
PHASE
Figure 2. VIN2 Sensing Circuit
Over-Voltage Protection (OVP)
IL
Rs
Cs
VC
The over-voltage protection function monitors the output
voltage through FB pin. When the FB voltage increases
over 125% of the reference voltage (VR) due to the high-
side MOSFET failure or other reasons, the over-voltage
protection comparator designed with a 2ms noise filter
will force the low-side MOSFET gate drivers high. This
action actively pulls down the output voltage and eventu-
ally attempts to trigger the over-current shutdown of an
ATX power supply. As soon as the output voltage is within
regulation, the OVP comparator is disengaged. The chip
will restore its normal operation. When the OVP occurs,
the POK will drop to low as well.
CSP
CSN
R2
Figure 3. Illustration of Inductor Current Sensing Circuit
The equations of the sensing network are,
VL(s)=IL(s)´ (SL+DCR)
1
IL(S)´ (SL + DCR)
1+ SRSCS
VC(S) = VL(S)´
=
1+ SRSCS
Take
This OVP scheme only clamps the voltage overshoot
and does not invert the output voltage when otherwise
activated with a continuously high output from low-side
MOSFETs driver, which is a common problem for OVP
schemes with a latch.
L
RSCS =
DCR
for example, if the above is true, the voltage across the
capacitor CS is equal to voltage drop across the inductor
DCR, and the voltage VC is proportional to the current IL.
The sensing current through the resistor R2 can be ex-
pressed as below :
Under-Voltage Protection (UVP)
In the operational process, when a short-circuit occurs,
the output voltage will drop quickly. Before the over-cur-
IL ´ DCR
ICS =
R2
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Rev. A.4 - Feb., 2009
APW7088
Function Description (Cont.)
Over-Current Protection (OCP) (Cont.)
Droop Control
where
VDROOP
ICS is the sensed current
IL is the inductor current
DCR is the inductor resistance
R2 is the sense resistor
RDROOP
VR
VREFIN/EN or 0.6V
The APW7088 is a two-phase PWM controller; therefore,
the IC has two sensed current parts, ICS1 and ICS2. When
ICS1 plus ICS2 is greater than 120mA, the over current occurs.
In over-current protection, the IC shuts off the converter
and then initials a new soft-start process. After 3 over-
current events are counted, the device turns off both high-
side and low-side MOSFETs and the converter’s output
is latched to be floating.
Figure 4. Illustration of Droop Setting Function
Over-Temperature Protection (OTP)
When the junction temperature increases above the ris-
ing threshold temperature TOTR, the IC will enter the over-
temperature protection state that suspends the PWM,
which forces the LGATE and UGATE gate drivers to out-
put low voltages and turns off the 5VCC linear regulator
output. The thermal sensor allows the converters to start
a start-up process and regulate the output voltage again
after the junction temperature cools by 50oC. The OTP is
designed with a 50oC hysteresis to lower the average TJ
during continuous thermal overload conditions, which
increases lifetime of the APW7088.
Current Sharing
The APW7088 uses inductor’s DCRs and external net-
works to sense the both currents flowing through the in-
ductors of the PWM1 and PWM2 channels. The current
sharing circuit, with closed-loop control, uses the sensed
currents to adjust the two-phase inductor currents. For
example, if the sensed current of PWM1 is bigger than
PWM2, the duty of PWM1 will decrease and the duty of
PWM2 will increase. Then, the device will reduce IL1
current and increase IL2 current for current sharing.
Table 1. DAC Output Voltage vs. VID Inputs
DAC Output
VID2
VID1
VID0
Voltage, VDAC (V)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1.20
DROOP
1.15
1.10
1.05
1.00
0.95
0.90
0.85
In some high current applications, a requirement on
precisely controlled output impedance is imposed. This
dependence of output voltage on load current is often
termed droop regulation.
As shown in figure 4, the droop control block gener-
ates a voltage through external resistor RDROOP, then
set the droop voltage. The droop voltage, VDROOP, is
proportional to the total current in two channels. As
the following equation shows,
VDROOP = 0.05´ [(ICS1 +ICS2)´ RDROOP]
The VDROOP voltage is used the regulator to adjust the out-
put voltage so that it’s equal to the reference voltage mi-
nus the droop voltage.
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Rev. A.4 - Feb., 2009
APW7088
Application Information
Output Voltage Setting
The output voltage is adjustable from 0.85V to 2.5V with a
resistor-divider connected with FB, AGND, and converter’s
output. Using 1% or better resistors for the resistor-di-
vider is recommended. The output voltage is determined
by :
FLC
-40dB/dec
RTOP
RGND
æ
ö
VOUT = VDAC ´ 1+
ç
÷
FESR
è
ø
Where VDAC is the internal digital VID programmable ref-
erence voltage, the RTOP is the resistor connected from
converter’s output to FB and RGND is the resistor con-
nected from FB to AGND. Suggested RGND is in the range
from 1K to 20KW. To prevent stray pickup, locate resis-
tors RTOP and RGND close to the APW7088.
-20dB/dec
Frequency(Hz)
Figure 6. Frequency Resopnse of the LC filters
PWM Compensation
The output LC filter of a step down converter introduces a
double pole, which contributes with -40dB/decade gain
slope and 180 degrees phase shift in the control loop. A
compensation network among COMP, FB, and VOUT
should be added. The compensation network is shown
in Figure 8. The output LC filters consists of the
output inductors and output capacitors. For two-phase
convertor, when assuming VIN1=VIN2=VIN, L1=L2=L, the
transfer function of the LC filter is given by :
The PWM modulator is shown in figure 7. The input is the
output of the error amplifier and the output is the PHASE
node. The transfer function of the PWM modulator is given
by :
V
IN
GAINPWM
=
DVOSC
VIN
Driver
OSC
PWM
Comparator
1+ s´ ESR´ COUT
PHASE
GAINLC
=
DVOSC
1
s2 ´ L´ COUT + s´ ESR´ COUT +1
2
Output of Error
Amplifier
The poles and zero of this transfer functions are :
1
Driver
F
=
LC
1
2
Figure 7. The PWM Modulator
2´ p ´
L´ COUT
The compensation network is shown in figure 8. It pro-
vides a close loop transfer function with the highest zero
crossover frequency and sufficient phase margin.
1
F
=
ESR
2´ p ´ ESR´ COUT
The FLC is the double-pole frequency of the two-phase LC
filters, and FESR is the frequency of the zero introduced by
the ESR of the output capacitors.
The transfer function of error amplifier is given by:
1
1
æ
ö
÷
ø
// R2 +
ç
VCOMP
VOUT
sC1
sC2
è
GAINAMP
=
=
VPHASE1
L1=L
VOUT
1
æ
ö
R1// R3 +
ç
÷
sC3
è
ø
L2=L
COUT
ESR
æ
ö
ö
1
1
æ
VPHASE2
ç
´ s +
÷
÷
s +
ç
÷
ç
R2´ C2
(
R1+ R3
)
´ C3
R1+ R3
è
ø
è
C1+ C2
ø
=
´
R1´ R3´ C1
æ
ö æ
1
ö
s s +
´ s +
÷ ç
ç
÷
R2´ C1´ C2
R3´ C3
è
ø è
ø
Figure 5. The Output LC Filter
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Rev. A.4 - Feb., 2009
APW7088
Application Information (Cont.)
PWM Compensation (Cont.)
4. Set the pole at the ESR zero frequency FESR
FP1 = FESR
:
The pole and zero frequencies of the transfer function
Calculate the C1 by the following equation:
are:
1
FZ1
FZ2
=
2´ p ´ R2´ C2
C2
C1=
1
2´ p ´ R2´ C2´ FESR - 1
=
=
2´ p ´
(
R1+R3
)
´ C3
5. Set the second pole FP2 at the half of the switching
frequency and also set the second zero FZ2 at the output LC
filter double pole FLC. The compensation gain should not
exceed the error amplifier open loop gain, check the
compensation gain at FP2 with the capabilities of the
error amplifier.
1
F
P1
C1´ C2
æ
ö
÷
ø
2´ p ´ R2´
ç
C1+ C2
è
1
F
=
P2
2´ p ´ R3´ C3
C1
FP2 = 0.5 X FSW
R3
C3
R2
C2
FZ2 = FLC
VOUT
Combine the two equations will get the following
component calculations:
FB
VCOMP
R1
R1
R3 =
VDAC
Figure 8. Compensation Network
FSW
- 1
2´ F
LC
The closed loop gain of the converter can be written as:
GAINLC X GAINPWM X GAINAMP
1
C3 =
p ´ R3´ FSW
Figure 9. shows the asymptotic plot of the closed loop
converter gain, and the following guidelines will help to
design the compensation network. Using the below
guidelines should give a compensation similar to the
curve plotted. A stable closed loop has a -20dB/ decade
slope and a phase margin greater than 45 degree.
FZ1 FZ2
FP1
FP2
Compensation Gain
20log
(R2/R1)
20log
(VIN/ΔVOSC
)
1. Choose a value for R1, usually between 1K and 5K.
2. Select the desired zero crossover frequency
FO= (1/5 ~ 1/10) X FSW
FLC
Use the following equation to calculate R2:
FESR
Converter Gain
DVOSC FO
R2 =
´
´ R1
PWM & Filter Gain
V
F
LC
IN
Frequency(Hz)
3. Place the first zero FZ1 before the output LC filter double
pole frequency FLC.
Figure 9. Converter Gain and Frequency
Output Inductor Selection
FZ1 = 0.75 X FLC
Calculate the C2 by the following equation:
The duty cycle (D) of a buck converter is the function of
the input voltage and output voltage. Once an output volt-
age is fixed, it can be written as:
1
C2 =
2´ p ´ R2´ FLC ´ 0.75
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APW7088
Application Information (Cont.)
Output Inductor Selection (Cont.)
of the inductor’s current. The ripple voltage of output ca-
pacitors can be represented by:
VOUT
D =
V
DIP - P
DVCOUT =
IN
8´ COUT ´ FSW
For two-phase converter, the inductor value (L) determines
the sum of the two inductor ripple currents, DIP-P, and af-
fects the load transient reponse. Higher inductor value
reduces the output capacitors’ ripple current and induces
lower output ripple voltage. The ripple current can be
approxminated by :
DVESR = DIP - P ´ RESR
These two components constitute a large portion of the
total output voltage ripple. In some applications, multiple
capacitors have to be parallelled to achieve the desired
ESR value. If the output of the converter has to support
another load with high pulsating current, more capaci-
tors are needed in order to reduce the equivalent ESR
and suppress the voltage ripple to a tolerable level. A
small decoupling capacitor in parallel for bypassing the
noise is also recommended, and the voltage rating of the
output capacitors must also be considered.
VIN - 2VOUT VOUT
DIP - P =
´
FSW ´ L
VIN
Where FSW is the switching frequency of the regulator.
Although the inductor value and frequency are increased
and the ripple current and voltage are reduced, a tradeoff
exists between the inductor’s ripple current and the regu-
lator load transient response time.
To support a load transient that is faster than the switch-
ing frequency, more capacitors are needed for reducing
the voltage excursion during load step change. For get-
ting same load transient response, the output capaci-
tance of two-phase converter only needs around half of
output capacitance of single-phase converter.
A smaller inductor will give the regulator a faster load
transient response at the expense of higher ripple current.
Increasing the switching frequency (FSW) also reduces
the ripple current and voltage, but it will increase the
switching loss of the MOSFETs and the power dissipa-
tion of the converter. The maximum ripple current occurs
at the maximum input voltage. A good starting point is to
choose the ripple current to be approximately 30% of the
maximum output current. Once the inductance value has
been chosen, select an inductor that is capable of carry-
ing the required peak current without going into saturation.
In some types of inductors, especially core that is made
of ferrite, the ripple current will increase abruptly when it
saturates. This results in a larger output ripple voltage.
Another aspect of the capacitor selection is that the total
AC current going through the capacitors has to be less
than the rated RMS current specified on the capacitors in
order to prevent the capacitor from over-heating.
Input Capacitor Selection
Use small ceramic capacitors for high frequency
decoupling and bulk capacitors to supply the surge cur-
rent needed each time high-side MOSFET turns on. Place
the small ceramic capacitors physically close to the
MOSFETs and between the drain of high-side MOSFET
and the source of low-side MOSFET.
Output Capacitor Selection
Output voltage ripple and the transient voltage deviation
are factors that have to be taken into consideration when
selecting output capacitors. Higher capacitor value and
lower ESR reduce the output ripple and the load tran-
sient drop. Therefore, selecting high performance low
ESR capacitors is recommended for switching regulator
applications. In addition to high frequency noise related
to MOSFET turn-on and turn-off, the output voltage ripple
includes the capacitance voltage drop DVCOUT and ESR
voltage drop DVESR caused by the AC peak-to-peak sum
The important parameters for the bulk input capacitor are
the voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and cur-
rent ratings above the maximum input voltage and larg-
est RMS current required by the circuit. The capacitor volt-
age rating should be at least 1.25 times greater than the
maximum input voltage and a voltage rating of 1.5 times
is a conservative guideline. For two-phase converter, the
RMS current of the bulk input capacitor is roughly calcu-
lated as the following equation:
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Rev. A.4 - Feb., 2009
APW7088
Application Information (Cont.)
Input Capacitor Selection (Cont.)
where
I
is the load current
IOUT
OUT
IRMS =
´
2D×(1- 2D)
TC is the temperature dependency of RDS(ON)
FSW is the switching frequency
tSW is the switching interval
2
For a through hole design, several electrolytic capacitors
may be needed. For surface mount design, solid tan-
talum capacitors can be used, but caution must be exer-
cised with regard to the capacitor surge current rating.
D is the duty cycle
Note that both MOSFETs have conduction losses while
the high-side MOSFET includes an additional transi-
tion loss. The switching interval, tSW, is the function of
the reverse transfer capacitance CRSS. The (1+TC) term is
a factor in the temperature dependency of the RDS(ON) and
can be extracted from the “RDS(ON) vs. Temperature” curve
of the power MOSFET.
MOSFETSelection
The APW7088 requires two N-Channel power MOSFETs
on each phase. These should be selected based upon
RDS(ON), gate supply requirements, and thermal manage-
ment requirements.
In high-current applications, the MOSFET power
dissipation, package selection, and heatsink are the domi-
nant design factors. The power dissipation includes two
loss components, conduction loss and switching loss.
The conduction losses are the largest component of
power dissipation for both the high-side and the low-
side MOSFETs. These losses are distributed between
the two MOSFETs according to duty factor (see the equa-
tions below). Only the high-side MOSFET has switching
losses since the low-side MOSFETs body diode or an
external Schottky rectifier across the lower MOSFET
clamps the switching node before the synchronous rec-
tifier turns on. These equations assume linear voltage-
current transitions and do not adequately model power
loss due the reverse-recovery of the low-side MOSFET
body diode. The gate-charge losses are dissipated by
the APW7088 and don’t heat the MOSFETs. However,
large gate-charge increases the switching interval, tSW
which increases the high-side MOSFET switching
losses. Ensure that all MOSFETs are within their maxi-
mum junction temperature at high ambient temperature
by calculating the temperature rise according to package
thermal-resistance specifications. A separate heatsink
may be necessary depending upon MOSFET power,
package type, ambient temperature, and air flow.
Layout Consideration
In any high switching frequency converter, a correct layout
is important to ensure proper operation of the regulator.
With power devices switching at higher frequency, the
resulting current transient will cause voltage spike across
the interconnecting impedance and parasitic circuit
elements. As an example, consider the turn-off transition
of the PWM MOSFET. Before turn-off condition, the
MOSFET is carrying the full load current. During turn-off,
current stops flowing in the MOSFET and is freewheeling
by the low side MOSFET and parasitic diode. Any parasitic
inductance of the circuit generates a large voltage spike
during the switching interval. In general, using short, wide
printed circuit traces should minimize interconnecting im-
pedances and the magnitude of voltage spike. Besides,
signal and power grounds are to be kept separating and
finally combined using ground plane construction or
single point grounding. The best tie-point between the
signal ground and the power ground is at the negative
side of the output capacitor on each channel, where there
is less noise. Noisy traces beneath the IC are not
recommended. Figure 10. illustrates the layout, with bold
lines indicating high current paths; these traces must be
short and wide. Components along the bold lines should
be placed lose together. Below is a checklist for your
layout :
For the high-side and low-side MOSFETs, the losses are
approximately given by the following equations:
Phigh-side = IOUT 2(1+ TC)(RDS(ON))D + (0.5)( IOUT)(V )( tSW)FSW
IN
Plow-side = IOUT 2(1+ TC)(RDS(ON))(1-D)
Copyright ã ANPEC Electronics Corp.
19
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Rev. A.4 - Feb., 2009
APW7088
Application Information (Cont.)
Layout Consideration (Cont.)
·
Keep the switching nodes (UGATEx, LGATEx, BOOTx,
and PHASEx) away from sensitive small signal nodes
since these nodes are fast moving signals. Therefore,
keep traces to these nodes as short as possible and
there should be no other weak signal traces in paral-
lel with theses traces on any layer.
APW7088
VIN1=VIN
BOOT1
The signals going through theses traces have both
high dv/dt and high di/dt with high peak charging and
discharging current. The traces from the gate drivers
to the MOSFETs (UGATEx, LGATEx) should be short
and wide.
·
UGATE1
PHASE1
LGATE1
L1
RS1
·
·
Place the source of the high-side MOSFET and the
drain of the low-side MOSFET as close as possible.
Minimizing the impedance with wide layout plane be-
tween the two pads reduces the voltage bounce of
the node. In addition, the large layout plane between
the drain of the MOSFETs (VIN and PHASEx nodes)
can get better heat sinking.
CS1
VOUT
CSP1
CSN1
CSN2
CSP2
L
O
A
D
CS2
RS2
LGATE2
For experiment result of accurate current sensing, the
current sensing components are suggested to place
close to the inductor part. To avoid the noise
interference, the current sensing trace should be away
from the noisy switching nodes.
PHASE2
UGATE2
L2
·
·
Decoupling capacitors, the resistor-divider, and boot
capacitor should be close to their pins. (For example,
place the decoupling ceramic capacitor close to the
drain of the high-side MOSFET as close as possible).
The input bulk capacitors should be close to the drain
of the high-side MOSFET, and the output bulk capaci-
tors should be close to the loads. The input capaci-
tor’s ground should be close to the grounds of the
output capacitors and low-side MOSFET.
BOOT2
VIN2=VIN
Figure 10. Layout Guidelines
·
Locate the resistor-divider close to the FB pin to mini-
mize the high impedance trace. In addition, FB pin
traces can’t be close to the switching signal traces
(UGATEx, LGATEx, BOOTx, and PHASEx).
Copyright ã ANPEC Electronics Corp.
20
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Rev. A.4 - Feb., 2009
APW7088
Package Information
QFN4x4-24
D
A
Pin 1
D2
A1
A3
Pin 1 Corner
e
QFN4x4-24
S
Y
M
B
O
MILLIMETERS
INCHES
MIN.
MAX.
MIN.
MAX.
0.039
0.002
L
A
0.80
0.00
1.00
0.05
0.031
0.000
A1
A3
b
0.20 REF
0.008 REF
0.008
0.154
0.098
0.154
0.098
0.012
0.161
0.110
0.161
0.110
0.18
0.30
4.10
2.80
4.10
2.80
D
3.90
2.50
3.90
2.50
D2
E
E2
e
0.50 BSC
0.020 BSC
0.014
0.008
0.018
L
0.35
0.20
0.45
K
Note : 1. Followed from JEDEC MO-220 WGGD-6.
Copyright ã ANPEC Electronics Corp.
21
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Rev. A.4 - Feb., 2009
APW7088
Carrier Tape & Reel Dimensions
P0
P2
P1
OD0
A
K0
A0
A
OD1
B
B
SECTION A-A
SECTION B-B
d
T1
Application
QFN4x4-24
A
H
T1
C
d
D
W
E1
F
5.5±0.05
K0
12.4+2.00 13.0+0.50
330.0±2.00 50 MIN.
1.5 MIN.
D1
20.2 MIN. 12.0±0.30 1.75±0.10
-0.00 -0.20
P0
P1
P2 D0
T
A0
B0
1.5+0.10
-0.00
0.6+0.00
-0.40
4.0±0.10
8.0±0.10
2.0±0.05
1.5 MIN.
4.30±0.20 4.30±0.20 1.30±0.20
(mm)
Devices Per Unit
Package Type
QFN4x4-24
Unit
Quantity
3000
Tape & Reel
Copyright ã ANPEC Electronics Corp.
22
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Rev. A.4 - Feb., 2009
APW7088
Taping Direction Information
QFN4x4-24
USER DIRECTION OF FEED
Classification Profile
Copyright ã ANPEC Electronics Corp.
23
www.anpec.com.tw
Rev. A.4 - Feb., 2009
APW7088
Classification Reflow Profiles
Profile Feature
Preheat & Soak
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
Temperature min (Tsmin
)
Temperature max (Tsmax
)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
3 °C/second max.
3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL)
183 °C
60-150 seconds
217 °C
60-150 seconds
Peak package body Temperature
(Tp)*
See Classification Temp in table 1
20** seconds
See Classification Temp in table 2
30** seconds
Time (tP)** within 5°C of the specified
classification temperature (Tc)
Average ramp-down rate (Tp to Tsmax
)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Volume mm3
350
Package
Thickness
<2.5 mm
³ 2.5 mm
Volume mm3
<350
235 °C
220 °C
220 °C
220 °C
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
Volume mm3
Volume mm3
350-2000
260 °C
Volume mm3
<350
260 °C
260 °C
250 °C
>2000
260 °C
245 °C
245 °C
1.6 mm – 2.5 mm
³ 2.5 mm
250 °C
245 °C
Reliability Test Program
Test item
SOLDERABILITY
HOLT
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
Description
5 Sec, 245°C
1000 Hrs, Bias @ 125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV, VMM≧200V
10ms, 1tr≧100mA
PCT
TCT
ESD
Latch-Up
MIL-STD-883E-3015.7
JESD 78
Copyright ã ANPEC Electronics Corp.
24
www.anpec.com.tw
Rev. A.4 - Feb., 2009
APW7088
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright ã ANPEC Electronics Corp.
Rev. A.4 - Feb., 2009
25
www.anpec.com.tw
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