APW8720BQBI-TRG_技术文档

APW8720B

Single Buck Voltage Mode PWM Controller

Features

General Description

·

Wide 5V to 12V Supply Voltage

The APW8720B is a voltage mode, fixed 300kHz switch-

ing frequency, synchronous buck converter. The

APW8720B allows wide input voltage that is either a single

5~12V or two supply voltage(s) for various applications. A

power-on-reset (POR) circuit monitors the VCC supply

voltage to prevent wrong logic controls. A built-in soft-start

circuit prevents the output voltages from overshoot as

Power-On-Reset Monitoring on VCC

Excellent Output Voltage Regulations

- 0.8V Internal Reference

- ±1% Over-Temperature Range

Integrated Soft-Start

·

Voltage Mode PWM Operation with External

Compensation

well as limits the input current. An internal 0.8V tempera-

ture-compensated reference voltage with high accuracy

is designed to meet the requirement of low output volt-

age applications. The APW8720B provides excellent out-

put voltage regulations against load current variation.

The controller’s over-current protection monitors the out-

put current by using the voltage drop across the R_DS(ON)of

low-side MOSFET, eliminating the need for a current sens-

ing resistor that features high efficiency and low cost. In

addition, the APW8720B also integrates excellent protec-

tion functions: The over-voltage protection (OVP) , under-

voltage protection (UVP). OVP circuit which monitors the

FB voltage to prevent the PWM output from over-voltage,

and UVP circuit which monitors the FB voltage to prevent

the PWM output from under-voltage or short-circuit.

The APW8720B is available in SOP-8P and TDFN3x3-10

packages.

·

Up to 90%Duty Ratio for Fast Transient Response

Constant Switching Frequency

- 300kHz ±10%

·

9V Driver Voltage for BOOT Supply with Internal

BootstrapDiode

Drive Dual Low Cost N-MOSFETs with Adaptive

Dead-Time Control

·

50% Under-Voltage Protection

125% Over-Voltage Protection

Adjustable Over-Current Protection Threshold

- Using the R_DS(ON)of Low-Side MOSFET

Shutdown Control byCOMP

·

Power Good Monitoring (TDFN-10 3mmx3mm

Package Only)

·

SOP-8P and TDFN3x3-10 Packages

Lead Free and Green Devices Available

(RoHS Compliant)

Simplified Application Circuit

VCC

V_IN

Applications

APW8720B

BOOT

VCC

·

Graphic Cards

DSL, Switch HUB

Wireless Lan

UGATE

COMP

V_OUT

OFF

ON

PHASE

LGATE

FB

Notebook Computer

Mother Board

GND

LCD Monitor/TV

ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and

advise customers to obtain the latest version of relevant information to verify before placing orders.

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Rev. A.5 - Mar., 2012

APW8720B

Ordering and Marking Information

APW8720B

Package Code

KA : SOP-8P QB : TDFN3x3-10

Operating Ambient Temperature Range

I : -40 to 85 ^oC

Assembly Material

Handling Code

Temperature Range

Package Code

TR : Tape & Reel

Assembly Material

G : Halogen and Lead Free Device

APW8720B

APW8720B KA :

APW8720B QB :

XXXXX - Date Code

XXXXX

APW

8720B

XXXXX

Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which

are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for

MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen

free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by

weight).

Pin Configuration

BOOT

UGATE

1

2

3

4

5

10 NC

BOOT 1

UGATE 2

8 PHASE

7 COMP

9

8

7

6

POK

COMP

11

GND

9

GND

PHASE

GND 3

6 FB

5 VCC

GND

FB

LGATE/OCSET 4

LGATE/OCSET

VCC

TDFN3x3-10

(Top View)

SOP-8P

(Top View)

Absolute Maximum Ratings (Note 1)

Symbol

Parameter

VCC Supply Voltage (VCC to GND)

Rating

-0.3 ~ 16

-0.3 ~ 30

Unit

V

V_VCC

BOOT Supply Voltage (BOOT to PHASE)

BOOT Supply Voltage (BOOT to GND)

V

V_BOOT

V_UGATE

V_LGATE

V_PHASE

V

> 20ns

< 20ns

> 20ns

< 20ns

> 20ns

< 20ns

-0.3 ~ V_BOOT+0.3

-5 ~ V_BOOT+5

-0.3 ~ V_VCC+0.3

-5 ~ V_VCC+5

-0.3 ~ 16

V

UGATE Voltage (UGATE to PHASE)

LGATE Voltage (LGATE to GND)

PHASE Voltage (PHASE to GND)

V

-5 ~ 21

V

FB and COMP to GND

POK to GND

-0.3 ~ 7

V

-0.3~V_CC+0.3

150

V

T_J

Maximum Junction Temperature

°C

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APW8720B

Absolute Maximum Ratings (Note 1)

Symbol

Parameter

Rating

-65 ~ 150

260

Unit

°C

T_STG

Storage Temperature

Maximum Lead Soldering Temperature, 10 Seconds

T_SDR

°C

Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are

stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under

"recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may

affect device reliability.

Thermal Characteristics

Symbol

Parameter

Typical Value

Unit

Thermal Resistance -Junction to Ambient ^{(Note 2)}

SOP-8P

TDFN3x3-10

60

55

°C/W

q_JA

Note 2: q_JAis measured with the component mounted on a high effective thermal conductivity test board in free air.

Recommended Operating Conditions (Note 3)

Symbol

Parameter

Range

3.3 ~ 13.2

4.5 ~ 13.2

0.8 ~ 5.5

0 ~ 20

Unit

V

V_IN

VIN Supply Voltage

V_VCC

V_OUT

I_OUT

VCC Supply Voltage

Converter Output Voltage

Converter Output Current

Ambient Temperature

Junction Temperature

V

A

T_A

-40 ~ 85

-40 ~ 125

°C

T_J

Note 3: Refer to the application circuit for further information.

Electrical Characteristics

Refer to the typical application circuit. These specifications apply over V_VCC= 12V, T_A= -40°C to 85°C, unless otherwise

noted. Typical values are at T_A= 25°C.

APW8720B

Symbol

Parameter

Test Conditions

Unit

Min.

Typ.

Max.

INPUT SUPPLY VOLTAGE AND CURRENT

UGATE and LGATE open;

COMP=GND

VCC Supply Current (Shutdown Mode)

I_VCC

-

700

3

mA

VCC Supply Current

POWER-ON-RESET(POR)

Rising VCC POR Threshold

VCC POR Hysteresis

UGATE and LGATE open

2

mA

3.8

0.3

4.1

0.5

4.4

0.6

V

OSCILLATOR

F_OSC

DV_OSC

D_MAX

Oscillator Frequency

Oscillator Sawtooth Amplitude ^{(Note 4)}

270

300

1.5

-

330

-

kHz

V

(1.2V~2.7V typical)

-

Maximum Duty Cycle

90

%

REFERENCE

Reference Voltage

Converter Line/Load Regulation ^{(Note 4)}

T_A= -40 ~ 85°C

0.792

-0.2

0.8

-

0.808

0.2

V

V_REF

V_CC=4.5~13.2V, I_OUT= 0 ~ 20A

%

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APW8720B

Electrical Characteristics (Cont.)

Refer to the typical application circuit. These specifications apply over V_VCC= 12V, T_A= -40°C to 85°C, unless otherwise

noted. Typical values are at T_A= 25°C.

APW8720B

Symbol

Parameter

Test Conditions

Unit

Min.

Typ.

Max.

ERROR AMPLIFIER

gm

Transconductance ^{(Note 4)}

Open-Loop Bandwidth ^{(Note 4)}

FB Input Leakage Current

COMP High Voltage

-

667

20

-

mA/V

MHz

mA

-

R_L= 10kW, C_L= 10pF

V_FB= 0.8V

R_L= OPEN

V_COMP= 2V

0.1

3

-

V

COMP Low Voltage

1.5

200

Maximum COMP Source Current

Maximum COMP Sink Current

mA

GATE DRIVERS

High-Side Gate Driver Source Current

V_BOOT-GND= 9V, V_UGATE-PHASE= 3V

V_VCC= 12V, V_LGATE-GND= 6V

-

1.0

1.1

1.5

1.8

30

-

A

High-Side Gate Driver Sink Current

Low-Side Gate Driver Source Current

Low-Side Gate Driver Sink Current

Dead-Time ^{(Note 4)}

A

T_D

PROTECTIONS

V_{FB_UV}FB Under-Voltage Protection Trip Point Percentage of V_REF

ns

40

-

45

2

50

-

%

Under-Voltage Debounce Interval

ms

Under-Voltage Protection Enable

Delay

The same as soft -start interval

V_FBrising

1

1.5

2

ms

V_{FB_OV}

FB Over-Voltage Protection Trip Point

FB Over-Voltage Protection Hysteresis

Over-Voltage Debounce Interval

115

125

5

135

%

-

2

ms

V_{OCP_MAX}Built-in Maximum OCP Voltage

350

9

-

mV

mA

I_OCSET

OCSET Current Source

10

11

V_OCCSET-GNDVoltage, Over All

Temperature

V_ROCEST

OCP Threshold Setting Range

150

-

mV

SOFT-START

V_DISABLEShutdown Threshold of V_COMP

T_SS

Internal Soft-Start Interval ^{(Note 4)}

POWER OK INDICATOR (POK) (ONLY FOR TDFN3X3-10 PACKAGE)

-

0.4

2

V

1

1.5

ms

I_POK

POK Leakage Current

V_POK=5V

-

0.1

90

1

mA

VFB is from low to target value

(POK Goes High)

85

95

%

V_POK

POK Threshold

VFB Falling, POK Goes Low

VFB Rising, POK Goes Low

45

120

1

50

125

3

55

130

5

%

POK Delay Time

ms

Note 4: Guaranteed by design, not production tested.

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APW8720B

Operating Waveforms

Refer to the typical application circuit. The test condition is V_IN=12V, T_A=25^oC unless otherwise specified.

Power On

Power Off

V_IN

1

2

3

1

2

V_OUT

V_UGATE

3

CH1:V_IN, 5V/Div

CH2:V_OUT, 500m V/Div

CH3:V_UGATE, 10V/Div

TIM E:1m s/Div

CH2:V_OUT, 500m V/Div

CH3:VU_GATE, 10V/Div

TIM E:2m s/Div

Enable

Shutdown

R_LOAD=10W

V_{COM P}

1

V_OUT

2

3

2

3

V_PHASE

CH1:V_{COM P}, 1V/Div

CH2:V_OUT, 500m V/Div

CH3:V_PHASE, 10V/Div

TIM E:1m s/Div

CH1:V_{COM P}, 1V/Div

CH2:V_OUT, 500m V/Div

CH3:V_PHASE, 10V/Div

TIM E:2m s/Div

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APW8720B

Operating Waveforms (Cont.)

Refer to the typical application circuit. The test condition is V_IN=12V, T_A=25^oC unless otherwise specified.

Over-Current Protection

Under-Voltage Protection

OCP

V_OUT

1

UVP

I

L

2

CH1:V_OUT, 500m V/Div

CH2:I ,10A/Div

L

TIM E:5m s/Div

UGATEFalling

UGATERising

V_UGATE

1

2

1

V_LGATE

2

3

V_PHASE

3

CH1:V_UGATE, 20V/Div

CH2:V_LGATE,10V/Div

CH3:V_PHASE,10V/Div

TIM E:50ns/Div

CH1:V_UGATE, 20V/Div

CH2:V_LGATE,10V/Div

CH3:V_PHASE,10V/Div

TIM E:50ns/Div

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APW8720B

Operating Waveforms (Cont.)

Refer to the typical application circuit. The test condition is V_IN=12V, T_A=25^oC unless otherwise specified.

Power OK

Load Transient

V_{O UT}

1

V_{O UT}

1

2

V_{P OK}

I

O UT

2

CH1:V_OUT, 50m V/Div, AC

CH2:I_OUT, 5A/Div

CH1: V_OUT, 500mV/Div

CH2: V_POK, 5V/Div

TIME:1ms/Div

TIM E:200ms/Div

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APW8720B

Pin Description

NO.

FUNCTION

NAME

SOP-8P

TDFN3x3-10

This pin provides the bootstrap voltage to the high-side gate driver for driving the

N-channel MOSFET. An external capacitor from PHASE to BOOT, an internal

diode, and the boot supply voltage (9V), generates the bootstrap voltage for the

high-side gate driver (UGATE).

1

BOOT

2

3

2

4

UGATE

GND

High-side Gate Driver Output. This pin is the gate driver for high-side MOSFET.

Signal and Power ground. Connecting this pin to system ground.

Low-side Gate Driver Output and Over-Current Setting Input. This pin is the gate

driver for low-side MOSFET. It also used to set the maximum inductor current.

Refer to the section in “Function Description” for detail.

4

5

6

5

6

7

LGATE

VCC

FB

Power Supply Input. Connect a nominal 5V to 12V power supply voltage to this

pin. A power-on-reset function monitors the input voltage at this pin. It is

recommended that a decoupling capacitor (1 to 10mF) is connected to GND for

noise decoupling.

Feedback Input of Converter. The converter senses feedback voltage via FB and

regulates the FB voltage at 0.8V. Connecting FB with a resistor-divider from the

output sets the output voltage of the converter.

This is a multiplexed pin. During soft-start and normal converter operation, this pin

represents the output of the error amplifier. It is used to compensate the regulation

control loop in combination with the FB pin.

7

8

COMP

Pulling COMP low (V_DISABLE= 0.4V max.) will shut down the controller. When the

pull-down device is released, the COMP pin will start to rise. When the COMP pin

rises above the V_DISABLEtrip point, the APW8720B will begin a new initialization

and soft-start cycle.

This pin is the return path for the high-side gate driver. Connecting this pin to the

high-side MOSFET source and connect a capacitor to BOOT for the bootstrap

voltage. This pin is also used to monitor the voltage drop across the low-side

MOSFET for over-current protection.

8

9

3

PHASE

GND

11

Thermal Pad. Connect this pad to the system ground plan for good thermal

conductivity.

(Exposed Pad) (Exposed Pad)

POK is an open drain output used to indicate the status of the output voltage.

Connect the POK pin to 5 to 12V through a pull-high resistor.

-

9

POK

NC

10

No Connect

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APW8720B

Block Diagram

VCC

9V

Sam ple

and

Hold

I

OCSET

BOOT

Regulator

Power-On-Reset

(10mA typical)

Sense Low Side

UGATE

PHASE

V_ROCSET

V_REF

9V

To LGATE

UVP

(0.8V typical)

V_ROCSET

Soft-Start

and

FaultLogic

Com parator

0.5

VCC

Inhibit

Gate

LGATE

1.25

Control

OVP Com parator

Soft-start

0.9

ErrorAm plifier

PW M Com parator

Delay

Tim e

V_REF

Oscillator

0.4V

Disable

GND

POK

FB

COM P

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APW8720B

Typical Application Circuit

1. APW8720B 12V Application Circuit

V_INSupply 12V

R4

2R2

APW8720B

C_IN1

1mF

C_IN2

220mF x 2

C4

1mF

C3

0.1mF

BOOT

VCC

Q1

APM2510

UGATE

PHASE

LGATE

COMP

OFF

R6

10k

ON

C1

V_OUT=1.2V

C2

L1

33pF

47nF

Q3

2N7002

0.5mH

POK

FB

R2

10k

C_OUT

Q2

APM2556

1000mF x 2

~680mF x 2

R_OCSET

GND

R1

1k

R3

2k

C5

R5

22

10nF

2. APW8720B 5V Application Circuit

D1

V_INSupply 5V

Schottky Diode

R4

2R2

APW8720B

C_IN1

1mF

C_IN2

220mF x 2

C4

1mF

C3

0.1mF

BOOT

VCC

Q1

APM2510

UGATE

PHASE

LGATE

COMP

OFF

ON

R6

10k

V_OUT=1.2V

L1

C2

47nF

Q3

C1

0.5mH

POK

FB

R2

10k

2N7002

33pF

C_OUT

Q2

APM2556

1000mF x 2

~680mF x 2

R_OCSET

GND

R1

1k

R3

2k

R5

22

C5

10nF

Note: Power OK Indicator (POK) (only for TDFN3x3-10 package).

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APW8720B

Function Description

A resistor (R_OCSET), connected from the LGATE/OCSET to

GND, programs the over-current trip level. Before the IC

initiates a soft-start process, an internal current source,

I_OCSET(10mA typical), flowing through the R_OCSETdevelops

a voltage (V_ROCSET) across the R_OCSET. The device holds

V_ROCSETand stops the current source I_OCSETduring normal

operation. When the voltage across the low-side MOSFET

exceeds the V_ROCSET, the APW8720B turns off the high-

side and low-side MOSFET,and the device will enters

hiccup mode until the over-current phenomenon is

released.

Power-On-Reset (POR)

The Power-On-Reset (POR) function of APW8720B con-

tinually monitors the input supply voltage (VCC) and en-

sures that the IC has sufficient supply voltage and can

work well. The POR function initiates a soft-start process

while the VCC voltage just exceeds the POR threshold;

the POR function also inhibits the operations of the IC

while the VCC voltage falls below the POR threshold.

Soft-Start

The APW8720B builds in a soft-start function about

1.5ms (Typ.) interval, which controls the output voltage

rising as well as limiting the current surge at the start-up.

During soft-start, an internal ramp voltage connected to

the one of the positive inputs of the error amplifier re-

places the reference voltage (0.8V typical) until the ramp

voltage reaches the reference voltage. The soft-start cir-

cuit interval is shown as figure 1. The UVP function en-

able delay is from t2 to t3.

For avoid large inductor current occurring in short circuit

before power on, the controller reduces internal current

source, I_ocset, to half during soft start time.

It means that when APW8720B is in soft start interval, the

internal current source, I_ocset, is only 5mA (typical).

The APW8720B has an internal OCP voltage, V_{OCP_MAX}

and the value is 0.35V (minimum). When the R_OCSET

,

x

I_OCSETexceed 0.35V or the R_OCSETis floating or not

connected, the V_ROCSETwill be the default value 0.35V. The

over current threshold would be 0.35V across low-side

MOSFET. The threshold of the valley inductor current-limit

is therefore given by:

Voltage(V)

POK Delay Time

V_VCC

OCSET count completed

OCSET count start

(OCSET duratiom, t2-t₁, less than 1.3ms)

V_POK

I

_OCSET´ R_OCSET

I_LIMIT

=

R_DS(ON)(low - side)

0.9xV_REF

V_OUT

For the over-current is never occurred in the normal oper-

ating load range, the variation of all parameters in the

above equation should be considered:

t₀

t₁t₂

t₃t₄

Figure 1. Soft-Start Interval

Time

- The R_DS(ON)of low-side MOSFET is varied by tempera-

ture and gate to source voltage. Users should deter-

mine the maximum R_DS(ON)by using the manufacturer’s

datasheet.

Over-Current Protection of the PWM Converter

The over-current function protects the switching converter

against over-current or short-circuit conditions. The con-

troller senses the inductor current by detecting the drain-

to-source voltage which is the product of the inductor’s

current and the on-resistance of the low-side MOSFET

during it’s on-state. This method enhances the converter’s

efficiency and reduces cost by eliminating a current sens-

ing resistor required.

- The minimum I_OCSET(9mA) and minimum R_OCSETshould

be used in the above equation.

- Note that the I_LIMITis the current flow through the low-

side MOSFET; I_LIMITmust be greater than valley inductor

current which is output current minus the half of induc-

tor ripple current.

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APW8720B

Function Description (Cont.)

Over-Current Protection of the PWM Converter(Cont.)

Adaptive Shoot-Through Protection of the PWM Con-

verter

DI

The gate drivers incorporate an adaptive shoot-through

protection to prevent high-side and low-side MOSFETs

from conducting simultaneously and shorting the input

supply. This is accomplished by ensuring the falling gate

has turned off one MOSFET before the other is allowed to

rise.

I_LIMIT> I_OUT(MAX)

-

2

Where DI = output inductor ripple current

- The overshoot and transient peak current also should

be considered.

During turn-off the low-side MOSFET, the LGATE voltage

is monitored until it is below 1.5V threshold, at which

time the UGATE is released to rise after a constant delay.

During turn-off of the high-side MOSFET, the UGATE-to-

PHASE voltage is also monitored until it is below 1.5V

threshold, at which time the LGATE is released to rise

after a constant delay.

Under-Voltage Protection

The under-voltage function monitors the voltage on FB

(V_FB) byUnder-Voltage (UV) comparator to protect the PWM

converter against short-circuit conditions. When the V_FB

falls below the falling UVP threshold (50% V_REF), a fault

signal is internally generated and the device turns off high-

side and low-side MOSFETs. The device will enters hic-

cup mode until the under-voltage phenomenon is

released.

Power OK Indicator

The APW8720B features an open-drain POK output pin

to indicate one of the IC's working statuses including

soft-start, under-voltage fault, over-current fault.

Over-Voltage Protection (OVP) of the PWM Converter

The over-voltage protection monitors the FB voltage to

prevent the output from over-voltage condition. When the

output voltage rises above 125% of the nominal output

voltage, the APW8720B turns off the high-side MOSFET

and turns on the low-side MOSFET until the output volt-

age falls below the falling OVP threshold.

In normal operation, when the output voltage rises 90%

of its target value, the POK goes high. When the output

voltage outruns 50% or 125% of the target voltage, POK

signal will be pulled low immediately.

Shutdown and Enable

The APW8720B can be shut down or enabled by pulling

low the voltage on COMP. The COMP is a dual-function

pin. During normal operation, this pin represents the out-

put of the error amplifier. It is used to compensate the

regulation control loop in combination with the FB pin.

Pulling the COMP low (V_DISABLE= 0.4V maximum) places

the controller into shutdown mode which UGATE and

LGATE are pulled to PHASE and GND respectively.

When the pull-down device is released, the COMP volt-

age will start to rise. When the COMP voltage rises above

the V_DISABLEthreshold, the APW8720B will begin a new

initialization and soft-start process.

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APW8720B

Application Information

Output Voltage Selection

lower output ripple voltage. The ripple current and ripple

voltage can be approximated by:

The output voltage can be programmed with a resistive

divider. Use 1% or better resistors for the resistive divider

is recommended. The FB pin is the inverter input of the

error amplifier, and the reference voltage is 0.8V. The

output voltage is determined by:

V

- V_OUTV_OUT

IN

I_RIPPLE

=

´

F_SW´ L

V

IN

where Fs is the switching frequency of the regulator.

DV_OUT= I_RIPPLEx ESR

æ

ç

è

ö

÷

ø

R₁

R₂

A tradeoff exists between the inductor’s ripple current and

the regulator load transient response time. A smaller in-

ductor will give the regulator a faster load transient re-

sponse at the expense of higher ripple current and vice

versa. The maximum ripple current occurs at the maxi-

mum input voltage. A good starting point is to choose the

ripple current to be approximately 30% of the maximum

output current.

ç

V_OUT= 0.8 ´ 1+

Where R1 is the resistor connected from V_OUTto FB and

R2 is the resistor connected from FB to the GND.

Output Capacitor Selection

The selection of C_OUTis determined by the required effec-

tive series resistance (ESR) and voltage rating rather than

the actual capacitance requirement. Therefore, selecting

high performance low ESR capacitors is intended for

switching regulator applications. In some applications,

multiple capacitors have to be paralleled to achieve the

desired ESR value. If tantalum capacitors are used, make

sure they are surge tested by the manufactures. If in doubt,

consult the capacitors manufacturer.

Once the inductance value has been chosen, selecting

an inductor is capable of carrying the required peak cur-

rent without going into saturation. In some types of

inductors, especially core that is make of ferrite, the ripple

current will increase abruptly when it saturates. This will

result in a larger output ripple voltage.

Compensation

Input Capacitor Selection

The output LC filter of a step down converter introduces a

double pole, which contributes with -40dB/decade gain

slope and 180 degrees phase shift in the control loop. A

compensation network between COMP pin and ground

should be added. The simplest loop compensation net-

work is shown in Figure 5.

The input capacitor is chosen based on the voltage rat-

ing and the RMS current rating. For reliable operation,

select the capacitor voltage rating to be at least 1.3 times

higher than the maximum input voltage. The maximum

RMS current rating requirement is approximately I_OUT/2

where I_OUTis the load current. During power up, the input

capacitors have to handle large amount of surge current.

If tantalum capacitors are used, make sure they are surge

tested by the manufactures. If in doubt, consult the ca-

pacitors manufacturer.

The output LC filter consists of the output inductor and

output capacitors. The transfer function of the LC filter is

given by:

1+ s´ ESR´ C_OUT

s²´ L´ C_OUT+ s´ ESR´ C_OUT+1

GAIN_LC

=

For high frequency decoupling, a ceramic capacitor be-

tween 0.1mF to 1mF can connect between VCC and ground

pin.

The poles and zero of this transfer function are:

1

F

=

LC

2´ p ´ L´ COUT

Inductor Selection

1

F_ESR

=

2´ p´ ESR´ COUT

The inductance of the inductor is determined by the out-

put voltage requirement. The larger the inductance, the

lower the inductor’s current ripple. This will translate into

The FLC is the double poles of the LC filter, and FESR is

the zero introduced by the ESR of the output capacitor.

Copyright ã ANPEC Electronics Corp.

13

www.anpec.com.tw

Rev. A.5 - Mar., 2012

APW8720B

Application Information (Cont.)

Compensation (Cont.)

The compensation circuit is shown in Figure 5. R2 and

C2 introduce a zero and C1 introduces a pole to reduce

the switching noise. The transfer function of error ampli-

fier is given by:

L

Output

PHASE

C_OUT

ESR

é

ù

ú

æ

1

ö

1

ç

÷

GAIN_AMP= gm´ Z_O= gm´ R2 +

//

ê

ç

÷

sC2 sC1

ê

ú

û

è

ø

ë

æ

ö

1

çs +

÷

ç

R2´ C2

è

ø

= gm´

æ

ö

C2 + C1

R2´ C1´ C2

s´ çs +

÷´ C1

ç

÷

è

ø

Figure 2. The Output LC Filter

The pole and zero of the compensation network are:

1

F_LC

F_P=

C1´ C2

-40dB/dec

2´ p ´ R2´

C1+ C2

1

F_Z=

F_ESR

2´ p ´ R2´ C2

Gain

V_OUT

-20dB/dec

Error

Amplifier

R1

FB

-

COMP

Frequency

R3

Figure 3. The LC Filter Gain & Frequency

+

R2

C2

V_REF

The PWM modulator is shown in Figure 4. The input is

the output of the error amplifier and the output is the PHASE

node. The transfer function of the PWM modulator is given

by:

C1

V

IN

Figure 5. Compensation Network

GAIN_PWM

=

DV_OSC

V_IN

The closed loop gain of the converter can be written as:

R3

Driver

GAIN_LC´ GAIN_PWM

´

´ GAIN_AMP

R1+R3

PWM

Comparator

Figure 6 shows the converter gain and the following guide-

lines will help to design the compensation network.

1.Select the desired zero crossover frequency F_O:

V_OSC

Output of

Error

(1/5 ~ 1/10) x F_SW>F_O>F_Z

PHASE

Amplifier

Use the following equation to calculate R2:

DVOSC

F

ESR R1+R3

F

gm

O

R2 =

´

_LC2

VIN

R3

F

Driver

Where:

gm = 667mA/V

Figure 4. The PWM Modulator

Copyright ã ANPEC Electronics Corp.

14

www.anpec.com.tw

Rev. A.5 - Mar., 2012

APW8720B

Application Information (Cont.)

Compensation (Cont.)

where I_OUTis the load current

TC is the temperature dependency of R_DS(ON)

F_SWis the switching frequency

2. Place the zero F_Zbefore the LC filter double poles F_LC:

F_Z= 0.75 x F_LC

t_swis the switching interval

Calculate the C2 by the equation:

D is the duty cycle

1

C2 =

Note that both MOSFETs have conduction losses while

the upper MOSFET includes an additional transition loss.

The switching internal, t_sw, is the function of the reverse

transfer capacitance C_RSS. Figure 7 illustrates the switch-

ing waveform internal of the MOSFET.

2´ p ´ R2´ 0.75´ FLC

3. Set the pole at the half the switching frequency:

F_P= 0.5xF_SW

Calculate the C1 by the equation:

The (1+TC) term factors in the temperature dependency

of the R_DS(ON)and can be extracted from the “R_DS(ON)vs Tem-

perature” curve of the power MOSFET.

C2

C1=

p ´ R2´ C2´ F^SW- 1

V_DS

F_Z=0.75F_LC

F_P=0.5F_SW

20 ^.log(gm ^.R2)

Compensation

Gain

F_LC

V_IN

F_O

20^.log

DV_OSC

Converter

Gain

F_ESR

PWM &

Filter Gain

Frequency

t_sw

Time

Figure 6. Converter Gain & Frequency

MOSFETSelection

Figure 7. Switching Waveform Across MOSFET

Layout Consideration

The selection of the N-channel power MOSFETs is deter-

mined by the R_DS(ON), reverse transfer capacitance (C_RSS),

and maximum output current requirement.The losses in

the MOSFETs have two components: conduction loss and

transition loss. For the upper and lower MOSFET, the

losses are approximately given by the following equations:

In any high switching frequency converter, a correct lay-

out is important to ensure proper operation of the

regulator. With power devices switching at 300kHz,the

resulting current transient will cause voltage spike across

the interconnecting impedance and parasitic circuit

elements. As an example, consider the turn-off transition

of the PWM MOSFET. Before turn-off, the MOSFET is car-

rying the full load current. During turn-off, current stops

flowing in the MOSFET and is free-wheeling by the lower

MOSFET and parasitic diode. Any parasitic inductance of

the circuit generates a large voltage spike during the

switching interval. In general, using short and wide printed

circuit traces should minimize interconnecting imped

P_UPPER= I_OUT²(1+ TC)(R_DS(ON))D + (0.5)(I_out)(V_IN)(t_sw)F_SW

P_LOWER= I_OUT²(1+ TC)(R_DS(ON))(1-D)

Copyright ã ANPEC Electronics Corp.

15

www.anpec.com.tw

Rev. A.5 - Mar., 2012

APW8720B

Application Information (Cont.)

Layout Consideration (Cont.)

APW8720B

V_IN

ances and the magnitude of voltage spike. And signal

and power grounds are to be kept separate till combined

using ground plane construction or single point

grounding. Figure 8. illustrates the layout, with bold lines

indicating high current paths; these traces must be short

and wide. Components along the bold lines should be

placed lose together. Below is a checklist for your layout:

- Keep the switching nodes (UGATE, LGATE, and PHASE)

away from sensitive small signal nodes since these

nodes are fast moving signals. Therefore, keep traces

to these nodes as short as possible.

VCC

BOOT

L

O

A

D

UGATE

PHASE

R_OCSET

LGATE

V_OUT

Close to IC

- The traces from the gate drivers to the MOSFETs (UG

and LG) should be short and wide.

Figure 8. Layout Guidelines

- Place the source of the high-side MOSFET and the drain

of the low-side MOSFET as close as possible. Minimiz-

ing the impedance with wide layout plane between the

two pads reduces the voltage bounce of the node.

- Decoupling capacitor, compensation component, the

resistor dividers, and boot capacitors should be close

their pins. (For example, place the decoupling ceramic

capacitor near the drain of the high-side MOSFET as

close as possible. The bulk capacitors are also placed

near the drain).

- The input capacitor should be near the drain of the up-

per MOSFET; the output capacitor should be near the

loads. The input capacitor GND should be close to the

output capacitor GND and the lower MOSFET GND.

- The drain of the MOSFETs (V_INand PHASE nodes) should

be a large plane for heat sinking.

- The R_OCSETresistance should be placed near the IC as

close as possible.

Copyright ã ANPEC Electronics Corp.

16

www.anpec.com.tw

Rev. A.5 - Mar., 2012

APW8720B

Package Information

SOP-8P

D

SEE VIEW A

D1

THERMAL

PAD

e

b

c

GAUGE PLANE

SEATING PLANE

L

NX

aaa

c

VIEW A

SOP-8P

S

Y

M

B

O

L

MILLIMETERS

INCHES

MIN.

MAX.

1.60

MIN.

MAX.

0.063

0.006

A

0.000

0.049

0.012

0.007

0.189

0.098

0.228

0.150

0.079

0.15

A1

A2

b

0.00

1.25

0.31

0.17

4.80

2.50

5.80

3.80

2.00

0.020

0.010

0.197

0.138

0.244

0.157

0.118

0.51

0.25

5.00

3.50

6.20

4.00

3.00

c

D

D1

E

E1

E2

e

h

L

q

1.27 BSC

0.050 BSC

0.004

0.010

0.016

0°

0.020

0.050

8°

0.25

0.40

0°

0.50

1.27

8°

aaa

0.10

Note : 1. Followed from JEDEC MS-012 BA.

2. Dimension "D" does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion or gate burrs shall not exceed 6 mil per side .

3. Dimension "E" does not include inter-lead flash or protrusions.

Inter-lead flash and protrusions shall not exceed 10 mil per side.

Copyright ã ANPEC Electronics Corp.

Rev. A.5 - Mar., 2012

17

www.anpec.com.tw

APW8720B

Package Information

TDFN3x3-10

D

A

Pin 1

A1

A3

D2

NX

aaa

C

Pin 1 Corner

e

TDFN3x3-10

S

Y

M

B

O

L

MILLIMETERS

INCHES

MIN.

0.70

0.00

MAX.

MIN.

MAX.

0.031

0.002

A

0.80

0.05

0.028

0.000

A1

A3

b

0.20 REF

0.008 REF

0.007

0.114

0.087

0.114

0.055

0.012

0.122

0.106

0.122

0.069

0.18

2.90

2.20

2.90

1.40

0.30

3.10

2.70

3.10

1.75

D

D2

E

E2

e

0.50 BSC

0.08

0.016 BSC

0.012

0.008

0.020

L

0.30

0.20

0.50

K

aaa

0.003

Note : 1. Followed from JEDEC MO-229 VEED-5.

Copyright ã ANPEC Electronics Corp.

18

www.anpec.com.tw

Rev. A.5 - Mar., 2012

APW8720B

Carrier Tape & Reel Dimensions

P0

P2

P1

OD0

A

K0

A0

A

OD1

B

SECTION A-A

SECTION B-B

d

T1

Application

SOP-8P

A

H

T1

12.4+2.00 13.0+0.50

-0.00 -0.20

P2 D0

C

d

D

W

E1

F

5.5±0.05

K0

330.0±2.00 50 MIN.

1.5 MIN.

D1

20.2 MIN. 12.0±0.30 1.75±0.10

P0

4.0±0.10

A

P1

8.0±0.10

H

T

A0

B0

1.5+0.10

-0.00

0.6+0.00

-0.40

2.0±0.05

1.5 MIN.

d

6.40±0.20 5.20±0.20 2.10±0.20

Application

TDFN3x3-10

T1

C

D

W

E1

F

5.5±0.05

K0

12.4+2.00 13.0+0.50

-0.00 -0.20

330.0±2.00 50 MIN.

1.5 MIN.

D1

20.2 MIN. 12.0±0.30 1.75±0.10

P0

P1

P2 D0

T

A0

B0

1.5+0.10

-0.00

0.6+0.00

-0.40

4.0±0.10

8.0±0.10

2.0±0.05

1.5 MIN.

3.30±0.20 3.30±0.20 1.30±0.20

(mm)

Devices Per Unit

Package Type

SOP-8P

Unit

Quantity

Tape & Reel

2500

3000

TDFN3x3-10

Copyright ã ANPEC Electronics Corp.

19

www.anpec.com.tw

Rev. A.5 - Mar., 2012

APW8720B

Taping Direction Information

SOP-8P

USER DIRECTION OF FEED

TDFN3x3-10

USER DIRECTION OF FEED

Copyright ã ANPEC Electronics Corp.

20

www.anpec.com.tw

Rev. A.5 - Mar., 2012

APW8720B

Classification Profile

Classification Reflow Profiles

Profile Feature

Sn-Pb Eutectic Assembly

Pb-Free Assembly

Preheat & Soak

100 °C

150 °C

60-120 seconds

150 °C

200 °C

60-120 seconds

Temperature min (T_smin

)

Temperature max (T_smax

)

Time (T_sminto T_smax) (t_s)

Average ramp-up rate

(T_smaxto T_P)

3 °C/second max.

Liquidous temperature (T_L)

Time at liquidous (t_L)

183 °C

60-150 seconds

217 °C

60-150 seconds

Peak package body Temperature

(T_p)*

See Classification Temp in table 1

20** seconds

See Classification Temp in table 2

30** seconds

Time (t_P)** within 5°C of the specified

classification temperature (T_c)

Average ramp-down rate (T_pto T_smax

)

6 °C/second max.

6 minutes max.

8 minutes max.

Time 25°C to peak temperature

* Tolerance for peak profile Temperature (T_p) is defined as a supplier minimum and a user maximum.

** Tolerance for time at peak profile temperature (t_p) is defined as a supplier minimum and a user maximum.

Copyright ã ANPEC Electronics Corp.

21

www.anpec.com.tw

Rev. A.5 - Mar., 2012

APW8720B

Classification Reflow Profiles (Cont.)

Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)

Volume mm³

350

Package

Thickness

<2.5 mm

³ 2.5 mm

Volume mm³

<350

235 °C

220 °C

Table 2. Pb-free Process – Classification Temperatures (Tc)

Package

Thickness

<1.6 mm

Volume mm³

350-2000

260 °C

Volume mm³

<350

260 °C

250 °C

>2000

260 °C

245 °C

1.6 mm – 2.5 mm

³ 2.5 mm

250 °C

245 °C

Reliability Test Program

Test item

SOLDERABILITY

HOLT

Method

JESD-22, B102

JESD-22, A108

JESD-22, A102

JESD-22, A104

MIL-STD-883-3015.7

JESD-22, A115

JESD 78

Description

5 Sec, 245°C

1000 Hrs, Bias @ T_j=125°C

168 Hrs, 100%RH, 2atm, 121°C

500 Cycles, -65°C~150°C

VHBM≧2KV

PCT

TCT

HBM

MM

VMM≧200V

10ms, 1_tr≧100mA

Latch-Up

Customer Service

Anpec Electronics Corp.

Head Office :

No.6, Dusing 1st Road, SBIP,

Hsin-Chu, Taiwan, R.O.C.

Tel : 886-3-5642000

Fax : 886-3-5642050

Taipei Branch :

2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,

Sindian City, Taipei County 23146, Taiwan

Tel : 886-2-2910-3838

Fax : 886-2-2917-3838

Copyright ã ANPEC Electronics Corp.

Rev. A.5 - Mar., 2012

22

www.anpec.com.tw


型号：	APW8720BQBI-TRG
厂家：	ANPEC ELECTRONICS COROPRATION
描述：	Single Buck Voltage Mode PWM Controller 单降压电压模式PWM控制器控制器
文件：	总22页 (文件大小：639K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

APW8720BQBI-TRG [ANPEC]

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