APW8722BKAI-TRG [ANPEC]
5V to 12V Single Buck Voltage Mode PWM Controller; 5V至12V单电压降压型PWM控制器
| 型号： | APW8722BKAI-TRG |
| 厂家： | 
ANPEC ELECTRONICS COROPRATION |
| 描述： | 5V to 12V Single Buck Voltage Mode PWM Controller |
| 文件： | 总23页 (文件大小：664K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APW8722/A/B/C/D
5V to 12V Single Buck Voltage Mode PWM Controller
Features
General Description
·
·
·
Wide 5V to 12V Supply Voltage
The APW8722 is a voltage mode, fixed 200kHz/300kHz/
600kHz switching frequency, synchronous buck converter.
The APW8722 allows wide input voltage that is either a
single 5~12V or two supply voltage(s) for various
applications. A power-on-reset (POR) circuit monitors the
VCC supply voltage to prevent wrong logic controls. Abuilt-
in soft-start circuit prevents the output voltages from over-
shoot as well as limits the input current. An internal 0.6V
temperature-compensated reference voltage with high
accuracy is designed to meet the requirement of low out-
put voltage applications. The APW8722 provides excel-
lent output voltage regulations against load current
Power-On-Reset Monitoring on VCC
Excellent Output Voltage Regulations
- 0.6V Internal Reference for APW8722/A/D
- 0.8V Internal Reference for APW8722B/C
- ±0.6% Over-Temperature Range
Integrated Soft-Start
·
·
Voltage Mode PWM Operation with External
Compensation
·
·
Up to 90%Duty Ratio for Fast Transient Response
Constant Switching Frequency
- 300kHz ±10% for APW8722/B
- 200kHz ±10% for APW8722C
variation.
The controller’s over-current protection monitors the out-
- 600kHz ±10% for APW8722A/D
Integrated Bootstrap Forward P-CH MOSFET
put current by using the voltage drop across the RDS
(ON) of low-side MOSFET, eliminating the need for a cur-
rent sensing resistor that features high efficiency and
low cost. In addition, the APW8722 also integrates excel-
lent protection functions. The over-voltage protection (OVP)
, under-voltage protection (UVP). OVP circuit which moni-
tors the FB voltage to prevent the PWM output from over
voltage, and UVP circuit which monitors the FB voltage to
prevent the PWM output from under voltage or short circuit.
The APW8722 is available in SOP-8P packages
·
·
·
·
50% Under-Voltage Protection
125% Over-Voltage Protection
Adjustable Over-Current Protection Threshold
- Using the RDS(ON) of Low-Side MOSFET
Shutdown Control byCOMP
·
·
·
SOP-8P Package
Lead Free and Green Devices Available
(RoHS Compliant)
Applications
·
·
·
·
·
·
Graphic Cards
DSL, Switch HUB
Wireless Lan
Notebook Computer
Mother Board
LCD Monitor/TV
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright ã ANPEC Electronics Corp.
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Rev. A.3 - Jun., 2013
APW8722/A/B/C/D
Simplified Application Circuit
VVCC
VIN
1
2
5
BOOT
VCC
7
UGATE
COMP
OFF
APW8722
ON
VOUT
8
4
PHASE
LGATE
6
FB
GND
3
Ordering and Marking Information
APW8722/A/B/C/D
Package Code
KA : SOP-8P
Assembly Material
Handling Code
Operating Ambient Temperature Range
I : -40 to 85 oC
Handling Code
Temperature Range
Package Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
APW8722X
XXXXX
X – A/B/C/D
XXXXX - Date Code
APW8722/A/B/C/D KA :
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Pin Configuration
APW8722A
APW8722/B/C/D
BOOT 1
UGATE 2
OCSET 3
LGATE 4
8 PHASE
7 COMP
6 FB
BOOT 1
UGATE 2
8 PHASE
7 COMP
6 FB
9 GND
9 GND
GND 3
5 VCC
5 VCC
LGATE/OCSET 4
SOP-8P
SOP-8P
(top view)
(top view)
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Rev. A.3 - Jun., 2013
APW8722/A/B/C/D
Absolute Maximum Ratings (Note 1)
Symbol
Parameter
Rating
-0.3 ~ 16
Unit
V
VVCC
VCC Supply Voltage (VCC to GND)
BOOT Supply Voltage (BOOT to PHASE)
BOOT Supply Voltage (BOOT to GND)
-0.3 ~ 16
V
VBOOT
VUGATE
VLGATE
VPHASE
-0.3 ~ 32
V
> 20ns
< 20ns
> 20ns
< 20ns
> 20ns
< 20ns
-0.3 ~ VBOOT+0.3
-5 ~ VBOOT+5
-0.3 ~ VVCC+0.3
-5 ~ VVCC+5
-0.3 ~ 16
V
UGATE Voltage (UGATE to PHASE)
LGATE Voltage (LGATE to GND)
PHASE Voltage (PHASE to GND)
V
V
V
V
-5 ~ 25
V
FB ,COMP to GND
-0.3 ~ 7
V
POK to GND
-0.3~VCC+0.3
150
V
TJ
Maximum Junction Temperature
Storage Temperature
°C
°C
°C
TSTG
TSDR
-65 ~ 150
260
Maximum Lead Soldering Temperature, 10 Seconds
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom-
mended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Thermal Characteristics
Symbol
Parameter
Typical Value
Unit
Thermal Resistance -Junction to Ambient (Note 2)
°C/W
qJA
SOP-8P
60
Note 2: qJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Recommended Operating Conditions (Note 3)
Symbol
Parameter
Range
4.5 ~ 13.2
0.6 ~ 5
Unit
V
VVCC
VCC Supply Voltage (VCC to GND)
Converter Output Voltage for APW8722/A/D
Converter Output Voltage for APW8722B/C
Converter Input Voltage
V
VOUT
0.8 ~ 5
V
VIN
IOUT
TA
3~13.2
V
Converter Output Current
0 ~ 25
A
Ambient Temperature
-40 ~ 85
-40 ~ 125
°C
°C
TJ
Junction Temperature
Note 3: Refer to the application circuit for further information.
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Rev. A.3 - Jun., 2013
APW8722/A/B/C/D
Electrical Characteristics
Refer to the typical application circuit. These specifications apply over VVCC = 12V, TA = -40°C to 85°C, unless otherwise
noted. Typical values are at TA = 25°C.
APW8722
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
INPUT SUPPLY VOLTAGE AND CURRENT
UGATE and LGATE open;
COMP=GND
VCC Supply Current (Shutdown Mode)
IVCC
-
-
-
550
10
mA
VCC Supply Current
POWER-ON-RESET(POR)
Rising VCC POR Threshold
VCC POR Hysteresis
UGATE and LGATE open
2.5
mA
3.8
0.3
4.1
0.5
4.4
0.6
V
V
OSCILLATOR
For APW8722/B
For APW8722C
For APW8722A/D
(1.2V~2.7V typical)
270
180
540
-
300
200
600
1.5
-
330
220
660
-
FOSC
Oscillator Frequency
kHz
Oscillator Sawtooth Amplitude (Note 4)
Maximum Duty Cycle
V
DVOSC
DMAX
-
90
%
REFERENCE
APW8722/A/D Reference Voltage
APW8722B/C Reference Voltage
ERROR AMPLIFIER
Open-Loop GAIN (Note 4)
TA = -40 ~ 85°C
TA = -40 ~ 85°C
0.596
0.795
0.6
0.8
0.604
0.805
V
VREF
-
-
-
90
20
-
-
-
dB
MHz
mA
RL = 10kW, CL = 10pF
RL = 10kW, CL = 10pF
VFB = 0.6V
Open-Loop Bandwidth (Note 4)
FB Input Leakage Current
0.1
GATE DRIVERS
High-side Gate Driver Source Current
High-side Gate Driver Sink Current
Low-side Gate Driver Source Current
Low-side Gate Driver Sink Current
Dead-time (Note 4)
VBOOT= 12V, VUGATE-PHASE = 6V
VBOOT= 12V, VUGATE-PHASE = 6V
VVCC = 12V, VLGATE-GND = 6V
VVCC = 12V, VLGATE-GND = 6V
-
-
-
-
-
1.0
1.1
1.8
2.0
30
-
-
-
-
-
A
TD
PROTECTIONS
FB Under-Voltage Protection Trip Point Percentage of VREF
ns
45
-
50
2
55
-
%
VFB_UV
Under-Voltage Debounce Interval
ms
Under-Voltage Protection Enable
Delay
-
1.5
125
105
-
ms
%
FB Over-Voltage Protection Rising
Threshold
VFB rising
VFB falling
120
100
130
110
VFB_OV
FB Over-Voltage Protection Falling
Threshold
%
Over-Voltage Debounce Interval
Built-in Maximum OCP Voltage
OCSET Current Source
-
-
2
-
-
ms
mV
mA
1200
10
VOCP_MAX
IOCSET
9
11
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Rev. A.3 - Jun., 2013
APW8722/A/B/C/D
Electrical Characteristics (Cont.)
Refer to the typical application circuit. These specifications apply over VVCC = 12V, TA = -40°C to 85°C, unless otherwise
noted. Typical values are at TA = 25°C.
APW8722
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
SOFT-START
Shutdown Threshold of VCOMP
-
-
-
0.4
-
V
VDISABLE
TSS
Internal Soft-Start Interval (Note 4)
1.5
ms
Note 4: Guaranteed by design, not production tested.
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Rev. A.3 - Jun., 2013
APW8722/A/B/C/D
Typical Operating Characteristics
Reference Voltage vs. Junction
Efficiency vs. Load Current
FSW=300KHz, VOUT=1.2V
Temperature
0.61
VCC = 12V
90
85
80
0.605
0.6
0.595
0.59
75
70
VIN=12V
H-Side:APW 3109x1
L-Side:APW 3116x1
65
60
-20
0
20
40
60
80
100 120
0.1
10.0
1
20.0
Junction Temperature (o
)
C
Output Current (A)
Switching Frequency vs. Junction
Temperature
Switching Frequency vs. Junction
Temperature
350
340
650
640
630
620
610
600
590
580
570
560
550
330
320
310
300
290
280
270
260
250
-20
0
20
40
60
80
(oC)
100 120
-20
0
20
40
60
80
(oC)
100 120
Junction Temperature
Junction Temperature
IOCSET vs. Junction Temperature
Load Regulation
0.3
0.2
11.4
11
10.6
10.2
9.8
0.1
0
-0.1
-0.2
9.2
8.8
8.2
-0.3
0
2
4
6
8
10
-20
0
20
40
60
80
(oC)
100 120
Output Current (A)
Junction Temperature
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Rev. A.3 - Jun., 2013
APW8722/A/B/C/D
Operating Waveforms
Refer to the typical application circuit. The test condition is VIN=12V, TA= 25oC unless otherwise specified.
Power On
Power Off
VIN
VIN
1
1
2
3
VOUT
VOUT
2
3
VUG ATE
VUG ATE
CH1:VIN,5V/Div
CH1:VIN,5V/Div
CH2:VOUT,500m V/Div
CH3:VUGATE, 10V/Div
CH2:VOUT,500m V/Div
CH3:VUGATE,10V/Div
TIM E:1m s/Div
TIM E:50m s/Div
Enable
Shutdown
RLOAD =12Ω
VCOM P
1
VCOM P
1
VOUT
VOUT
2
3
2
3
VPHASE
VPHASE
CH1:VEN,5V/Div,DC
CH2:VOUT, 500m V/Div, DC
CH3:VPHASE,10V/Div,DC
TIM E:1m s/Div
CH1:VCOM P, 1V/Div
CH2:VOUT,500m V/Div
CH3:VPHASE,10V/Div
TIM E:10m s/Div
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Rev. A.3 - Jun., 2013
APW8722/A/B/C/D
Operating Waveforms
Refer to the typical application circuit. The test condition is VIN=12V, TA= 25oC unless otherwise specified.
Over-Current Protection
Under-Voltage Protection
ROCSET=open ,RDS (low Side =12.5m Ω
)
VOUT
VFB
UVP
UVP
UVP
1
2
3
1
2
VPHASE
O CP
I
L
I
L
CH1:VOUT,500m V/Div
CH1:VFB,200m V/Div
CH2:VPHASE,10V/Div
CH2:I ,10A/Div
L
CH3:I ,10A/Div
L
TIM E:20m s/Div
TIM E:10us/Div
UGATEFalling
UGATERising
VUGATE
1
VUGATE
VPHASE
VLGATE
1
VLGATE
2
2
VPHASE
3
3
CH1:VUGATE,20V/Div
CH2:VLGATE,10V/Div
CH3:VPHASE,10V/Div
TIM E:20ns/Div
CH1:VUGATE,20V/Div
CH2:VLGATE,10V/Div
CH3:VPHASE,10V/Div
TIM E:20ns/Div
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Rev. A.3 - Jun., 2013
APW8722/A/B/C/D
Operating Waveforms
Refer to the typical application circuit. The test condition is VIN=12V, TA= 25oC unless otherwise specified.
Load Transient
VOUT
1
I
OUT
2
CH1:VOUT,50m V/Div,AC
CH2:IOUT, 5A/Div
TIM E:200us/Div
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Rev. A.3 - Jun., 2013
APW8722/A/B/C/D
Pin Description
PIN
No.
Function Description
Name
APW8722A
APW8722/B/C/D
This pin provides the bootstrap voltage to the high-side gate driver for
driving the N-channel MOSFET. An external capacitor from PHASE to
BOOT, an internal switch generates the bootstrap voltage for the
high-side gate driver (UGATE).
1
1
BOOT
High-side Gate Driver Output. This pin is the gate driver for high-side
MOSFET.
2
-
2
3
UGATE
GND
Signal and Power ground. Connecting this pin to system ground.
Current-Limit Threshold Setting Pin. There is an internal source current
10uA through a resistor from OCSET pin to GND. This pin is used to
monitor the voltage drop across the Drain and Source of the low-side
MOSFET for current-limit
3
-
OCSET
LGATE
Output of The Low-side MOSFET Driver. Connect this pin to the low-side
MOSFET.
4
-
-
Low-side Gate Driver Output and Over-Current Setting Input. This pin is
the gate driver for low-side MOSFET. It also used to set the maximum
inductor current. Refer to the section in “Function Description” for detail.
LGATE/
OCSET
4
Power Supply Input. Connect a nominal 5V to 12V power supply voltage
to this pin. A power-on reset function monitors the input voltage at this
pin. It is recommended that a decoupling capacitor (1 to 10µF) be
connected to GND for noise decoupling.
5
6
5
6
VCC
FB
Feedback Input of Converter. The converter senses feedback voltage via
FB and regulates the FB voltage at 0.6V/0.8V. Connecting FB with a
resistor-divider from the output sets the output voltage of the converter.
This is a multiplexed pin. During soft-start and normal converter
operation, this pin represents the output of the error amplifier. It is used to
compensate the regulation control loop in combination with the FB pin.
7
7
COMP
Pulling COMP low (VDISABLE = 0.4V max.) will shut down the controller.
When the pull-down device is released, the COMP pin will start to rise.
When the COMP pin rises above the VDISABLE trip point, the APW8722 will
begin a new initialization and soft-start cycle.
This pin is the return path for the high-side gate driver. Connecting this
pin to the high-side MOSFET source and connect a capacitor to BOOT
for the bootstrap voltage. This pin is also used to monitor the voltage drop
across the low-side MOSFET for over-current protection.
8
8
PHASE
GND
Thermal Pad. Connect this pad to the system ground plan for
good thermal conductivity.
9
9
(Exposed Pad)
(Exposed Pad)
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Rev. A.3 - Jun., 2013
APW8722/A/B/C/D
Block Diagram
VCC
IOCSET
(10µA typical)
Power-On
Reset
BOOT
Sample
and Hold
Regulator
Sense Low
Side
UGATE
VREF
VROCSET
To
LGATE
(0.6V/0.8V typical)
PHASE
UVP
VROCSET
Comparator
0.5
Soft Start
and
IZCMP
VCC
Fault Logic
Inhibit
OVP
Gate
Control
Comparator
1.25
LGATE
Soft-start
Error Amplifier
PWM
Comparator
VREF
Oscillator
0.4V
Disable
FB
GND
COMP
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Rev. A.3 - Jun., 2013
APW8722/A/B/C/D
Typical Application Circuit
For APW8722/B/C/D
VCC Supply
(5~12V)
VIN
R4
2R2
CIN1
1µF
CIN2
C4
1µF
220µF x 2
C3
0.1µF
1
2
5
7
BOOT
VCC
Q1
UGATE
COMP
APM 2510
L1
OFF
ON
C1
C2
100nF
R2
4.7kW
APW8722
VOUT
8
4
100pF
PHASE
Q3
2N7002
0.5µH
LGATE/
OCSET
Q2
COUT
APM 2556
6
1000µF x 2
FB
ROCSET
GND
3
R1
1kW
R2
1kW
R3
C3
1kW
22nF
For APW8722A
VCC Supply
(5~12V)
VIN
R4
2R2
CIN1
1µF
CIN2
APW8722(SOP-8OP)
C4
1µF
220µF x 2
C3
0.1µF
1
5
BOOT
VCC
Q1
2
UGATE
7
APM 251
0
COMP
OFF
ON
C1
L1
C2
100nF
R2
4.7kW
VOUT
8
100pF
PHASE
Q3
0.5µH
2N7002
Q2
4
COUT
LGATE
APM 255
6
6
1000µF x 2
FB
OCSET
3
ROCSET
R1
R3
1kW
1kW
R3
1kW
C3
22nF
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Rev. A.3 - Jun., 2013
APW8722/A/B/C/D
Function Description
A resistor (ROCSET), connected from the LGATE/OCSET to
GND, programs the over-current trip level. Before the IC
initiates a soft-start process, an internal current source,
IOCSET (10mA typical), flowing through the ROCSET develops
a voltage (VROCSET) across the ROCSET. The device holds
VROCSET and stops the current source IOCSET during normal
operation. When the voltage across the low-side MOSFET
exceeds the VROCSET, the APW8722 turns off the high-side
and low-side MOSFET,and the device will enters hiccup
mode until the over-current phenomenon is released.
Power-On-Reset (POR)
The Power-On-Reset (POR) function of APW8722 con-
tinually monitors the input supply voltage (VCC) and en-
sures that the IC has sufficient supply voltage and can
work well. The POR function initiates a soft-start process
while the VCC voltage just exceeds the POR threshold;
the POR function also inhibits the operations of the IC
while the VCC voltage falls below the POR threshold.
Soft-Start
For avoid large inductor current occurring in short circuit
before power on, the controller reduces internal current
source, Iocset, to half during soft start time. It means that
when APW8722 is in soft start interval, the internal cur-
rent source, Iocset, is only 5mA (typical).
The APW8722 builds in a soft-start function about 1.5ms
(Typ.) interval, which controls the output voltage rising as
well as limiting the current surge at the start-up. During
soft-start, an internal ramp voltage connected to the one
of the positive inputs of the error amplifier replaces the
reference voltage (0.6V typical) until the ramp voltage
reaches the reference voltage. The soft-start circuit inter-
val is shown as figure 1.
The APW8722 has an internal OCP voltage, VOCP_MAX, and
the value is 1.2V (typical). When the ROCSET x IOCSET exceed
1.2V or the ROCSET is floating or not connected, the VROCSET
will be the default value 1.2V. The over current threshold
would be 1.2V across low-side MOSFET. The threshold
of the valley inductor current-limit is therefore given by:
Voltage(V)
POK Delay Time
VVCC
OCSET count completed
OCSET count start
(OCSET duratiom, t2-t1, less than 0.9ms)
2´ IOCSET ´ ROCSET
ILIMIT
=
VPOK
RDS(ON)(low - side)
0.9xVREF
VOUT
For the over-current is never occurred in the normal oper-
ating load range, the variation of all parameters in the
above equation should be considered:
t0
t1 t2
t3 t4
Time
- The RDS(ON) of low-side MOSFET is varied by tempera-
ture and gate to source voltage. Users should deter-
mine the maximum RDS(ON) by using the manufacturer’s
datasheet.
Figure 1. Soft-Start Interval
Over-Current Protection of the PWM Converter
- The minimum IOCSET (9mA) and minimum ROCSET should
be used in the above equation.
The over-current function protects the switching converter
against over-current or short-circuit conditions. The con-
troller senses the inductor current by detecting the drain-
to-source voltage which is the product of the inductor’s
current and the on-resistance of the low-side MOSFET
during it’s on-state. This method enhances the converter’s
efficiency and reduces cost by eliminating a current sens-
ing resistor required.
- Note that the ILIMIT is the current flow through the low-
side MOSFET; ILIMIT must be greater than valley inductor
current which is output current minus the half of induc-
tor ripple current.
DI
ILIMIT > IOUT(MAX)
-
2
Where DI = output inductor ripple current
- The overshoot and transient peak current also should
be considered.
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Rev. A.3 - Jun., 2013
APW8722/A/B/C/D
Function Description (Cont.)
Adaptive Shoot-Through Protection of the PWM Con-
verter
Under-Voltage Protection
The gate drivers incorporate an adaptive shoot-through
protection to prevent high-side and low-side MOSFETs
from conducting simultaneously and shorting the input
supply. This is accomplished by ensuring the falling gate
has turned off one MOSFET before the other is allowed to
rise.
The under-voltage function monitors the voltage on FB
(VFB) byUnder-Voltage (UV) comparator to protect the PWM
converter against short-circuit conditions. When the VFB
falls below the falling UVP threshold (50% VREF), a fault
signal is internally generated and the device turns off high-
side and low-side MOSFETs. The device will enters hic-
cup mode until the under-voltage phenomenon is
released.
During turn-off the low-side MOSFET, the LGATE voltage
is monitored until it is below 1.5V threshold, at which
time the UGATE is released to rise after a constant delay.
During turn-off of the high-side MOSFET, the UGATE-to-
PHASE voltage is also monitored until it is below 1.5V
threshold, at which time the LGATE is released to rise
after a constant delay.
Over-Voltage Protection (OVP) of the PWM Converter
The over-voltage protection monitors the FB voltage to
prevent the output from over-voltage condition. When the
output voltage rises above 125% of the nominal output
voltage, the APW8722 turns off the high-side MOSFET
and turns on the low-side MOSFET until the output volt-
age falls below the falling below 105%, the OVP com-
parator is disengaged and both high-side and low-side
drivers turn off.
This OVP scheme only clamps the voltage overshoot and
does not invert the output voltage when otherwise acti-
vated with a continuously high output from low-side
MOSFET driver. It’s a common problem for OVP schemes
with a latch. Once an over-voltage fault condition is set, it
can be reset by releasing COMP or toggling VCC power-
on-reset signal.
Shutdown and Enable
The APW8722 can be shut down or enabled by pulling
low the voltage on COMP. The COMP is a dual-function
pin. During normal operation, this pin represents the out-
put of the error amplifier. It is used to compensate the
regulation control loop in combination with the FB pin.
Pulling the COMP low (VDISABLE = 0.4V maximum) places
the controller into shutdown mode which UGATE and
LGATE are pulled to PHASE and GND respectively.
When the pull-down device is released, the COMP volt-
age will start to rise. When the COMP voltage rises above
the VDISABLE threshold, the APW8722 will begin a new ini-
tialization and soft-start process.
Copyright ã ANPEC Electronics Corp.
14
www.anpec.com.tw
Rev. A.3 - Jun., 2013
APW8722/A/B/C/D
Application Information
Output Voltage Selection
lower output ripple voltage. The ripple current and ripple
voltage can be approximated by:
The output voltage can be programmed with a resistive
divider. Use 1% or better resistors for the resistive divider
is recommended. The FB pin is the inverter input of the
error amplifier, and the reference voltage is 0.6V. The
output voltage is determined by:
V
- VOUT VOUT
IN
IRIPPLE
=
´
FSW ´ L
V
IN
where Fs is the switching frequency of the regulator.
DVOUT = IRIPPLE x ESR
æ
ç
è
ö
÷
÷
ø
R1
R2
A tradeoff exists between the inductor’s ripple current and
the regulator load transient response time. A smaller in-
ductor will give the regulator a faster load transient re-
sponse at the expense of higher ripple current and vice
versa. The maximum ripple current occurs at the maxi-
mum input voltage. A good starting point is to choose the
ripple current to be approximately 30% of the maximum
output current.
ç
VOUT = 0.6 ´ 1+
Where R1 is the resistor connected from VOUT to FB and
R2 is the resistor connected from FB to the GND.
Output Capacitor Selection
The selection of COUT is determined by the required effec-
tive series resistance (ESR) and voltage rating rather than
the actual capacitance requirement. Therefore, selecting
high performance low ESR capacitors is intended for
switching regulator applications. In some applications,
multiple capacitors have to be paralleled to achieve the
desired ESR value. If tantalum capacitors are used, make
sure they are surge tested by the manufactures. If in doubt,
consult the capacitors manufacturer.
Once the inductance value has been chosen, selecting
an inductor is capable of carrying the required peak cur-
rent without going into saturation. In some types of
inductors, especially core that is make of ferrite, the ripple
current will increase abruptly when it saturates. This will
result in a larger output ripple voltage.
PWM Compensation
Input Capacitor Selection
The output LC filter of a step down converter introduces a
double pole, which contributes with -40dB/decade gain
slope and 180 degrees phase shift in the control loop. A
compensation network among COMP, FB, and VOUT
should be added. The compensation network is shown in
Figure 5. The output LC filter consists of the output induc-
tor and output capacitors. The transfer function of the LC
filter is given by:
The input capacitor is chosen based on the voltage rat-
ing and the RMS current rating. For reliable operation,
select the capacitor voltage rating to be at least 1.3 times
higher than the maximum input voltage. The maximum
RMS current rating requirement is approximately IOUT/2
where IOUT is the load current. During power up, the input
capacitors have to handle large amount of surge current.
If tantalum capacitors are used, make sure they are surge
tested by the manufactures. If in doubt, consult the ca-
pacitors manufacturer.
1
F
=
ESR
2´ p ´ ESR´ COUT
The FLC is the double poles of the LC filter, and FESR is the
zero introduced by the ESR of the output capacitor.
For high frequency decoupling, a ceramic capacitor be-
tween 0.1mF to 1mF can connect between VCC and ground
pin.
VPHASE
L
VOUT
Inductor Selection
COUT
ESR
The inductance of the inductor is determined by the out-
put voltage requirement. The larger the inductance, the
lower the inductor’s current ripple. This will translate into
Figure 2. The Output LC Filter
Copyright ã ANPEC Electronics Corp.
15
www.anpec.com.tw
Rev. A.3 - Jun., 2013
APW8722/A/B/C/D
Application Information(Cont.)
The poles and zeros of the transfer function are:
1
FLC
FZ1
=
2´ p ´ R2´ C2
1
-40dB/dec
FZ2
=
2´ p ´
(
R1+ R3
)
´ C3
1
F
=
=
P1
C1´ C2
æ
ö
÷
ø
2´ p ´ R2´
ç
FESR
C1+ C2
è
1
F
P2
2´ p ´ R3´ C3
-20dB/dec
C1
R3
C3
R2
C2
VOUT
Frequency(Hz)
FB
VCOMP
R1
Figure 3. The LC Filter GAIN and Frequency
VREF
The PWM modulator is shown in Figure 4. The input is
the output of the error amplifier and the output is the
PHASE node. The transfer function of the PWM modulator
is given by:
Figure 5. Compensation Network
The closed loop gain of the converter can be written as:
GAINLC X GAINPWM X GAINAMP
V
IN
GAINPWM
=
DVOSC
Figure 6. shows the asymptotic plot of the closed loop
converter gain, and the following guidelines will help to
design the compensation network. Using the below
guidelines should give a compensation similar to the
curve plotted. A stable closed loop has a -20dB/ decade
slope and a phase margin greater than 45 degree.
VIN
Driver
OSC
PWM
Comparator
ΔVOSC
PHASE
Output of
Error Amplifier
1. Choose a value for R1, usually between 1K and 5K.
2. Select the desired zero crossover frequency
FO: (1/5 ~ 1/10) X FS >FO>FESR
Driver
Figure 4. The PWM Modulator
Use the following equation to calculate R2:
The compensation network is shown in Figure 5. It
provides a close loop transfer function with the highest
zero crossover frequency and sufficient phase margin.
The transfer function of error amplifier is given by:
DVOSC FO
R2 =
´
´ R1
V
F
LC
IN
3. Place the first zero FZ1 before the output LC filter double
pole frequency FLC.
1
1
æ
ö
÷
ø
// R2 +
ç
FZ1 = 0.75 X FLC
VCOMP
VOUT
sC1
sC2
è
GAINAMP
=
=
Calculate the C2 by the equation:
1
æ
ö
R1// R3 +
ç
÷
1
sC3
è
ø
C2 =
2´ p ´ R2´ FLC ´ 0.75
æ
ö
ö
1
1
æ
ç
´ s +
÷
÷
s +
ç
è
÷
ç
R2´ C2
(
R1+ R3
)
´ C3
R1+ R3
ø
è
ø
=
´
C1+ C2
1
R1´ R3´ C1
æ
ö æ
ö
s s +
´
s +
ç
÷ ç
ø è
÷
R2´ C1´ C2
R3´ C3
è
ø
Copyright ã ANPEC Electronics Corp.
16
www.anpec.com.tw
Rev. A.3 - Jun., 2013
APW8722/A/B/C/D
Application Information(Cont.)
MOSFETSelection
4. Set the pole at the ESR zero frequency FESR
FP1 = FESR
:
The selection of the N-channel power MOSFETs is deter-
mined by the RDS(ON), reverse transfer capacitance (CRSS),
and maximum output current requirement.The losses in
the MOSFETs have two components: conduction loss and
transition loss. For the upper and lower MOSFET, the
losses are approximately given by the following equations:
Calculate the C1 by the equation:
C2
C1=
2´ p ´ R2´ C2´ F
- 1
ESR
5. Set the second pole FP2 at the half of the switching
frequency and also set the second zero FZ2 at the output LC
filter double pole FLC. The compensation gain should not
exceed the error amplifier open loop gain, check the
compensation gain at FP2 with the capabilities of the error
amplifier.
PUPPER = IOUT2 (1+ TC)(RDS(ON))D + (0.5)(Iout)(VIN)(tsw)FSW
PLOWER = IOUT2 (1+ TC)(RDS(ON))(1-D)
where IOUT is the load current
TC is the temperature dependency of RDS(ON)
FSW is the switching frequency
FP2 = 0.5 X FS
FZ2 = FLC
tsw is the switching interval
D is the duty cycle
Combine the two equations will get the following component
Note that both MOSFETs have conduction losses while
the upper MOSFET includes an additional transition loss.
The switching internal, tsw, is the function of the reverse
transfer capacitance CRSS. Figure 7 illustrates the switch-
ing waveform internal of the MOSFET.
calculations:
1+ s´ ESR´ COUT
s2 ´ L´ COUT + s´ ESR´ COUT +1
GAINLC
=
The poles and zero of this transfer functions are:
1
The (1+TC) term factors in the temperature dependency
of the RDS(ON) and can be extracted from the “RDS(ON) vs Tem-
perature” curve of the power MOSFET.
F
=
LC
2´ p ´ L´ COUT
R1
FS
R3 =
C3 =
- 1
VDS
2´ F
LC
1
p ´ R3´ FS
FZ1 FZ2 FP1 FP2
Compensation
Gain
20log
(R2/R1)
20log
(VIN/ΔVOSC
)
tsw
Time
FLC
Figure 7. Switching Waveform Across MOSFET
FESR
Converter
Gain
PWM & Filter
Gain
Frequency(Hz)
Figure 6. Converter Gain and Frequency
Copyright ã ANPEC Electronics Corp.
17
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Rev. A.3 - Jun., 2013
APW8722/A/B/C/D
Application Information (Cont.)
Layout Consideration
- The drain of the MOSFETs (VIN and PHASE nodes) should
be a large plane for heat sinking.
In any high switching frequency converter, a correct lay-
out is important to ensure proper operation of the
regulator. With power devices switching at 300kHz,the
resulting current transient will cause voltage spike across
the interconnecting impedance and parasitic circuit
elements. As an example, consider the turn-off transition
of the PWM MOSFET. Before turn-off, the MOSFET is car-
rying the full load current. During turn-off, current stops
flowing in the MOSFET and is free-wheeling by the lower
MOSFET and parasitic diode. Any parasitic inductance of
the circuit generates a large voltage spike during the
switching interval. In general, using short and wide printed
circuit traces should minimize interconnecting imped
- The ROCSET resistance should be placed near the IC as
close as possible.
APW8722
VIN
VCC
BOOT
L
O
A
UGATE
D
PHASE
ances and the magnitude of voltage spike. And signal
and power grounds are to be kept separate till combined
using ground plane construction or single point
grounding. Figure 8. illustrates the layout, with bold lines
indicating high current paths; these traces must be short
and wide. Components along the bold lines should be
placed lose together. Below is a checklist for your layout:
ROCSET
LGATE
VOUT
Close to IC
Figure 8. Layout Guidelines
- Keep the switching nodes (UGATE, LGATE, and PHASE)
away from sensitive small signal nodes since these
nodes are fast moving signals. Therefore, keep traces
to these nodes as short as possible.
- The traces from the gate drivers to the MOSFETs (UG
and LG) should be short and wide.
- Place the source of the high-side MOSFET and the drain
of the low-side MOSFET as close as possible. Minimiz-
ing the impedance with wide layout plane between the
two pads reduces the voltage bounce of the node.
- Decoupling capacitor, compensation component, the
resistor dividers, and boot capacitors should be close
their pins. (For example, place the decoupling ceramic
capacitor near the drain of the high-side MOSFET as
close as possible. The bulk capacitors are also placed
near the drain).
- The input capacitor should be near the drain of the up-
per MOSFET; the output capacitor should be near the
loads. The input capacitor GND should be close to the
output capacitor GND and the lower MOSFET GND.
Copyright ã ANPEC Electronics Corp.
18
www.anpec.com.tw
Rev. A.3 - Jun., 2013
APW8722/A/B/C/D
Package Information
SOP-8P
-T-
SEATING PLANE < 4 mils
SEE VIEW A
D
D1
THERMAL
PAD
c
b
e
NX
GAUGE PLANE
SEATING PLANE
aaa
c
L
VIEW A
SOP-8P
S
Y
M
B
O
L
MILLIMETERS
INCHES
MIN.
MAX.
1.60
MIN.
MAX.
0.063
0.006
A
0.000
0.049
0.012
0.007
0.189
0.098
0.228
0.150
0.079
0.15
A1
A2
0.00
1.25
0.31
0.17
4.80
2.50
5.80
3.80
2.00
b
0.51
0.25
5.00
3.50
6.20
4.00
3.00
0.020
0.010
0.197
0.138
0.244
0.157
0.118
c
D
D1
E
E1
E2
e
1.27 BSC
0.050 BSC
0.004
0.010
0.016
0oC
0.020
0.050
8oC
0.25
0.40
0oC
0.50
1.27
8oC
h
L
°
aaa
0.10
Note : 1. Followed from JEDEC MS-012 BA.
2. Dimension "D" does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side .
3. Dimension "E" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
Copyright ã ANPEC Electronics Corp.
19
www.anpec.com.tw
Rev. A.3 - Jun., 2013
APW8722/A/B/C/D
Carrier Tape & Reel Dimensions
P0
P2
P1
OD0
A
K0
A0
A
OD1
B
B
SECTION A-A
SECTION B-B
d
T1
Application
SOP-8P
A
H
T1
12.4+2.00 13.0+0.50
-0.00 -0.20
P2 D0
C
d
D
W
E1
F
330.0±2.00 50 MIN.
1.5 MIN.
D1
20.2 MIN. 12.0±0.30 1.75±0.10
5.5±0.05
P0
P1
T
A0
B0
K0
1.5+0.10
-0.00
0.6+0.00
-0.40
4.0±0.10
8.0±0.10
2.0±0.05
1.5 MIN.
6.40±0.20 5.20±0.20
2.10±0.20
(mm)
Devices Per Unit
Package Type
SOP-8P
Unit
Quantity
2500
Tape & Reel
Copyright ã ANPEC Electronics Corp.
20
www.anpec.com.tw
Rev. A.3 - Jun., 2013
APW8722/A/B/C/D
Taping Direction Information
SOP-8
USER DIRECTION OF FEED
Classification Profile
Copyright ã ANPEC Electronics Corp.
21
www.anpec.com.tw
Rev. A.3 - Jun., 2013
APW8722/A/B/C/D
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
Preheat & Soak
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
Temperature min (Tsmin
)
Temperature max (Tsmax
)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
3 °C/second max.
3 °C/second max.
Liquidous temperature (TL)
Time at liquidous (tL)
183 °C
60-150 seconds
217 °C
60-150 seconds
Peak package body Temperature
(Tp)*
See Classification Temp in table 1
20** seconds
See Classification Temp in table 2
30** seconds
Time (tP)** within 5°C of the specified
classification temperature (Tc)
Average ramp-down rate (Tp to Tsmax
)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Volume mm3
350
Package
Thickness
<2.5 mm
³ 2.5 mm
Volume mm3
<350
235 °C
220 °C
220 °C
220 °C
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
Volume mm3
Volume mm3
350-2000
260 °C
Volume mm3
<350
260 °C
260 °C
250 °C
>2000
260 °C
245 °C
245 °C
1.6 mm – 2.5 mm
³ 2.5 mm
250 °C
245 °C
Reliability Test Program
Test item
SOLDERABILITY
HOLT
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
PCT
TCT
HBM
MM
VMM≧200V
10ms, 1tr≧100mA
Latch-Up
Copyright ã ANPEC Electronics Corp.
22
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Rev. A.3 - Jun., 2013
APW8722/A/B/C/D
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright ã ANPEC Electronics Corp.
Rev. A.3 - Jun., 2013
23
www.anpec.com.tw
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