APW8723QBI-TRG [ANPEC]
5V to 12V Single Buck Voltage Mode PWM Controller; 5V至12V单电压降压型PWM控制器
| 型号： | APW8723QBI-TRG |
| 厂家： | 
ANPEC ELECTRONICS COROPRATION |
| 描述： | 5V to 12V Single Buck Voltage Mode PWM Controller |
| 文件： | 总23页 (文件大小：721K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APW8723
5V to 12V Single Buck Voltage Mode PWM Controller
Features
General Description
The APW8723 is a voltage mode, fixed 300kHz switching
·
·
·
Wide 5V to 12V Supply Voltage
frequency, synchronous buck converter. The APW8723
allows wide input voltage that is either a single 5V~12V
or two supply voltage(s) for various applications. The
power-on-reset (POR) circuit monitors the VCC supply
voltage to prevent wrong logic controls. A built-in soft-start
circuit prevents the output voltages from overshoot as
well as limits the input current. An internal 0.8V tempera-
ture-compensated reference voltage with high accuracy
is designed to meet the requirement of low output volt-
age applications. The APW8723 provides excellent out-
put voltage regulations against load current variation.
APW8723 is built in reference voltage offset function for
applications that require adjusting supply voltage.
The controller’s over-current protection monitors the out-
put current by using the voltage drop across the RDS(ON) of
low-side MOSFET, eliminating the need for a current sens-
ing resistor that features high efficiency and low cost. In
addition, the APW8723 also integrates excellent protec-
tion functions, The over-voltage protection (OVP) , under-
voltage protection (UVP) and over-temperature protec-
tion (OTP). OVP circuit which monitors the FB voltage to
prevent the PWM output from over voltage, and UVP cir-
cuit which monitors the FB voltage to prevent the PWM
output from under voltage or short circuit. OTP circuit which
monitors the junction temperature to prevent over-heat-
ing conditions.
Power-On-Reset Monitoring on VCC
Excellent Output Voltage Regulations
- 0.8V Internal Reference
- ±1% Over Temperature Range
Integrated Soft-Start
·
·
Voltage Mode PWM Operation with External
Compensation
·
·
Up to 90%Duty Ratio for Fast Transient Response
Constant Switching Frequency
- 300kHz ±10%
·
·
Integrated Bootstrap Forward P-CH MOSFET
Drive Dual Low Cost N-MOSFETs with Adaptive
Dead Time Control
·
·
·
50% Under-Voltage Protection
125% Over-Voltage Protection
Adjustable Over-Current Protection Threshold
- Using the RDS(ON) of Low-Side MOSFET
Shutdown Control byCOMP
·
·
·
·
Power Good Monitoring
TDFN3x3-10 Package
Lead Free and Green Devices Available
(RoHS Compliant)
The APW8723 is available in TDFN3x3-10 package.
Applications
·
·
·
·
·
·
Graphic Cards
DSL, Switch HUB
Wireless Lan
Notebook Computer
Mother Board
LCD Monitor/TV
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright ã ANPEC Electronics Corp.
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Rev. A.2 - Apr., 2013
APW8723
Simplified Application Circuit
VIN
APW8723 (TDFN3x3-10)
BOOT
UGATE
COMP
PHASE
LGATE/
OCSET
OFS
REFOUT
Current Controller
Ordering and Marking Information
Package Code
QB : TDFN3x3-10
APW8723
Operating Ambient Temperature Range
Assembly Material
Handling Code
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
Temperature Range
Package Code
APW
8723
APW8723 QB :
XXXXX - Date Code
XXXXX
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Pin Configuration
BOOT 1
10 REPOUT
9 OFS
8 POK
UGATE
PHASE
2
3
4
5
7 COMP
LGATE/OCSET
VCC
6
FB
TDFN3x3-10
(Top View)
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Rev. A.2 - Apr., 2013
APW8723
Absolute Maximum Ratings (Note 1)
Symbol
Parameter
VCC Supply Voltage (VCC to GND)
Rating
-0.3 ~ 16
Unit
V
VVCC
BOOT Supply Voltage (BOOT to PHASE)
-0.3 ~ 16
V
VBOOT
> 40ns
< 40ns
> 40ns
< 40ns
> 40ns
< 40ns
> 40ns
< 40ns
-0.3 ~ 32
V
BOOT Supply Voltage (BOOT to GND)
-0.3 ~ 40
V
-0.3 ~ VBOOT+0.3
-5 ~ VBOOT+5
-0.3 ~ VVCC+0.3
-5 ~ VVCC+5
-0.3 ~ 16
V
VUGATE
VLGATE
VPHASE
UGATE Voltage (UGATE to PHASE)
LGATE Voltage (LGATE to GND)
PHASE Voltage (PHASE to GND)
V
V
V
V
-5 ~ 30
V
FB and COMP to GND
-0.3 ~ 7
V
POK to GND
-0.3~VCC+0.3
150
V
TJ
Maximum Junction Temperature
Storage Temperature
°C
°C
°C
TSTG
TSDR
-65 ~ 150
260
Maximum Lead Soldering Temperature, 10 Seconds
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom-
mended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Thermal Characteristics
Symbol
Parameter
Typical Value
Unit
Thermal Resistance -Junction to Ambient (Note 2)
°C/W
qJA
TDFN3x3-10
55
Note 2: qJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Recommended Operating Conditions (Note 3)
Symbol
Parameter
Range
4 ~ 13.2
4.5 ~ 13.2
0.8 ~ 5
Unit
V
VIN
VIN Supply Voltage
VVCC
VOUT
IOUT
VCC Supply Voltage
Converter Output Voltage
Converter Output Current
Ambient Temperature
Junction Temperature
V
V
0 ~ 25
A
TA
-40 ~ 85
-40 ~ 125
°C
°C
TJ
Note 3: Refer to the application circuit for further information.
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Rev. A.2 - Apr., 2013
APW8723
Electrical Characteristics
Refer to the typical application circuit. These specifications apply over VVCC = 12V, TA = -40°C to 85°C, unless otherwise noted. Typical
values are at TA = 25°C.
APW8723
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
INPUT SUPPLY VOLTAGE AND CURRENT
UGATE and LGATE open;
COMP=GND
VCC Supply Current (Shutdown Mode)
IVCC
-
-
-
550
3
mA
VCC Supply Current
POWER-ON-RESET(POR)
Rising VCC POR Threshold
VCC POR Hysteresis
UGATE and LGATE open
2
mA
3.8
0.3
4.1
0.5
4.4
0.6
V
V
OSCILLATOR
Oscillator Frequency
270
300
1.5
-
330
-
kHz
V
FOSC
DVOSC
DMAX
Oscillator Sawtooth Amplitude (Note 4) (1.2V~2.7V typical)
Maximum Duty Cycle
-
-
90
%
REFERENCE
Reference Voltage
TA = -40 ~ 85°C
0.792
0.8
0.808
V
VREF
ERROR AMPLIFIER
Transconductance (Note 4)
-
-
-
667
20
-
-
uA/V
MHz
mA
gm
Open-Loop Bandwidth (Note 4)
FB Input Leakage Current
RL = 10kW, CL = 10pF
VFB = 0.8V
-
0.1
Maximum COMP Source Current
Maximum COMP Sink Current
VCOMP=2V
200
200
uA
VCOMP=2V
uA
GATE DRIVERS
High-side Gate Driver Source Current
VBOOT-GND= 12V, VUGATE-PHASE = 6V
VBOOT-GND= 12V, VUGATE-PHASE = 6V
VVCC = 12V, VLGATE-GND = 6V
-
-
-
-
-
1.0
1.1
1.8
2.0
30
-
-
-
-
-
A
High-side Gate Driver Sink Current
Low-side Gate Driver Source Current
Low-side Gate Driver Sink Current
Dead-time (Note 4)
A
VVCC = 12V, VLGATE-GND = 6V
ns
TD
PROTECTIONS
FB Under-Voltage Protection Trip Point Percentage of VOFS
45
-
50
2
55
-
%
VFB_UV
Under-Voltage Debounce Interval
ms
FB Over-Voltage Protection Rising
Threshold
VFB rising
120
125
130
%
VFB_OV
FB Over-Voltage Protection Hysteresis VFB falling
Over-Voltage Debounce Interval
-
-
20
2
-
%
-
ms
VOCSET=IOCSET×ROCSET
OCP setting Range
55
621
-
600
759
mV
mV
Built-in Maximum OCP Voltage
690
VOCP_MAX
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Rev. A.2 - Apr., 2013
APW8723
Electrical Characteristics (Cont.)
Refer to the typical application circuit. These specifications apply over VVCC = 12V, TA = -40°C to 85°C, unless otherwise noted. Typical
values are at TA = 25°C.
APW8723
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
PROTECTIONS (cont.)
OCSET Current Source
9
-
10
140
40
11
-
IOCSET
mA
oC
oC
Over-Temperature Protection
Threshold
Hysteresis
-
-
SOFT-START
Internal Soft-Start Interval (Note 4)
VOUT from 0% to 90% Regulation
-
-
2
-
-
ms
V
TSS
COMP VOLTAGE
Shutdown Threshold of VCOMP
0.4
VDISABLE
OFS FUNCTION
REFOUT current limiting
Only sourcing
VPOK=5V
-
2
-
-
mA
V
OFS setting range
0.4
3
POWER GOOD (Only for TDFN3×3-10 Package)
POK Leakage Current
POK Threshold
-
0.1
90
50
1
IPOK
mA
VFB is from low to target value
(POK Goes High)
85
95
%
VPOK
VFB Falling, POK Goes Low
VFB Rising, POK Goes Low
45
55
%
%
120
125
1.5
130
Vref=90% regulation to POK goes
high
POK Delay Time
-
-
ms
Note 4: Guaranteed by design, not production tested.
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Rev. A.2 - Apr., 2013
APW8723
Typical Operating Characteristics
Reference Voltage vs. Junction
Switching Frequency vs. Junction
Temperature
Temperature
0.81
350
340
VCC = 12V
330
320
310
300
290
280
270
260
250
0.805
0.8
0.795
0.79
-20
0
20
40
60
80
100 120
-20
0
20
40
60
80
100 120
(oC)
(oC)
Junction Temperature
Junction Temperature
Load Regulation
Line Regulation
0.2
0.1
0
0.3
0.2
VCC=12V
IL=0A
Vout=1.2V
0.1
0
-0.1
-0.1
-0.2
-0.2
-0.3
0
2
4
6
8
10
4
5
6
7
8
9
10 11 12 13
Output Current (A)
Input Voltage(V)
IOCSET vs. Junction Temperature
11.4
11
10.6
10.2
9.8
9.4
9
8.6
-20
0
20
40
60
80
(oC)
100 120
Junction Temperature
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Rev. A.2 - Apr., 2013
APW8723
Operating Waveforms
Refer to the typical application circuit. The test condition is VIN=12V, TA= 25oC unless otherwise specified.
Power On
Power Off
VIN
VIN
1
2
VOUT
1
2
VOUT
VUGATE
VUG ATE
3
3
CH1:VIN,5V/Div
CH1:VIN,5V/Div
CH2:VOUT,1V/Div
CH3:VUGATE,10V/Div
CH2:VOUT,1V/Div
CH3:VUGATE, 10V/Div
TIM E:1m s/Div
TIM E:50m s/Div
Enable
Shutdown
VCOM P
VCOM P
1
1
VOUT
VOUT
2
2
VUG ATE
VUGATE
3
3
CH1:VCOM P, 1V/Div
CH2:VOUT,1V/Div
CH3:VUGATE,10V/Div
CH1:VCOM P, 1V/Div
CH2:VOUT,1V/Div
CH3:VUGATE,10V/Div
TIM E:1m s/Div
TIM E:1m s/Div
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Rev. A.2 - Apr., 2013
APW8723
Operating Waveforms
Refer to the typical application circuit. The test condition is VIN=12V, TA= 25oC unless otherwise specified.
Over-Current Protection
Under-Voltage Protection
ROCSET =6.8kΩ,RDS (low Side )=10.5m Ω
VOUT
VOUT
1
2
VPHASE
1
I
L
I
L
3
2
CH1:VOUT, 1V/Div
CH1:VOUT,1V/Div
CH2:VPHASE,10V/Div
CH2:I ,10A/Div
L
CH3:I ,10A/Div
L
TIM E:1m s/Div
TIM E:10us/Div
UGATEFalling
UGATERising
VUGATE
VUGATE
1
2
1
2
3
VLGATE
VPHASE
VPHASE
VLGATE
3
CH1:VUGATE,20V/Div
CH2:VLGATE ,10V/Div
CH3:VPHASE ,10V/Div
TIM E:20ns/Div
CH1:VUGATE,20V/Div
CH2:VLGATE ,10V/Div
CH3:VPHASE ,10V/Div
TIM E:20ns/Div
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Rev. A.2 - Apr., 2013
APW8723
Operating Waveforms
Refer to the typical application circuit. The test condition is VIN=12V, TA= 25oC unless otherwise specified.
Power OK
Load Transient
VOUT
1
VOUT
1
2
I
OUT
Pok
2
CH1:VOUT,50m V/Div,AC
CH2:IOUT, 5A/Div
CH1:VOUT, 1V/Div
CH2:POK,5V/Div
TIM E:200us/Div
TIM E:1m s/Div
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Rev. A.2 - Apr., 2013
APW8723
Pin Description
PIN
FUNCTION
NO.
NAME
TDFN3x3-10
This pin provides the bootstrap voltage to the high-side gate driver for driving the N-channel
MOSFET. An external capacitor (0.1mF at least) from PHASE to BOOT, an internal switch
generates the bootstrap voltage for the high-side gate driver (UGATE).
1
BOOT
High-side Gate Driver Output. This pin is the gate driver for high-side MOSFET.
2
3
UGATE
PHASE
This pin is the return path for the high-side gate driver. Connecting this pin to the high-side
MOSFET source and connect a capacitor to BOOT for the bootstrap voltage. This pin is also
used to monitor the voltage drop across the low-side MOSFET for over-current protection.
Low-side Gate Driver Output and Over-Current Setting Input. This pin is the gate driver for
low-side MOSFET. It also used to set the maximum inductor current. Refer to the section in
“Function Description” for detail.
LGATE/
OCSET
4
5
6
Power Supply Input. Connect a nominal 5V to 12V power supply voltage to this pin. A
power-on reset function monitors the input voltage at this pin. It is recommended that a
decoupling capacitor (1mF to 10mF) be connected to GND for noise decoupling.
VCC
FB
Feedback Input of Converter. The converter senses feedback voltage via FB and regulates
the FB voltage at 0.8V. Connecting FB with a resistor-divider from the output sets the output
voltage of the converter.
This is a multiplexed pin. During soft-start and normal converter operation, this pin represents
the output of the error amplifier. It is used to compensate the regulation control loop in
combination with the FB pin.
7
8
COMP
Pulling COMP low (VDISABLE = 0.4V max.) will shut down the controller. When the pull-down
device is released, the COMP pin will start to rise. When the COMP pin rises above the
VDISABLE trip point, the APW8723 will begin a new initialization and soft-start cycle.
POK is an open drain output used to indicate the status of the output voltage. Connect the
POK pin to 5 to 12V through a pull-high resistor.
POK
OFS
Reference Voltage Offset Setting. Must connect this pin to REFOUT pin through a resister
when APW8723 is used. Operated an installation that can make bi-direction current flow within
limits to develop a positive and negative voltage difference between OFS pin and REFOUT
pin, then the APW8723 can adjust reference voltage.
9
0.8V Reference Output. Bypass to GND with a capacitor (0.01mF to 0.1mF).
10
REFOUT
GND
11
Signal and Power ground. Connect this pad to the system ground plan for good thermal
conductivity.
(Exposed Pad)
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APW8723
Block Diagram
VCC
Power-On Reset
UVLO
BOOT
IOCSET
(10µA typical)
Sample
and Hold
Regulator
Sense Low Side
UGATE
PHASE
VREF
To
LGATE
(0.8V typical )
VROCSET
UVP
VROCSET
Comparator
0.5
Soft Start
and
IZCMP
VCC
Fault Logic
Inhibit
OVP
Gate
Control
Comparator
1.25
LGATE
Soft-start
Error Amplifier
PWM
Comparator
VREF
(0.8V typical )
REFOUT
Oscillator
0.4V
Disable
OFS FB
COMP
GND
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APW8723
Typical Application Circuit
VCC Supply
(5~12V)
VIN
R4
2R2
CIN1
CIN2
APW8723 (TDFN3*3-10)
C4
1mF
C3
1mF
220mF x 2
1
5
8
BOOT
VCC
0.1mF
Q1
2
POK
UGATE
APM310
9
R5 100kW
7
L1
COMP
VOUT
OFF
Exposed
3
4
ON
PHASE
pad
0.5µH
GND
Q3
2N7002
Q2
APM3106
LGATE/
OCSET
R2
10kW
COUT
6
C1
33pF
FB
1000mF x 2
ROCSET
OFS
9
C2
47nF
REFOUT
10
ROFFSET
C5
0.1mF
R3
R1
2kW
1kW
Current Controller
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Rev. A.2 - Apr., 2013
APW8723
Function Description
A resistor (ROCSET), connected from the LGATE/OCSET to
GND, programs the over-current trip level. Before the IC
initiates a soft-start process, an internal current source,
IOCSET (10mA typical), flowing through the ROCSET develops
a voltage (VROCSET) across the ROCSET. The device holds
VROCSET and stops the current source IOCSET during normal
operation. When the voltage across the low-side MOSFET
exceeds the VROCSET, the APW8723 turns off the high side
and low-side MOSFET, and the device will enter hiccup
mode until the over-current phenomenon is released.
The APW8723 has an internal OCP voltage, VOCP_MAX, and
the value is 0.621V(minmum). When the ROCSET x IOCSET
exceed 0.621V or the ROCSET is floating or not connected,
the VROCSET will be the default value 0.621V. The over cur-
rent threshold would be 0.621V across low-side MOSFET.
The threshold of the valley inductor current limit is there-
fore given by:
Power-On-Reset (POR)
The Power-On-Reset (POR) function of APW8723 con-
tinually monitors the input supply voltage (VCC) and en-
sures that the IC has sufficient supply voltage and can
work well. The POR function initiates a soft-start process
while the VCC voltage just exceeds the POR threshold;
the POR function also inhibits the operations of the IC
while the VCC voltage falls below the POR threshold.
Soft-Start
The APW8723 builds in a soft-start function about 2ms
(Typ.) interval, which controls the output voltage rising as
well as limiting the current surge at the start-up. During
soft-start, an internal ramp voltage connected to the one
of the positive inputs of the error amplifier replaces the
reference voltage (0.8V typical) until the ramp voltage
reaches the reference voltage. The soft-start circuit inter-
val is shown as figure 1.
IOCSET ´ ROCSET
ILIMIT
=
RDS(ON)(low - side)
Voltage(V)
For the over-current is never occurred in the normal oper-
ating load range, the variation of all parameters in the
above equation should be considered:
POK Delay
Soft Start
Time
Time
VVCC
OCSET count completed
OCSET count start
(OCSET duratiom, t2- t1, less than 0.474ms)
VPOK
- The RDS(ON) of low-side MOSFET is varied by tempera-
ture and gate to source voltage. Users should deter-
mine the maximum RDS(ON) by using the manufacturer’s
datasheet.
0.9 xVREF
VOUT
- The minimum IOCSET (9mA) and minimum ROCSET should
be used in the above equation.
t0
t1 t2
t3
t4
- Note that the ILIMIT is the current flow through the low-
side MOSFET; ILIMIT must be greater than valley inductor
current which is output current minus the half of induc-
tor ripple current.
Time
Figure 1. Soft-Start Interval
Over-Current Protection of the PWM Converter
The over-current function protects the switching converter
against over-current or short-circuit conditions. The con-
troller senses the inductor current by detecting the drain-
to-source voltage which is the product of the inductor’s
current and the on-resistance of the low-side MOSFET
during it’s on-state. This method enhances the converter’s
efficiency and reduces cost by eliminating a current sens-
ing resistor required.
DI
ILIMIT > IOUT(MAX)
-
2
Where DI = output inductor ripple current
- The overshoot and transient peak current also should
be considered.
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Rev. A.2 - Apr., 2013
APW8723
Function Description (Cont.)
Under-Voltage Protection
the controller into shutdown mode which UGATE and
LGATE are pulled to PHASE and GND respectively.
When the pull-down device is released, the COMP volt-
age will start to rise. When the COMP voltage rises above
the VDISABLE threshold, the APW8723 will begin a new ini-
tialization and soft-start process.
The under-voltage function monitors the voltage on FB
(VFB) byUnder-Voltage (UV) comparator to protect the PWM
converter against short-circuit conditions. When the VFB
falls below the falling UVP threshold (50% VREF), a fault
signal is internally generated and the device turns off high-
side and low-side MOSFETs. The device will enters hic-
cup mode until the UVP is released.
Adaptive Shoot-Through Protection of the PWM Con-
verter
Over-Voltage Protection (OVP)
The gate drivers incorporate an adaptive shoot-through
protection to prevent high-side and low-side MOSFETs
from conducting simultaneously and shorting the input
supply. This is accomplished by ensuring the falling gate
has turned off one MOSFET before the other is allowed to
rise.
The over-voltage protection monitors the FB voltage to
prevent the output from over-voltage condition. When the
output voltage rises above 125% of the nominal output
voltage, the APW8723 turns off the high-side MOSFET
and turns on the low-side MOSFET until the output volt-
age falls below 105%, the OVP comparator is disen-
gaged and both high-side and low-side drivers turn off.
This OVP scheme only clamps the voltage overshoot and
does not invert the output voltage when otherwise acti-
vated with a continuously high output from low-side
MOSFET driver. It’s a common problem for OVP schemes
with a latch. Once an over-voltage fault condition is set, it
can be reset by releasing COMP or toggling VCC power-
on-reset signal.
During turn-off the low-side MOSFET, the LGATE voltage
is monitored until it is below 1.5V threshold, at which
time the UGATE is released to rise after a constant delay.
During turn-off of the high-side MOSFET, the UGATE-to-
PHASE voltage is also monitored until it is below 1.5V
threshold, at which time the LGATE is released to rise
after a constant delay.
Reference Voltage Offset Functionr
For some special applications like over-clocking Purpose
or variety output voltage choice, the APW8723 can pro-
vide reference voltage offset function to support these
applications. It must connect OFS pin to REFOUT pin
through a resister (ROFFSET) when APW8723 is used. Op-
erated an installation that can make bi-direction cur-
rent flow within limits to develop a positive and negative
voltage difference between OFS pin and REFOUT pin,
then the APW8723 can adjust reference voltage. It is de-
termined by:
Over-Temperature Protection (OTP)
When the junction temperature increases above the ris-
ing threshold temperature TOTR, the IC will enter the
over-temperature protection state that suspends the
PWM, which forces the UGATE and LGATE gate drivers
output low. The thermal sensor allows the converters to
start a start-up process and regulate the output voltage
again after the junction temperature cools by 40oC. The
OTP is designed with a 40oC hysteresis to lower the av-
erage TJ during continuous thermal overload conditions,
which increases lifetime of the APW8723.
VOFS = VREFOUT ±
IOFFSET ´ ROFFSET
Shutdown and Enable
When this function is inhibited, the ROFFSET should be short
to ensure that VOFS equals VREFOUT
The APW8723 can be shut down or enabled by pulling
low the voltage on COMP. The COMP is a dual-function
pin. During normal operation, this pin represents the out-
put of the error amplifier. It is used to compensate the
regulation control loop in combination with the FB pin.
Pulling the COMP low (VDISABLE = 0.4V maximum) places
.
Copyright ã ANPEC Electronics Corp.
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Rev. A.2 - Apr., 2013
APW8723
Application Information
Output Voltage Selection
lower output ripple voltage. The ripple current and ripple
voltage can be approximated by:
The output voltage can be programmed with a resistive
divider. Use 1% or better resistors for the resistive divider
is recommended. The FB pin is the inverter input of the
error amplifier, and the reference voltage is 0.8V. The
output voltage is determined by:
V
- VOUT VOUT
IN
IRIPPLE
=
´
FSW ´ L
V
IN
where Fs is the switching frequency of the regulator.
DVOUT = IRIPPLE x ESR
æ
ç
è
ö
÷
÷
ø
R1
R2
A tradeoff exists between the inductor’s ripple current and
the regulator load transient response time. A smaller in-
ductor will give the regulator a faster load transient re-
sponse at the expense of higher ripple current and vice
versa. The maximum ripple current occurs at the maxi-
mum input voltage. A good starting point is to choose the
ripple current to be approximately 30% of the maximum
output current.
ç
VOUT = 0.8 ´ 1+
Where R1 is the resistor connected from VOUT to FB and
R2 is the resistor connected from FB to the GND.
Output Capacitor Selection
The selection of COUT is determined by the required effec-
tive series resistance (ESR) and voltage rating rather than
the actual capacitance requirement. Therefore, selecting
high performance low ESR capacitors is intended for
switching regulator applications. In some applications,
multiple capacitors have to be paralleled to achieve the
desired ESR value. If tantalum capacitors are used, make
sure they are surge tested by the manufactures. If in doubt,
consult the capacitors manufacturer.
Once the inductance value has been chosen, selecting
an inductor is capable of carrying the required peak cur-
rent without going into saturation. In some types of
inductors, especially core that is make of ferrite, the ripple
current will increase abruptly when it saturates. This will
result in a larger output ripple voltage.
Compensation
Input Capacitor Selection
The output LC filter of a step down converter introduces a
double pole, which contributes with -40dB/decade gain
slope and 180 degrees phase shift in the control loop. A
compensation network between COMP pin and ground
should be added. The simplest loop compensation net-
work is shown in Figure 5.
The input capacitor is chosen based on the voltage rat-
ing and the RMS current rating. For reliable operation,
select the capacitor voltage rating to be at least 1.3 times
higher than the maximum input voltage. The maximum
RMS current rating requirement is approximately IOUT/2
where IOUT is the load current. During power up, the input
capacitors have to handle large amount of surge current.
If tantalum capacitors are used, make sure they are surge
tested by the manufactures. If in doubt, consult the ca-
pacitors manufacturer.
The output LC filter consists of the output inductor and
output capacitors. The transfer function of the LC filter is
given by:
1+ s´ ESR´ COUT
s2 ´ L´ COUT + s´ ESR´ COUT +1
GAINLC
=
For high frequency decoupling, a ceramic capacitor be-
tween 0.1mF to 1mF can connect between VCC and ground
pin.
The poles and zero of this transfer function are:
1
F
=
LC
2´ p ´ L´ COUT
Inductor Selection
1
FESR
=
2´ p´ ESR´ COUT
The inductance of the inductor is determined by the out-
put voltage requirement. The larger the inductance, the
lower the inductor’s current ripple. This will translate into
The FLC is the double poles of the LC filter, and FESR is
the zero introduced by the ESR of the output capacitor.
Copyright ã ANPEC Electronics Corp.
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Rev. A.2 - Apr., 2013
APW8723
Application Information (Cont.)
Compensation (Cont.)
The compensation circuit is shown in Figure 5. R2 and
C2 introduce a zero and C1 introduces a pole to reduce
the switching noise. The transfer function of error ampli-
fier is given by:
L
Output
PHASE
COUT
ESR
é
ù
ú
ú
û
æ
1
ö
1
ç
÷
GAINAMP = gm´ ZO = gm´ R2 +
//
ê
ç
÷
sC2 sC1
ê
è
ø
ë
æ
ö
1
çs +
÷
÷
ç
R2´ C2
è
ø
= gm´
æ
ö
C2 + C1
R2´ C1´ C2
s´ çs +
÷´ C1
ç
÷
è
ø
Figure 2. The Output LC Filter
The pole and zero of the compensation network are:
1
FLC
FP =
C1´ C2
-40dB/dec
2´ p ´ R2´
C1+ C2
1
FZ =
FESR
2´ p ´ R2´ C2
Gain
VOUT
-20dB/dec
Error
Amplifier
R1
FB
-
COMP
Frequency
R3
Figure 3. The LC Filter Gain & Frequency
+
R2
C2
VREF
The PWM modulator is shown in Figure 4. The input is
the output of the error amplifier and the output is the PHASE
node. The transfer function of the PWM modulator is given
by:
C1
V
IN
Figure 5. Compensation Network
GAINPWM
=
DVOSC
VIN
The closed loop gain of the converter can be written as:
R3
Driver
GAINLC ´ GAINPWM
´
´ GAINAMP
R1+R3
PWM
Comparator
Figure 6 shows the converter gain and the following guide-
lines will help to design the compensation network.
1.Select the desired zero crossover frequency FO:
VOSC
Output of
Error
(1/5 ~ 1/10) x FSW >FO>FZ
PHASE
Amplifier
Use the following equation to calculate R2:
DVOSC
F
ESR R1+R3
F
gm
O
R2 =
´
´
´
LC2
VIN
R3
F
Driver
Where:
gm = 667mA/V
Figure 4. The PWM Modulator
Copyright ã ANPEC Electronics Corp.
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Rev. A.2 - Apr., 2013
APW8723
Application Information (Cont.)
Compensation (Cont.)
where IOUT is the load current
TC is the temperature dependency of RDS(ON)
FSW is the switching frequency
2. Place the zero FZ before the LC filter double poles FLC:
FZ = 0.75 x FLC
tsw is the switching interval
Calculate the C2 by the equation:
D is the duty cycle
1
C2 =
Note that both MOSFETs have conduction losses while
the upper MOSFET includes an additional transition loss.
The switching internal, tsw, is the function of the reverse
transfer capacitance CRSS. Figure 7 illustrates the switch-
ing waveform internal of the MOSFET.
2´ p ´ R2´ 0.75´ FLC
3. Set the pole at the half the switching frequency:
FP = 0.5xFSW
Calculate the C1 by the equation:
The (1+TC) term factors in the temperature dependency
of the RDS(ON) and can be extracted from the “RDS(ON) vs Tem-
perature” curve of the power MOSFET.
C2
C1=
p ´ R2´ C2´ FSW - 1
VDS
FZ=0.75FLC
FP=0.5FSW
20 . log(gm . R2)
Compensation
Gain
Gain
FLC
VIN
FO
20.log
DVOSC
Converter
Gain
FESR
PWM &
Filter Gain
Frequency
tsw
Time
Figure 6. Converter Gain & Frequency
MOSFETSelection
Figure 7. Switching Waveform Across MOSFET
Layout Consideration
The selection of the N-channel power MOSFETs is deter-
mined by the RDS(ON), reverse transfer capacitance (CRSS),
and maximum output current requirement.The losses in
the MOSFETs have two components: conduction loss and
transition loss. For the upper and lower MOSFET, the
losses are approximately given by the following equations:
In any high switching frequency converter, a correct lay-
out is important to ensure proper operation of the
regulator. With power devices switching at 300kHz,the
resulting current transient will cause voltage spike across
the interconnecting impedance and parasitic circuit
elements. As an example, consider the turn-off transition
of the PWM MOSFET. Before turn-off, the MOSFET is car-
rying the full load current. During turn-off, current stops
flowing in the MOSFET and is free-wheeling by the lower
MOSFET and parasitic diode. Any parasitic inductance of
the circuit generates a large voltage spike during the
switching interval. In general, using short and wide printed
circuit traces should minimize interconnecting imped
PUPPER = IOUT2 (1+ TC)(RDS(ON))D + (0.5)(Iout)(VIN)(tsw)FSW
PLOWER = IOUT2 (1+ TC)(RDS(ON))(1-D)
Copyright ã ANPEC Electronics Corp.
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Rev. A.2 - Apr., 2013
APW8723
Application Information (Cont.)
Layout Consideration (Cont.)
APW8723
VIN
ances and the magnitude of voltage spike. And signal
and power grounds are to be kept separate till combined
using ground plane construction or single point
grounding. Figure 8. illustrates the layout, with bold lines
indicating high current paths; these traces must be short
and wide. Components along the bold lines should be
placed lose together. Below is a checklist for your layout:
- Keep the switching nodes (UGATE, LGATE, and PHASE)
away from sensitive small signal nodes since these
nodes are fast moving signals. Therefore, keep traces
to these nodes as short as possible.
VCC
BOOT
L
O
A
D
UGATE
PHASE
ROCSET
LGATE
VOUT
Close to IC
- The traces from the gate drivers to the MOSFETs (UG
and LG) should be short and wide.
Figure 8. Layout Guidelines
- Place the source of the high-side MOSFET and the drain
of the low-side MOSFET as close as possible. Minimiz-
ing the impedance with wide layout plane between the
two pads reduces the voltage bounce of the node.
- Decoupling capacitor, compensation component, the
resistor dividers, and boot capacitors should be close
their pins. (For example, place the decoupling ceramic
capacitor near the drain of the high-side MOSFET as
close as possible. The bulk capacitors are also placed
near the drain).
Recommended Minimum Footprint
ThermalVia diameter
12mil X 5
Ground plane for
ThermalPAD
0.275mm
0.75mm
0.30mm
- The input capacitor should be near the drain of the up-
per MOSFET; the output capacitor should be near the
loads. The input capacitor GND should be close to the
output capacitor GND and the lower MOSFET GND.
- The drain of the MOSFETs (VIN and PHASE nodes) should
be a large plane for heat sinking.
0.50mm
1.75mm
- The ROCSET resistance should be placed near the IC as
close as possible.
TDFN3X3 -10L and Pattern R ecommendation
Copyright ã ANPEC Electronics Corp.
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Rev. A.2 - Apr., 2013
APW8723
Package Information
TDFN3x3-10
A
D
Pin 1
A1
A3
D2
Pin 1
Corner
e
TDFN3x3-10
S
Y
M
B
O
MILLIMETERS
MIN. MAX.
0.70
INCHES
MIN.
MAX.
0.031
0.002
L
A
0.80
0.05
0.028
0.000
A1
A3
b
0.00
0.20 REF
0.008 REF
0.007
0.114
0.087
0.114
0.055
0.012
0.122
0.106
0.122
0.069
0.18
2.90
2.20
2.90
1.40
0.30
3.10
2.70
3.10
1.75
D
D2
E
E2
e
0.50 BSC
0.020 BSC
0.012
0.008
0.020
L
0.30
0.20
0.50
K
Note : 1. Followed from JEDEC MO-229 VEED-5.
Copyright ã ANPEC Electronics Corp.
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Rev. A.2 - Apr., 2013
APW8723
Carrier Tape & Reel Dimensions
P0
P2
P1
OD0
A
K0
A0
A
OD1
B
B
SECTION A-A
SECTION B-B
d
T1
Application
TDFN3x3-10
A
H
T1
12.4+2.00 13.0+0.50
-0.00 -0.20
P2 D0
C
d
D
W
E1
F
3.5±0.05
K0
330.0±2.00 50 MIN.
1.5 MIN.
D1
20.2 MIN. 12.0±0.30 1.75±0.10
P0
P1
T
A0
B0
1.5+0.10
-0.00
0.6+0.00
-0.40
4.0±0.10
8.0±0.10
2.0±0.05
1.5 MIN.
3.30±0.20 3.30±0.20 1.30±0.20
(mm)
Devices Per Unit
Package Type
TDFN3x3-10
Unit
Quantity
3000
Tape & Reel
Copyright ã ANPEC Electronics Corp.
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Rev. A.2 - Apr., 2013
APW8723
Taping Direction Information
TDFN3x3-10
USER DIRECTION OF FEED
Classification Profile
Copyright ã ANPEC Electronics Corp.
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Rev. A.2 - Apr., 2013
APW8723
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
Preheat & Soak
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
Temperature min (Tsmin
)
Temperature max (Tsmax
)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
3 °C/second max.
3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL)
183 °C
60-150 seconds
217 °C
60-150 seconds
Peak package body Temperature
(Tp)*
See Classification Temp in table 1
20** seconds
See Classification Temp in table 2
30** seconds
Time (tP)** within 5°C of the specified
classification temperature (Tc)
Average ramp-down rate (Tp to Tsmax
)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Volume mm3
350
Package
Thickness
<2.5 mm
³ 2.5 mm
Volume mm3
<350
235 °C
220 °C
220 °C
220 °C
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
Volume mm3
Volume mm3
350-2000
260 °C
Volume mm3
<350
260 °C
260 °C
250 °C
>2000
260 °C
245 °C
245 °C
1.6 mm – 2.5 mm
³ 2.5 mm
250 °C
245 °C
Reliability Test Program
Test item
SOLDERABILITY
HOLT
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
PCT
TCT
HBM
MM
VMM≧200V
10ms, 1tr≧100mA
Latch-Up
Copyright ã ANPEC Electronics Corp.
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Rev. A.2 - Apr., 2013
APW8723
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright ã ANPEC Electronics Corp.
Rev. A.2 - Apr., 2013
23
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