AOZ1024DI [AOS]
EZBuck⑩ 4A Synchronous Buck Regulator; EZBuck ™ 4A同步降压稳压器
| 型号： | AOZ1024DI |
| 厂家： | 
ALPHA & OMEGA SEMICONDUCTORS |
| 描述： | EZBuck⑩ 4A Synchronous Buck Regulator |
| 文件： | 总16页 (文件大小：738K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AOZ1024D
EZBuck™ 4A Synchronous Buck Regulator
General Description
Features
The AOZ1024D is a synchronous high efficiency, simple
to use, 4A buck regulator. The AOZ1024D works from a
4.5V to 16V input voltage range, and provides up to 4A
of continuous output current with an output voltage
adjustable down to 0.8V.
● 4.5V to 16V operating input voltage range
● Synchronous rectification: 100mΩ internal high-side
switch and 20mΩ internal low-side switch
● High efficiency: up to 95%
● Internal soft start
The AOZ1024D comes in a DFN 5x 4 package and is
rated over a -40°C to +85°C ambient temperature range.
● 1.5% initial output accuracy
● Output voltage adjustable to 0.8V
● 4A continuous output current
● Fixed 500kHz PWM operation
● Cycle-by-cycle current limit
● Pre-bias start-up
● Short-circuit protection
● Thermal shutdown
● Small size DFN 5x 4 package
Applications
● Point of load DC/DC conversion
● PCIe graphics cards
● Set top boxes
● DVD drives and HDD
● LCD panels
● Cable modems
● Telecom/networking/datacom equipment
Typical Application
VIN
C1
22µF
Ceramic
VIN
L1 4.7µH
EN
VOUT
LX
AOZ1024D
R1
COMP
C2, C3
22µF
R
C
FB
Ceramic
C
C
R2
AGND
PGND
Figure 1. 3.3V/4A Synchronous Buck Regulator
Rev. 1.1 November 2007
www.aosmd.com
Page 1 of 16
AOZ1024D
Ordering Information
Part Number
Ambient Temperature Range
Package
Environmental
AOZ1024DI
-40°C to +85°C
DFN-8
RoHS
All AOS Products are offering in packaging with Pb-free plating and compliant to RoHS standards.
Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.
Pin Configuration
1
2
3
4
8
7
6
5
PGND
VIN
LX
LX
LX
AGND
FB
EN
GND
COMP
5 x 4 DFN
(Top Thru View)
Pin Description
Pin Number Pin Name
Pin Function
1
2
3
PGND
Power ground. Electrically needs to be connected to AGND.
V
Supply voltage input. When V rises above the UVLO threshold the device starts up.
IN
IN
AGND
Reference connection for controller section. Also used as thermal connection for controller
section. Electrically needs to be connected to PGND.
4
FB
The FB pin is used to determine the output voltage via a resistor divider between the output
and GND.
5
6
COMP
EN
External loop compensation pin.
The enable pin is active high. Connect in to V if not used and do not leave it open.
IN
7, 8
LX
PWM output connection to inductor.
Rev. 1.1 November 2007
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AOZ1024D
Block Diagram
VIN
Internal
+5V
UVLO
& POR
5V LDO
Regulator
OTP
EN
+
ISen
–
Reference
& Bias
Softstart
Q1
ILimit
+
–
+
Level
Shifter
+
FET
Driver
+
–
PWM
Control
Logic
0.8V
PWM
Comp
EAmp
FB
LX
Q2
500kHz/68kHz
Oscillator
COMP
Frequency
Foldback
Comparator
+
–
0.2V
AGND
PGND
Absolute Maximum Ratings
Recommend Operating Ratings
Exceeding the Absolute Maximum ratings may damage the
device.
The device is not guaranteed to operate beyond the Maximum
Operating Ratings.
Parameter
Rating
Parameter
Rating
Supply Voltage (V )
18V
-0.7V to V +0.3V
Supply Voltage (V )
4.5V to 16V
IN
IN
LX to AGND
Output Voltage Range
0.8V to V
IN
IN
EN to AGND
-0.3V to V +0.3V
Ambient Temperature (T )
-40°C to +85°C
50°C/W
IN
A
FB to AGND
-0.3V to 6V
-0.3V to 6V
-0.3V to +0.3V
-0.3V to 6V
+150°C
Package Thermal Resistance DFN-8
)
(2
(Θ
)
JA
COMP to AGND
PGND to AGND
PGOOD to AGND
Note:
2
2.The value of ΘJA is measured with the device mounted on 1-in FR-4
board with 2oz. Copper, in a still air environment with T = 25°C. The
value in any given application depends on the user's specific board
design.
A
Junction Temperature (T )
J
Storage Temperature (T )
-65°C to +150°C
2.0kV
S
(1)
ESD Rating
Note:
1. Devices are inherently ESD sensitive, handling precautions are
required. Human body model rating: 1.5kΩ in series with 100pF.
Rev. 1.1 November 2007
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Page 3 of 16
AOZ1024D
Electrical Characteristics
)
(3
T = 25°C, V = V = 12V, V = 3.3V unless otherwise specified
OUT
A
IN
EN
Symbol
Parameter
Conditions
Min.
4.5
Typ. Max. Units
V
Supply Voltage
16
V
IN
V
Input Under-Voltage Lockout Threshold
V
V
Rising
Falling
4.1
3.7
UVLO
IN
IN
V
I
Supply Current (Quiescent)
Shutdown Supply Current
Feedback Voltage
I
= 0, VFB = 1.2V, V > 1.2V
1.6
3
2.5
20
mA
uA
V
IN
OUT
EN
I
V
= 0V
OFF
EN
V
0.788
0.8
0.5
1
0.812
FB
Load Regulation
%
Line Regulation
%
I
Feedback Voltage Input Current
EN Input Threshold
200
nA
FB
V
Off Threshold
On Threshold
0.6
EN
V
2
V
EN Input Hysteresis
100
mV
HYS
MODULATOR
f
Frequency
350
100
500
600
6
kHz
%
O
D
Maximum Duty Cycle
Minimum Duty Cycle
Error Amplifier Voltage Gain
Error Amplifier Transconductance
MAX
D
%
MIN
500
200
V/ V
µA/V
PROTECTION
I
Current Limit
5.0
3
6.0
A
LIM
Over-Temperature Shutdown Limit
T Rising
150
100
J
°C
ms
T Falling
J
t
Soft Start Interval
5
7
SS
OUTPUT STAGE
High-Side Switch On-Resistance
V
V
= 12V
= 5V
97
166
130
200
IN
IN
mΩ
mΩ
Low-Side Switch On-Resistance
V
V
= 12V
= 5V
18
30
23
36
IN
IN
Note:
3. Specification in BOLD indicate an ambient temperature range of -40°C to +85°C. These specifications are guaranteed by design.
Rev. 1.1 November 2007
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Page 4 of 16
AOZ1024D
Typical Performance Characteristics
Circuit of Figure 1. T = 25°C, V = V = 12V, V = 3.3V unless otherwise specified.
OUT
A
IN
EN
Light Load Operation
Full Load (CCM) Operation
Vin ripple
0.1V/div
Vin ripple
0.1V/div
Vo ripple
20mV/div
Vo ripple
20mV/div
IL
1A/div
IL
1A/div
VLX
10V/div
VLX
10V/div
1µs/div
1µs/div
Startup to Full Load
Short Circuit Protection
LX
10V/div
VIN
10V/div
Vo
2V/div
Vo
2V/div
lL
5A/div
lin
1A/div
1ms/div
100µs/div
50% to 100% Load Transient
Short Circuit Recovery
Vo
2V/div
Vo Ripple
200mV/div
IL
lo
5A/div
2A/div
100µs/div
2ms/div
Rev. 1.1 November 2007
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Page 5 of 16
AOZ1024D
Efficiency
AOZ1024D Efficiency
Efficiency (V = 12V) vs. Load Current
IN
100
95
90
85
80
75
70
65
5V OUTPUT
3.3V OUTPUT
1.8V OUTPUT
1.2V OUTPUT
0
0.5
1
1.5
2
2.5
3
3.5
4
Load Current (A)
Thermal Derating Curves
For DFN package part under typical line and output voltage condition. Circuit of Figure 1. 25°C ambient temperature
and natural convection (air speed<50LFM) unless otherwise specified.
Derating Curve at 5V/6V Input
Derating Curve at 12V Input
5
4
3
2
1
0
4.4
4.2
4.0
3.8
3.6
3.4
1.2V OUTPUT
1.8V
1.2V, 1.8V OUTPUT
3.3V
3.3V
OUTPUT
5V
OUTPUT
25
35
45
55
65
75
85
25
35
45
55
65
75
85
Ambient Temperature (TA)
Ambient Temperature (TA)
Rev. 1.1 November 2007
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Page 6 of 16
AOZ1024D
Detailed Description
The AOZ1024D is a current-mode step down regulator
with integrated high-side PMOS switch and a low-side
NMOS switch. It operates from a 4.5V to 16V input volt-
age range and supplies up to 4A of load current.The duty
cycle can be adjusted from 6% to 100% allowing a wide
range of output voltage. Features include enable control,
Power-On Reset, input under voltage lockout, output over
voltage protection, active high power good state, fixed
internal soft-start, and thermal shut down.
switch to output.The internal adaptive FET driver guaran-
tees no turn on overlap of both high-side and low-side
switch.
Compared with regulators using freewheeling Schottky
diodes, the AOZ1024D uses freewheeling NMOSFET to
realize synchronous rectification. It greatly improves the
converter efficiency and reduces power loss in the
low-side switch.
The AOZ1024D uses a P-Channel MOSFET as the
high-side switch. It saves the bootstrap capacitor
normally seen in a circuit which is using an NMOS
switch. It allows 100% turn-on of the high-side switch to
achieve linear regulation mode of operation. The mini-
The AOZ1024D is available in a DFN 5x4 package.
Enable and Soft Start
The AOZ1024D has internal soft start feature to limit
in-rush current and ensure the output voltage ramps up
smoothly to regulation voltage. A soft start process
begins when the input voltage rises to 4.1V and voltage
on the EN pin is HIGH. In the soft start process, the
output voltage is typically ramped to regulation voltage in
5ms. The 4ms soft start time is set internally.
mum voltage drop from V to V is the load current x
IN
O
DC resistance of MOSFET + DC resistance of buck
inductor. It can be calculated by equation below:
V
= V – I × R
IN O DSON
O_MAX
where;
The EN pin of the AOZ1024D is active HIGH. Connect
V
V
is the maximum output voltage,
O_MAX
the EN pin to V if enable function is not used. Pulling
IN
is the input voltage from 4.5V to 16V,
IN
EN to ground will disable the AOZ1024D. Do not leave it
open.The voltage on EN pin must be above 2V to enable
the AOZ1024D. When voltage on the EN pin falls below
0.6V, the AOZ1024D is disabled. If an application circuit
requires the AOZ1024D to be disabled, an open drain or
open collector circuit should be used to interface to the
EN pin.
I
is the output current from 0A to 4A, and
O
R
is the on resistance of internal MOSFET, the value is
DS(ON)
between 97mΩ and 200mΩ depending on input voltage and
junction temperature.
Switching Frequency
The AOZ1024D switching frequency is fixed and set by
an internal oscillator. The practical switching frequency
could range from 350kHz to 600kHz due to device
variation.
Steady-State Operation
Under steady-state conditions, the converter operates in
fixed frequency and Continuous-Conduction Mode (CCM)
.
The AOZ1024D integrates an internal P-MOSFET as the
high-side switch. Inductor current is sensed by amplifying
the voltage drop across the drain to source of the high
side power MOSFET. Output voltage is divided down by
the external voltage divider at the FB pin. The difference
of the FB pin voltage and reference is amplified by the
internal transconductance error amplifier. The error volt-
age, which shows on the COMP pin, is compared against
the current signal, which is sum of inductor current signal
and ramp compensation signal, at PWM comparator
input. If the current signal is less than the error voltage,
the internal high-side switch is on. The inductor current
flows from the input through the inductor to the output.
When the current signal exceeds the error voltage,
the high-side switch is off. The inductor current is
Output Voltage Programming
Output voltage can be set by feeding back the output
to the FB pin by using a resistor divider network (see
Figure 1). The resistor divider network includes R and
1
R . Usually, a design is started by picking a fixed R
2
2
value and calculating the required R with equation
1
below:
R
1
V
= 0.8 × 1 +
------
O
R
2
Some standard values of R and R for the most
1
2
commonly used output voltage values are listed in
Table 1.
freewheeling through the internal low-side N-MOSFET
Rev. 1.1 November 2007
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AOZ1024D
Table 1.
V (V)
Thermal Protection
An internal temperature sensor monitors the junction
temperature. It shuts down the internal control circuit and
high side PMOS if the junction temperature exceeds
150°C. The regulator will restart automatically under the
control of soft-start circuit when the junction temperature
decreases to 100ºC.
R (kΩ)
R (kΩ)
O
1
2
0.8
1.0
4.99
10
Open
10
1.2
1.5
1.8
2.5
3.3
5.0
11.5
10.2
10
12.7
21.5
31.6
52.3
Application Information
The basic AOZ1024 application circuit is show in
Figure 1. Component selection is explained below.
10
10
Input capacitor
The combination of R and R should be large enough to
1
2
avoid drawing excessive current from the output, which
The input capacitor must be connected to the V pin and
IN
will cause power loss.
PGND pin of AOZ1024D to maintain steady input voltage
and filter out the pulsing input current. The voltage rating
of input capacitor must be greater than maximum input
voltage plus ripple voltage.
Since the switch duty cycle can be as high as 100%, the
maximum output voltage can be set as high as the input
voltage minus the voltage drop on upper PMOS and
inductor.
The input ripple voltage can be approximated by equation
below:
Protection Features
The AOZ1024D has multiple protection features to pre-
vent system circuit damage under abnormal conditions.
I
V
V
O
O
O
∆V
=
× 1 –
×
------------------
----------
----------
IN
f × C
V
V
IN
IN
IN
Since the input current is discontinuous in a buck
converter, the current stress on the input capacitor is
another concern when selecting the capacitor. For a buck
circuit, the RMS value of input capacitor current can be
calculated by:
Over Current Protection (OCP)
The sensed inductor current signal is also used for over
current protection. Since the AOZ1024D employs peak
current mode control, the COMP pin voltage is propor-
tional to the peak inductor current.The COMP pin voltage
is limited to be between 0.4V and 2.5V internally. The
peak inductor current is automatically limited cycle by
cycle.
V
V
O
O
I
= I
×
O
1 –
----------
IN
----------
CIN_RMS
V
V
IN
When the output is shorted to ground under fault
conditions, the inductor current decays very slowly during
if we let m equal the conversion ratio:
V
a switching cycle because of V = 0V. To prevent cata-
O
O
= m
----------
strophic failure, a secondary current limit is designed
inside the AOZ1024D. The measured inductor current is
compared against a preset voltage which represents the
current limit, between 5.0A and 6.0A. When the output
current is more than current limit, the high side switch will
be turned off. The converter will initiate a soft start once
the over-current condition is resolved.
V
IN
The relation between the input capacitor RMS current
and voltage conversion ratio is calculated and shown in
Figure 2 on the next page. It can be seen that when V is
O
half of V , C is under the worst current stress. The
IN
IN
worst current stress on C is 0.5 x I .
IN
O
Power-On Reset (POR)
A power-on reset circuit monitors the input voltage.
When the input voltage exceeds 4.1V, the converter
starts operation. When input voltage falls below 3.7V,
the converter will be shut down.
Rev. 1.1 November 2007
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Page 8 of 16
AOZ1024D
The inductor takes the highest current in a buck circuit.
The conduction loss on inductor need to be checked for
thermal and efficiency requirements.
0.5
0.4
0.3
0.2
0.1
0
Surface mount inductors in different shape and styles are
available from Coilcraft, Elytone and Murata. Shielded
inductors are small and radiate less EMI noise, but they
cost more than unshielded inductors. The choice
depends on EMI requirement, price, and size.
ICIN_RMS(m)
IO
Output Capacitor
The output capacitor is selected based on the DC output
voltage rating, output ripple voltage specification and
ripple current rating.
0
0.5
1
m
Figure 2. I
vs. Voltage Conversion Ratio
CIN
The selected output capacitor must have a higher rated
voltage specification than the maximum desired output
voltage including ripple. De-rating needs to be consid-
ered for long term reliability.
For reliable operation and best performance, the input
capacitors must have current rating higher than I
CIN_RMS
at worst operating conditions. Ceramic capacitors are
preferred for input capacitors because of their low ESR
and high current rating. Depending on the application
circuits, other low ESR tantalum capacitor may also be
used. When selecting ceramic capacitors, X5R or X7R
type dielectric ceramic capacitors should be used for
their better temperature and voltage characteristics. Note
that the ripple current rating from capacitor manufactures
are based on certain amount of life time. Further
de-rating may be necessary in practical design.
Output ripple voltage specification is another important
factor for selecting the output capacitor. In a buck
converter circuit, output ripple voltage is determined by
inductor value, switching frequency, output capacitor
value and ESR. It can be calculated by the equation
below:
1
∆V = ∆I × ESR
+
--------------------------
O
L
CO
8 × f × C
O
Inductor
where,
The inductor is used to supply constant current to output
when it is driven by a switching voltage. For given input
and output voltage, inductance and switching frequency
together decide the inductor ripple current, which is:
C
is output capacitor value, and
O
ESR is the equivalent series resistance of the output
CO
capacitor.
V
V
O
O
When a low ESR ceramic capacitor is used as the output
capacitor, the impedance of the capacitor at the switching
frequency dominates. Output ripple is mainly caused by
capacitor value and inductor ripple current. The output
ripple voltage calculation can be simplified to:
∆I
=
× 1 –
-----------
f × L
----------
L
V
IN
The peak inductor current is:
∆I
L
1
I
= I
+
O
--------
∆V = ∆I ×
--------------------------
Lpeak
O
L
2
8 × f × C
O
High inductance gives low inductor ripple current but
requires a larger size inductor to avoid saturation. Low
ripple current reduces inductor core losses. It also
reduces RMS current through inductor and switches,
which results in less conduction loss. Usually, peak to
peak ripple current on inductor is designed to be 20–30%
of output current.
If the impedance of ESR at switching frequency
dominates, the output ripple voltage is mainly decided
by capacitor ESR and inductor ripple current. The output
ripple voltage calculation can be further simplified to:
∆V = ∆I × ESR
CO
O
L
For lower output ripple voltage across the entire operat-
ing temperature range, X5R or X7R dielectric type of
ceramic, or other low ESR tantalum capacitors are
recommended to be used as output capacitors.
When selecting the inductor, make sure it is able to
handle the peak current without saturation even at the
highest operating temperature.
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Page 9 of 16
AOZ1024D
where;
is the error amplifier transconductance, which is 200 x 10
A/V,
In a buck converter, output capacitor current is continu-
ous. The RMS current of output capacitor is decided by
the peak to peak inductor ripple current. It can be
calculated by:
-6
G
EA
G
is the error amplifier voltage gain, which is 500 V/V, and
VEA
∆I
L
C is compensation capacitor in Figure 1.
c
I
=
----------
CO_RMS
12
The zero given by the external compensation network,
capacitor C and resistor R , is located at:
c
c
Usually, the ripple current rating of the output capacitor is
a smaller issue because of the low current stress. When
the buck inductor is selected to be very small and induc-
tor ripple current is high, output capacitor could be over-
stressed.
1
f
=
------------------------------------
2π × C × R
Z 2
C
C
To design the compensation circuit, a target crossover
frequency f for close loop must be selected.The system
C
Loop Compensation
crossover frequency is where control loop has unity gain.
The crossover is the also called the converter bandwidth.
Generally a higher bandwidth means faster response to
load transient. However, the bandwidth should not be too
high because of system stability concern. When design-
ing the compensation loop, converter stability under all
line and load condition must be considered.
The AOZ1024D employs peak current mode control for
easy use and fast transient response. Peak current mode
control eliminates the double pole effect of the output
L&C filter. It greatly simplifies the compensation loop
design.
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is dominant pole can be
calculated by:
Usually, it is recommended to set the bandwidth to be
equal or less than 1/10 of switching frequency. The
AOZ1024D operates at a frequency range from 350kHz
to 600kHz. It is recommended to choose a crossover
frequency equal or less than 40kHz.
1
f
=
-----------------------------------
P1
2π ×
×
R
C
O
L
f
= 40kHz
C
The zero is a ESR zero due to output capacitor and its
ESR. It is can be calculated by:
The strategy for choosing R and CC is to set the cross
C
over frequency with R and set the compensator zero
C
1
with C . Using selected crossover frequency, f , to
f
=
-------------------------------------------------
C
C
Z 1
2π × C × ESR
calculate R :
c
O
CO
where;
is the output filter capacitor,
V
2π × C
O
c
R
= f
×
C
×
----------- -----------------------------
C
C
O
V
G
EA
× G
FB
CS
R is load resistor value, and
L
where;
ESR is the equivalent series resistance of output capacitor.
CO
f is the desired crossover frequency. For best performance, f
C
C
is set to be about 1/10 of the switching frequency;
The compensation design is actually to shape the
converter control loop transfer function to get desired
gain and phase. Several different types of compensation
network can be used for the AOZ1024D. For most cases,
a series capacitor and resistor network connected to the
COMP pin sets the pole-zero and is adequate for a stable
high-bandwidth control loop.
V
is 0.8V,
FB
-6
G
is the error amplifier transconductance, which is 200 x 10
EA
A/V, and
G
is the current sense circuit transconductance, which is
CS
6.68 A/V.
The compensation capacitor C and resistor R together
C
C
In the AOZ1024D, FB pin and COMP pin are the inverting
input and the output of internal error amplifier. A series
R and C compensation network connected to COMP
provides one pole and one zero. The pole is:
make a zero. This zero is put somewhere close to the
dominate pole f but lower than 1/5 of selected cross-
p1
over frequency. C can is selected by:
2
1.5
G
C
=
-------------------------------------
EA
C
f
=
------------------------------------------
2π × R × f
P2
C
P1
2π× C × G
c
VEA
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Page 10 of 16
AOZ1024D
The previous equation can also be simplified to:
The maximum junction temperature of AOZ1024D is
150°C, which limits the maximum load current capability.
Please see the thermal de-rating curves for maximum
load current of the AOZ1024D under different ambient
temperature.
C
× R
L
O
C
=
----------------------
C
R
C
An easy-to-use application software which helps to
design and simulate the compensation loop can be found
at www.aosmd.com.
The thermal performance of the AOZ1024D is strongly
affected by the PCB layout. Extra care should be taken
by users during design process to ensure that the IC
will operate under the recommended environmental
conditions.
Thermal Management and Layout
Consideration
In the AOZ1024D buck regulator circuit, high pulsing
current flows through two circuit loops. The first loop
The AOZ1024D is standard DFN5*4 package. Several
layout tips are listed below for the best electric and
thermal performance. Figure 3 on the next page
illustrates a PCB layout example of AOZ1024D.
starts from the input capacitors, to the V pin, to the
IN
LX pins, to the filter inductor, to the output capacitor
and load, and then return to the input capacitor through
ground. Current flows in the first loop when the high side
switch is on. The second loop starts from inductor, to the
output capacitors and load, to the lowside NMOSFET.
Current flows in the second loop when the lowside
NMOSFET is on.
1. The LX pins are connected to internal PFET and
NFET drains. They are low resistance thermal
conduction path and most noisy switching node.
Connected a large copper plane to LX pin to help
thermal dissipation. For full load (4A) application,
also connect the LX pads to the bottom layer by
thermal vias to enhance the thermal dissipation.
In PCB layout, minimizing the two loops area reduces the
noise of this circuit and improves efficiency. A ground
plane is strongly recommended to connect input capaci-
tor, output capacitor, and PGND pin of the AOZ1024D.
2. Do not use thermal relief connection to the V and
IN
the PGND pin. Pour a maximized copper area to
the PGND pin and the VIN pin to help thermal
dissipation.
In the AOZ1024D buck regulator circuit, the major power
dissipating components are the AOZ1024D and the
output inductor. The total power dissipation of converter
circuit can be measured by input power – output power.
3. Input capacitor should be connected to the V pin
IN
and the PGND pin as close as possible.
4. A ground plane is preferred. If a ground plane is
not used, separate PGND from AGND and connect
them only at one point to avoid the PGND pin noise
coupling to the AGND pin.
P
= V × I – V × I
IN IN O O
total
The power dissipation of the inductor can be
approximately calculated by output current and DCR
of inductor.
5. Make the current trace from LX pins to L to C to the
O
PGND as short as possible.
6. Pour copper plane on all unused board area and
2
P
= I × R
× 1.1
inductor
connect it to stable DC nodes, like V , GND or V
.
inductor
O
IN
OUT
7. Keep sensitive signal trace far away form the LX pins.
The actual junction temperature can be calculated with
power dissipation in the AOZ1024D and thermal
impedance from junction to ambient.
T
= (P
–P
) × Θ
inductor _loss JA
junction
total
Rev. 1.1 November 2007
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Page 11 of 16
AOZ1024D
Bottom Layer
Thermal Dissipation
Thermal Vias
Figure 3. AOZ1024D (DFN 5x4) PCB Layout
Rev. 1.1 November 2007
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Page 12 of 16
AOZ1024D
Package Dimensions, DFN 5x4
D
A
Pin #1 IDA
L
e
D/2
B
1
E/2
R
E
E3
E2
Index Area
(D/2 x E/2)
D2
D3
L1
aaa C
ccc C
A
A3
C
Seating
Plane
ddd C
A1
b
C A B
bbb
Dimensions in millimeters
Dimensions in inches
Symbols Min.
Nom. Max.
Symbols Min.
Nom. Max.
A
A1
A3
b
0.80
0.00
0.90
0.02
1.00
0.05
A
A1
A3
b
0.031 0.035 0.039
0.000 0.001 0.002
0.008 REF
Recommended Land Pattern
0.20 REF
0.40
2.125
1.775
0.35
0.45
0.014 0.016 0.018
0.197 BSC
0.6
D
5.00 BSC
D
D2
D3
E
1.975 2.125 2.225
1.625 1.775 1.875
4.00 BSC
D2
D3
E
0.078 0.084 0.088
0.064 0.070 0.074
0.157 BSC
2.7
2.2
E2
E3
e
2.500 2.650 2.750
2.050 2.200 2.300
0.95 BSC
E2
E3
e
0.098 0.104 0.108
0.081 0.087 0.091
0.037 BSC
0.8
0.5
0.95
L
0.600 0.700 0.800
0.400 0.500 0.600
0.30 REF
L
0.024 0.028 0.031
0.016 0.020 0.024
0.012 REF
Unit: mm
L1
R
L1
R
aaa
bbb
ccc
ddd
–
–
–
–
0.15
0.10
0.10
0.08
–
–
–
–
aaa
bbb
ccc
ddd
–
–
–
–
0.006
0.004
0.004
0.003
–
–
–
–
Notes:
1. Dimensions and tolerancing conform to ASME Y14.5M-1994.
2. All dimensions are in millimeters.
3. The location of the terminal #1 identifier and terminal numbering convention conforms to JEDEC publication 95 SP-002.
4. Dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. If the terminal has the
optional radius on the other end of the terminal, the dimension b should not be measured in that radius area.
5. Coplanarity applies to the terminals and all other bottom surface metallization.
6. Drawing shown are for illustration only.
Rev. 1.1 November 2007
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Page 13 of 16
AOZ1024D
Tape Dimensions, DFN 5x4
Tape
T
D1
E1
E2
D0
E
B0
Feeding
Direction
K0
P0
A0
Unit: mm
Package
A0
B0
K0
D0
D1
1.50
E
E1
E2
P0
P1
4.00
P2
T
1.50
Min.
Typ.
DFN 5x4
(12 mm)
5.30
±0.10
4.30
±0.10
1.20
±0.10
12.00
±0.30
1.75
±0.10
5.50
±0.10
8.00
2.00
0.30
±0.05
+0.10 / –0
±0.10 ±0.20 ±0.10
Leader/Trailer and Orientation
Trailer Tape
(300mm Min.)
Components Tape
Orientation in Pocket
Leader Tape
(500mm Min.)
Rev. 1.1 November 2007
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Page 14 of 16
AOZ1024D
Reel Dimensions, DFN 5x4
II
I
6.0±1
M
I
Zoom In
R1
P
B
W1
III
Zoom In
3-1.8
0.05
II
Zoom In
A
N=ø100±2
A A
1.8
6.0
6.45±0.05
6.2
0.00
-0.05
8.00
R1
2.20
2.00
8.9±0.1
14 REF
5.0
C
1.8
12 REF
11.90
46.0±0.1
44.5±0.1
41.5 REF
43.00
44.5±0.1
3.3
4.0
6.50
6.10
40°
10.0
VIEW: C
2.5
1.80
0.80
3.00
A
8.0±0.1
+0.05
0.00
2.00
6.50
8.00
10.71
6°
Rev. 1.1 November 2007
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Page 15 of 16
AOZ1024D
AOZ1024D Package Marking
Z1024DI
FAYWLT
Part Number Code
Assembly Lot Code
Fab & Assembly Location
Year & Week Code
This data sheet contains preliminary data; supplementary data may be published at a later date.
Alpha & Omega Semiconductor reserves the right to make changes at any time without notice.
LIFE SUPPORT POLICY
ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
Rev. 1.1 November 2007
www.aosmd.com
Page 16 of 16
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