AOZ1210 [AOS]
EZBuck⑩ 2A Simple Buck Regulator; EZBuck ™ 2A简单的降压稳压器
| 型号： | AOZ1210 |
| 厂家： | 
ALPHA & OMEGA SEMICONDUCTORS |
| 描述： | EZBuck⑩ 2A Simple Buck Regulator |
| 文件： | 总14页 (文件大小：576K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AOZ1210
EZBuck™ 2A Simple Buck Regulator
General Description
Features
The AOZ1210 is a high efficiency, simple to use, 2A buck
regulator flexible enough to be optimized for a variety of
applications. The AOZ1210 works from a 4.5V to 27V
input voltage range, and provides up to 2A of continuous
output current on each buck regulator output. The output
voltage is adjustable down to 0.8V.
● 4.5V to 27V operating input voltage range
● 70mΩ internal NFET, efficiency: up to 95%
● Internal soft start
● Output voltage adjustable down to 0.8V
● 2A continuous output current
● Fixed 370kHz PWM operation
● Cycle-by-cycle current limit
● Short-circuit protection
● Thermal shutdown
● Small size SO-8 packages
Applications
● Point of load DC/DC conversion
● Set top boxes
● DVD drives and HDD
● LCD Monitors & TVs
● Cable modems
● Telecom/Networking/Datacom equipment
Typical Application
C7
VIN
C1
22µF
VIN
EN
BS
L1
6.8µH
VOUT
LX
FB
AOZ1210
R1
R2
C4, C6
22µF
VBIAS
C4
GND
COMP
RC
CC
Figure 1. 3.3V/2A Buck Regulator
Rev. 1.3 December 2007
www.aosmd.com
Page 1 of 14
AOZ1210
Ordering Information
Part Number
Ambient Temperature Range
Package
Environmental
AOZ1210AI
-40°C to +85°C
SO-8
RoHS
All AOS Products are offering in packaging with Pb-free plating and compliant to RoHS standards.
Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.
Pin Configuration
1
2
3
4
8
7
6
5
LX
BST
GND
FB
VBIAS
VIN
EN
COMP
SO-8
(Top View)
Pin Description
Pin Number Pin Name
Pin Function
1
LX
PWM output connection to inductor. LX pin needs to be connected externally. Thermal connection
for output stage.
2
BST
Bootstrap voltage input. High side driver supply. Connected to 0.1µF capacitor between BST and
LX.
3
4
GND
FB
Ground.
Feedback input. It is regulated to 0.8V. The FB pin is used to determine the PWM output voltage
via a resistor divider between the output and GND.
5
6
7
8
COMP
EN
External loop compensation. Output of internal error amplifier. Connect a series RC network to
GND for control loop compensation.
Enable pin. The enable pin is active HIGH. Connect EN pin to V if not used. Do not leave the EN
IN
pin floating.
V
Supply voltage input. Range from 4.5V to 27V. When V rises above the UVLO threshold the
IN
IN
device starts up. All V pins need to be connected externally.
IN
VBIAS
Compensation pin of internal linear regulator. Place put a 1µF capacitor between this pin and
ground.
Rev. 1.3 December 2007
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Page 2 of 14
AOZ1210
Block Diagram
VIN
+5V
VBIAS
EN
UVLO
& POR
5V LDO
Regulator
OTP
+
ISen
–
Reference
& Bias
Softstart
BST
LX
ILimit
Q1
+
–
+
GM = 200µA/V
EAmp
+
–
PWM
Control
Logic
0.8V
PWM
Comp
FB
COMP
Q2
370kHz/24kHz
Oscillator
Frequency
Foldback
Comparator
+
–
0.2V
GND
Absolute Maximum Ratings
Exceeding the Absolute Maximum Ratings may damage the device.
Recommend Operating Ratings
The device is not guaranteed to operate beyond the Maximum
Operating Ratings.
Parameter
Rating
Parameter
Rating
Supply Voltage (V )
30V
-0.7V to V +0.3V
IN
Supply Voltage (V )
4.5V to 27V
LX to GND
IN
IN
EN to GND
-0.3V to V +0.3V
Output Voltage Range
0.8V to V
IN
IN
FB to GND
-0.3V to 6V
-0.3V to 6V
Ambient Temperature (T )
-40°C to +85°C
105°C/W
A
COMP to GND
BST to GND
VBIAS to GND
Package Thermal Resistance SO-8
)
(2
(Θ
)
V
+6V
JA
LX
-0.3V to 6V
+150°C
Note:
2. The value of ΘJA is measured with the device mounted on 1-in
2
Junction Temperature (T )
J
FR-4 board with 2oz. Copper, in a still air environment with T = 25°C.
The value in any given application depends on the user's specific
board design.
A
Storage Temperature (T )
-65°C to +150°C
2kV
S
(1)
ESD Rating: Human Body Model
Note:
1. Devices are inherently ESD sensitive, handling precautions are
required. Human body model rating: 1.5kΩ in series with 100pF.
Rev. 1.3 December 2007
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Page 3 of 14
AOZ1210
Electrical Characteristics
)
(3
T = 25°C, V = V = 12V, V = 3.3V unless otherwise specified
OUT
A
IN
EN
Symbol
Parameter
Conditions
Min.
4.5
Typ. Max. Units
V
Supply Voltage
27
V
V
IN
V
Input Under-Voltage Lockout Threshold
V
V
Rising
Falling
4.3
4.1
UVLO
IN
IN
I
Supply Current (Quiescent)
Shutdown Supply Current
Feedback Voltage
I
= 0, V = 1.2V, V > 2V
2
3
3
mA
µA
IN
OUT
FB
EN
I
V
= 0V
20
OFF
EN
V
0.782
0.8
0.5
0.08
0.818
V
FB
Load Regulation
%
Line Regulation
% / V
nA
I
Feedback Voltage Input Current
200
FB
ENABLE
V
EN Input Threshold
EN Input Hysteresis
Off Threshold
On Threshold
0.6
EN
V
2.5
V
200
mV
HYS
MODULATOR
f
Frequency
315
85
370
425
6
kHz
%
O
D
Maximum Duty Cycle
Minimum Duty Cycle
Error Amplifier Voltage Gain
Error Amplifier Transconductance
MAX
D
G
%
MIN
VEA
500
200
V / V
µA /V
G
EA
PROTECTION
I
Current Limit
3.5
5.0
A
LIM
Over-Temperature Shutdown Limit
T Rising
145
100
J
°C
T Falling
J
f
Short Circuit Hiccup Frequency
Soft Start Interval
V
= 0V
24
4
kHz
ms
SC
FB
t
SS
PWM OUTPUT STAGE
R
High-Side Switch On-Resistance
High-Side Switch Leakage
70
100
10
mΩ
DS(ON)
V
= 0V, V = 0V
µA
EN
LX
Note:
3. Specification in BOLD indicate an ambient temperature range of -40°C to +85°C. These specifications are guaranteed by design.
Rev. 1.3 December 2007
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Page 4 of 14
AOZ1210
Typical Performance Characteristics
Circuit of Figure 1. T = 25°C, V = V = 24V, V = 3.3V unless otherwise specified.
OUT
A
IN
EN
Light Load (DCM) Operation
Full Load (CCM) Operation
Vin ripple
0.1V/div
Vin ripple
0.1V/div
Vo ripple
20mV/div
Vo ripple
20mV/div
IL
1A/div
IL
1A/div
VLX
20V/div
VLX
20V/div
1µs/div
1µs/div
Startup to Full Load
Short Circuit Protection
Vo
2V/div
Vo
2V/div
lin
0.5A/div
lL
2A/div
2ms/div
200µs/div
50% to 100% Load Transient
Short Circuit Recovery
Vo
2V/div
Vo Ripple
200mV/div
lo
1A/div
IL
2A/div
200µs/div
2ms/div
Rev. 1.3 December 2007
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Page 5 of 14
AOZ1210
Efficiency Curves
Efficiency
Efficiency
IN
V
= 5V
V
= 12V
IN
100
95
90
85
80
75
100
95
90
85
80
75
8.0V OUTPUT
3.3V OUTPUT
1.8V OUTPUT
5.0V OUTPUT
3.3V OUTPUT
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
Current (A)
Current (A)
Efficiency
V
= 24V
IN
100
95
90
85
80
75
8.0V OUTPUT
5.0V OUTPUT
3.3V OUTPUT
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
Current (A)
Rev. 1.3 December 2007
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Page 6 of 14
AOZ1210
Detailed Description
The AOZ1210 is a current-mode step down regulator with
integrated high side NMOS switch. It operates from a
4.5V to 27V input voltage range and supplies up to 2A of
load current. The duty cycle can be adjusted from 6% to
85% allowing a wide range of output voltages. Features
include; enable control, Power-On Reset, input under
voltage lockout, fixed internal soft-start and thermal shut
down.
high-side switch is off. The inductor current is freewheel-
ing through the Schottky diode to the output.
Switching Frequency
The AOZ1210 switching frequency is fixed and set by
an internal oscillator. The switching frequency is set to
370kHz.
The AOZ1210 is available in SO-8 package.
Output Voltage Programming
Output voltage can be set by feeding back the output to
the FB pin with a resistor divider network. In the applica-
tion circuit shown in Figure 1. The resistor divider
Enable and Soft Start
The AOZ1210 has an internal soft start feature to limit
in-rush current and ensure the output voltage ramps up
smoothly to the regulation voltage. A soft start process
begins when the input voltage rises to 4.1V and voltage
on EN pin is HIGH. In the soft start process, the output
voltage is typically ramped to regulation voltage in 4 ms.
The 4.0 ms soft start time is set internally.
network includes R and R . Typically, a design is started
1
2
by picking a fixed R value and calculating the required
2
R value with equation below.
1
R
1
V
= 0.8 × 1 +
------
O
R
2
If the enable function is not used, connect the EN pin to
Some standard values for R and R for the most
commonly used output voltages are listed in Table 1.
V . Pulling EN to ground will disable the AOZ1210. Do
1
2
IN
not leave EN open. The voltage on the EN pin must be
above 2.5 V to enable the AOZ1210. When voltage on
EN pin falls below 0.6V, the AOZ1210 is disabled. If an
application circuit requires the AOZ1210 to be disabled,
an open drain or open collector circuit should be used to
interface with the EN pin.
Table 1.
V (V)
R (kΩ)
R (kΩ)
2
O
1
0.8
1.2
1.5
1.8
2.5
3.3
5.0
1.0
Open
4.99
10
10
11.5
10.2
10
Steady-State Operation
12.7
21.5
31.6
52.3
Under steady-state conditions, the converter operates in
fixed frequency and Continuous-Conduction Mode
(CCM).
10
The AOZ1210 integrates an internal N-MOSFET as the
high-side switch. Inductor current is sensed by amplifying
the voltage drop across the drain to source of the high
side power MOSFET. Since the N-MOSFET requires a
gate voltage higher than the input voltage, a boost
capacitor connected between the LX and BST pins drives
the gate. The boost capacitor is charged while LX is low.
An internal 10Ω switch from LX to GND is used to ensure
that LX is pulled to GND even in the light load. Output
voltage is divided down by the external voltage divider at
the FB pin. The difference of the FB pin voltage and
reference is amplified by the internal transconductance
error amplifier. The error voltage, which shows on the
COMP pin, is compared against the current signal. The
current signal is the sum of inductor current signal and
ramp compensation signal, at the PWM comparator
input. If the current signal is less than the error voltage,
the internal high-side switch is on. The inductor current
flows from the input through the inductor to the output.
When the current signal exceeds the error voltage, the
10
The combination of R and R should be large enough to
avoid drawing excessive current from the output, which
will cause power loss.
1
2
Protection Features
The AOZ1210 has multiple protection features to prevent
system circuit damage under abnormal conditions.
Over Current Protection (OCP)
The sensed inductor current signal is also used for over
current protection. Since the AOZ1210 employs peak
current mode control, the COMP pin voltage is propor-
tional to the peak inductor current.The COMP pin voltage
is limited to be between 0.4V and 2.5V internally. The
peak inductor current is automatically limited cycle by
cycle.
Rev. 1.3 December 2007
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Page 7 of 14
AOZ1210
The cycle-by-cycle current limit threshold is internally set.
When the load current reaches the current limit thresh-
old, the cycle-by-cycle current limit circuit turns off the
high side switch immediately to terminate the current
duty cycle. The inductor current stops rising. The cycle-
by-cycle current limit protection directly limits inductor
peak current.The average inductor current is also limited
due to the limitation on the peak inductor current. When
cycle-by-cycle current limit circuit is triggered, the output
voltage drops as the duty cycle decreases.
Since the input current is discontinuous in a buck
converter, the current stress on the input capacitor is
another concern when selecting the capacitor. For a buck
circuit, the RMS value of input capacitor current can be
calculated by:
V
V
O
O
I
= I
×
O
1 –
----------
----------
CIN_RMS
V
V
IN
IN
if let m equal the conversion ratio:
The AOZ1210 has internal short circuit protection to
protect itself from catastrophic failure under output short
circuit conditions. The FB pin voltage is proportional to
the output voltage. Whenever the FB pin voltage is below
0.2V, the short circuit protection circuit is triggered. To
prevent current limit running away when the comp pin
voltage is higher than 2.1V, the short circuit protection is
also triggered. As a result, the converter is shut down
and hiccups at a frequency equals to 1/16 of normal
switching frequency. The converter will start up via a soft
start once the short circuit condition is resolved. In short
circuit protection mode, the inductor average current is
greatly reduced because of the low hiccup frequency.
V
O
= m
----------
V
IN
The relationship between the input capacitor RMS
current and voltage conversion ratio is calculated and
shown in Figure 2. It can be seen that when V is half of
O
V , C is under the worst current stress. The worst
IN
IN
current stress on CIN is 0.5 x I .
O
0.5
0.4
0.3
ICIN_RMS(m)
Power-On Reset (POR)
IO
A power-on reset circuit monitors the input voltage.
When the input voltage exceeds 4.3V, the converter
starts operation. When input voltage falls below 4.1V,
the converter will stop switching.
0.2
0.1
0
0
0.5
1
Thermal Protection
m
An internal temperature sensor monitors the junction
temperature. It shuts down the internal control circuit and
high side NMOS if the junction temperature exceeds
145°C. The regulator will restart automatically under the
control of soft-start circuit when the junction temperature
decreases to 100°C.
Figure 2. I
vs. Voltage Conversion Ratio
CIN
For reliable operation and best performance, the input
capacitors must have a current rating higher than
I
at the worst operating conditions. Ceramic
CIN_RMS
capacitors are preferred for input capacitors because of
their low ESR and high ripple current rating. Depending
on the application circuits, other low ESR tantalum
capacitor or aluminum electrolytic capacitor may also be
used. When selecting ceramic capacitors, X5R or X7R
type dielectric ceramic capacitors are preferred for their
better temperature and voltage characteristics. Note that
the ripple current rating from capacitor manufactures is
based on certain amount of life time. Further de-rating
may be necessary for practical design requirement.
Application Information
The basic AOZ1210 application circuit is shown in
Figure 1. Component selection is explained below.
Input Capacitor
The input capacitor (C in Figure 1) must be connected to
1
the V pin and GND pin of the AOZ1210 to maintain
IN
steady input voltage and filter out the pulsing input
current. The voltage rating of the input capacitor must be
greater than maximum input voltage + ripple voltage.
Inductor
The inductor is used to supply constant current to output
when it is driven by a switching voltage. For given input
and output voltage, inductance and switching frequency
together decide the inductor ripple current, which is,
The input ripple voltage can be approximated by equation
below:
I
V
V
O
O
O
V
V
O
∆V
=
× 1 –
×
------------------
----------
----------
O
IN
∆I
=
× 1 –
-----------
f × L
----------
V
f × C
V
L
IN
IN
IN
V
IN
Rev. 1.3 December 2007
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Page 8 of 14
AOZ1210
The peak inductor current is:
If the impedance of ESR at switching frequency
∆I
L
dominates, the output ripple voltage is mainly decided by
capacitor ESR and inductor ripple current. The output
ripple voltage calculation can be further simplified to:
I
= I
+
O
--------
Lpeak
2
High inductance gives low inductor ripple current but
requires larger size inductor to avoid saturation. Low
ripple current reduces inductor core losses. It also
reduces RMS current through inductor and switches,
which results in less conduction loss.
∆V = ∆I × ESR
CO
O
L
For lower output ripple voltage across the entire operat-
ing temperature range, X5R or X7R dielectric type of
ceramic, or other low ESR tantalum capacitor or
aluminum electrolytic capacitor may also be used as out-
put capacitors.
When selecting the inductor, make sure it is able to
handle the peak current without saturation even at the
highest operating temperature.
In a buck converter, output capacitor current is continu-
ous. The RMS current of output capacitor is decided by
the peak to peak inductor ripple current. It can be calcu-
lated by:
The inductor takes the highest current in a buck circuit.
The conduction loss on inductor needs to be checked for
thermal and efficiency requirements.
Surface mount inductors in different shape and styles are
available from Coilcraft, Elytone and Murata. Shielded
inductors are small and radiate less EMI noise. But they
cost more than unshielded inductors. The choice
depends on EMI requirement, price and size.
∆I
L
I
=
----------
CO_RMS
12
Usually, the ripple current rating of the output capacitor is
a smaller issue because of the low current stress. When
the buck inductor is selected to be very small and induc-
tor ripple current is high, output capacitor could be over-
stressed.
Output Capacitor
The output capacitor is selected based on the DC output
voltage rating, output ripple voltage specification and
ripple current rating.
Schottky Diode Selection
The selected output capacitor must have a higher rated
voltage specification than the maximum desired output
voltage including ripple. De-rating needs to be consid-
ered for long term reliability.
The external freewheeling diode supplies the current to
the inductor when the high side NMOS switch is off. To
reduce the losses due to the forward voltage drop and
recovery of diode, a Schottky diode is recommended.
The maximum reverse voltage rating of the chosen
Schottky diode should be greater than the maximum
input voltage, and the current rating should be greater
than the maximum load current.
Output ripple voltage specification is another important
factor for selecting the output capacitor. In a buck con-
verter circuit, output ripple voltage is determined by
inductor value, switching frequency, output capacitor
value and ESR. It can be calculated by the equation
below:
Loop Compensation
1
The AOZ1210 employs peak current mode control for
easy use and fast transient response. Peak current mode
control eliminates the double pole effect of the output
L&C filter. It greatly simplifies the compensation loop
design.
∆V = ∆I × ESR
+
--------------------------
O
L
CO
8 × f × C
O
where;
C
is output capacitor value and
O
ESR is the Equivalent Series Resistor of output capacitor.
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is the dominant pole and
can be calculated by:
CO
When low ESR ceramic capacitor is used as output
capacitor, the impedance of the capacitor at the switching
frequency dominates. Output ripple is mainly caused by
capacitor value and inductor ripple current. The output
ripple voltage calculation can be simplified to:
1
f
=
-----------------------------------
p1
2π × C × R
O
L
1
∆V = ∆I ×
--------------------------
O
L
8 × f × C
O
Rev. 1.3 December 2007
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Page 9 of 14
AOZ1210
The zero is a ESR zero due to output capacitor and its
ESR. It is can be calculated by:
The strategy for choosing R and C is to set the cross
C C
over frequency with R and set the compensator zero
C
with C . Using selected crossover frequency, f , to
C
C
1
calculate R :
f
=
-------------------------------------------------
C
Z 1
2π × C × ESR
O
CO
V
2π × C
O
O
R
= f
×
C
×
where;
is the output filter capacitor,
----------- -----------------------------
C
V
G
EA
× G
FB
CS
C
O
where;
f is desired crossover frequency,
R is load resistor value, and
L
C
ESR is the equivalent series resistance of output capacitor.
CO
V
is 0.8V,
FB
The compensation design is actually to shape the
converter close loop transfer function to get desired gain
and phase. Several different types of compensation
network can be used for AOZ1210. For most cases, a
series capacitor and resistor network connected to the
COMP pin sets the pole-zero and is adequate for a stable
high-bandwidth control loop.
-6
G
is the error amplifier transconductance, which is 200x10
EA
A/V, and
G
is the current sense circuit transconductance, which is
CS
5.64 A/V
The compensation capacitor C and resistor R together
make a zero. This zero is put somewhere close to the
dominate pole fp1 but lower than 1/5 of the selected
C
C
In the AOZ1210, FB pin and COMP pin are the inverting
input and the output of internal transconductance error
amplifier. A series R and C compensation network
connected to COMP provides one pole and one zero.
The pole is:
crossover frequency. C can is selected by:
C
1.5
C
=
------------------------------------
C
2π × R × f
C
p1
G
EA
The equation above can also be simplified to:
f
=
-------------------------------------------
p2
2π × C × G
C
VEA
C
× R
L
O
C
=
----------------------
where;
C
R
C
-6
G
is the error amplifier transconductance, which is 200 x 10
EA
A/V,
An easy-to-use application software which helps to
design and simulate the compensation loop can be found
at www.aosmd.com.
G
is the error amplifier voltage
VEA
The zero given by the external compensation network,
capacitor C (C5 in Figure 1) and resistor R (R1 in
Figure 1), is located at:
Thermal Management and Layout
Consideration
C
C
In the AOZ1210 buck regulator circuit, high pulsing
current flows through two circuit loops. The first loop
1
f
=
------------------------------------
Z 2
2π × C × R
C
C
starts from the input capacitors, to the V pin, to the LX
IN
pins, to the filter inductor, to the output capacitor and
load, and then returns to the input capacitor through
ground. Current flows in the first loop when the high side
switch is on. The second loop starts from inductor, to the
output capacitors and load, to the GND pin of the
AOZ1210, to the LX pins of the AZO1210. Current flows
in the second loop when the low side diode is on.
To design the compensation circuit, a target crossover
frequency f for close loop must be selected.The system
C
crossover frequency is where the control loop has unity
gain. The crossover frequency is also called the
converter bandwidth. Generally a higher bandwidth
means faster response to load transient. However, the
bandwidth should not be too high due to system stability
concern. When designing the compensation loop,
converter stability under all line and load condition must
be considered.
In PCB layout, minimizing the two loops area reduces the
noise of this circuit and improves efficiency. A ground
plane is recommended to connect input capacitor, output
capacitor, and GND pin of the AOZ1210.
Usually, it is recommended to set the bandwidth to be
less than 1/10 of switching frequency. It is recommended
to choose a crossover frequency less than 30kHz.
In the AOZ1210 buck regulator circuit, the three major
power dissipating components are the AOZ1210,
external diode and output inductor. The total power
f
= 30kHz
C
Rev. 1.3 December 2007
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Page 10 of 14
AOZ1210
dissipation of converter circuit can be measured by input
power minus output power.
The thermal performance of the AOZ1210 is strongly
affected by the PCB layout. Care should be taken by
users during design process to ensure that the IC will
operate under the recommended environmental
conditions.
P
= V × I – V × I
IN IN O O
total_loss
The power dissipation of inductor can be approximately
calculated by output current and DCR of the inductor.
Several layout tips are listed below for the best electric
and thermal performance. Figure 3 is a layout example.
2
P
= I × R
× 1.1
inductor
inductor _loss
O
1. Do not use thermal relief connection to the V and
IN
the GND pin. Pour a maximized copper area to the
The power dissipation of the diode is:
GND pin and the V pin to help thermal dissipation.
IN
V
O
2. Input capacitor should be connected as close as
P
= I × V × 1 –
----------
diode_loss
O
F
possible to the V and GND pins.
V
IN
IN
3. Make the current trace from LX pins to L to C to
O
GND as short as possible.
The actual AOZ1210 junction temperature can be
calculated with power dissipation in the AOZ1210 and
thermal impedance from junction to ambient.
4. Pour copper plane on all unused board area and
connect it to stable DC nodes, like V , GND or V
.
IN
OUT
T
= (P
–P
) × Θ
inductor _loss
5. Keep sensitive signal traces such as the trace
connecting FB and COMP pins away from the
LX pins.
junction
total_loss
JA
+ T
ambient
The maximum junction temperature of AOZ1210 is
145°C, which limits the maximum load current capability.
Rc
Cc
5 COMP
6 EN
4 FB
AOZ1210 /2
3 GND
7 Vin
2 BST
8 VBIAS
1 LX
L1
Vo
C
C2
2
Figure 3. Layout Example of the AOZ1210
Rev. 1.3 December 2007
www.aosmd.com
Page 11 of 14
AOZ1210
Package Dimensions
D
e
Gauge Plane
Seating Plane
0.25
8
L
E
E1
h x 45°
1
C
θ
7° (4x)
A2
A
0.1
A1
b
Dimensions in millimeters
Dimensions in inches
Symbols Min. Nom. Max.
Symbols Min.
Nom. Max.
0.053 0.065 0.069
0.004 0.010
0.049 0.059 0.065
2.20
A
A1
A2
b
1.35
0.10
1.25
0.31
0.17
4.80
3.80
1.65
—
1.75
0.25
1.65
0.51
0.25
5.00
4.00
A
A1
A2
b
—
1.50
—
0.012
0.007
—
—
0.020
0.010
c
—
c
5.74
D
E1
e
4.90
3.90
1.27 BSC
6.00
—
D
E1
e
0.189 0.193 0.197
0.150 0.154 0.157
0.050 BSC
1.27
E
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
E
0.228 0.236 0.244
h
h
0.010
0.016
0°
—
—
—
0.020
0.050
8°
L
—
L
0.80
θ
—
θ
Unit: mm
Notes:
1. All dimensions are in millimeters.
2. Dimensions are inclusive of plating
3. Package body sizes exclude mold flash and gate burrs. Mold flash at the non-lead sides should be less than 6 mils.
4. Dimension L is measured in gauge plane.
5. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.
Rev. 1.3 December 2007
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Page 12 of 14
AOZ1210
Tape and Reel Dimensions
SO-8 Carrier Tape
P1
P2
See Note 3
D1
T
See Note 5
E1
E2
E
See Note 3
B0
K0
D0
P0
A0
Feeding Direction
Unit: mm
Package
A0
B0
K0
D0
1.60
D1
E
E1
E2
P0
P1
P2
T
SO-8
6.40
5.20
2.10
1.50
12.00 1.75
5.50
8.00
4.00
2.00
0.25
(12mm) ±0.10 ±0.10 ±0.10 ±0.10 ±0.10 ±0.10 ±0.10 ±0.10 ±0.10 ±0.10 ±0.10 ±0.10
SO-8 Reel
W1
S
G
V
N
K
M
R
H
W
Tape Size Reel Size
M
N
W
W1
ø330.00 ø97.00 13.00 17.40
H
K
S
G
R
V
ø13.00
10.60
2.00
—
—
—
12mm
ø330
±0.50
±0.10 ±0.30 ±1.00
+0.50/-0.20
±0.50
SO-8 Tape
Leader/Trailer
& Orientation
Trailer Tape
300mm min. or
75 empty pockets
Components Tape
Orientation in Pocket
Leader Tape
500mm min. or
125 empty pockets
Rev. 1.3 December 2007
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Page 13 of 14
AOZ1210
AOZ1210 Package Marking
Z1210AI
FAYWLT
Part Number
Assembly Lot Code
Fab & Assembly Location
Year & Week Code
This datasheet contains preliminary data; supplementary data may be published at a later date.
Alpha & Omega Semiconductor reserves the right to make changes at any time without notice.
LIFE SUPPORT POLICY
ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
Rev. 1.3 December 2007
www.aosmd.com
Page 14 of 14
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