AOZ8304A [AOS]
Low Capacitance 3.3 V TVS Diode;
| 型号： | AOZ8304A |
| 厂家： | 
ALPHA & OMEGA SEMICONDUCTORS |
| 描述： | Low Capacitance 3.3 V TVS Diode 电视 |
| 文件： | 总8页 (文件大小：468K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AOZ8304A
Low Capacitance 3.3 V TVS Diode
General Description
Features
The AOZ8304A is a transient voltage suppressor array
designed to protect high speed data lines from ESD and
lightning.
z ESD protection for high-speed data lines:
– IEC 61000-4-2, level 4 (ESD) immunity test
–
±30 kV (air discharge) and ±30 kV (contact discharge)
– IEC 61000-4-4 (EFT) 40 A (5/50 ns)
– IEC 61000-4-5 (Lightning) 25 A
– Human Body Model (HBM) ±30 kV
This AOZ8304A incorporates eight surge rated, low
capacitance steering diodes and a TVS in a single
package. During transient conditions, the steering
diodes direct the transient to either the positive side of
the power supply line or to ground. The AOZ8304A
may be used to meet the ESD immunity requirements of
IEC 61000-4-2, Level 4 and IEC 61000-4-5. The TVS
diodes provide effective suppression of ESD voltages:
±30 kV (air discharge) and ±30 kV (contact discharge).
z Small package saves board space
z Low insertion loss
z Protects four I/O lines
z Low clamping voltage
z Low operating voltage: 3.3 V
z Green product
The AOZ8304A comes in a Halogen Free and RoHS
compliant DFN-10 2.6 mm x 2.6 mm package and is
rated over a -40 °C to +85 °C ambient temperature
range. The AOZ8304A is compatible with both lead free
and SnPb assembly techniques. The small size,
low capacitance and high ESD protection makes the
AOZ8304A ideal for protecting high speed video and
data communication interfaces.
z Pb-free device
Applications
z 10/100/1000 Ethernet
z USB 2.0 power and data line protection
z Video graphics cards
z Monitors and flat panel displays
z Digital Video Interface (DVI)
z T1/E1 telecom ports
Typical Application
AOZ8304A
TRD0+
TRD0-
TRD1+
TRD1-
Gigabit
RJ45
Connector
Ethernet
AOZ8304A
TRD2+
Controller
TRD2-
TRD3+
TRD3-
VCC
75Ω
75Ω 75Ω
75Ω
Figure 1. 10/100/1000 Ethernet Port Connection
Rev. 1.1 August 2011
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AOZ8304A
Ordering Information
Part Number
Ambient Temperature Range
-40 °C to +85 °C
Package
Environmental
Green Product
AOZ8304ADI
2.6 mm x 2.6 mm DFN-10
AOS Green Products (with “L” suffix) use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.
Pin Configuration
1
10
9
CH1
NC
NC
Pin Number
Description
2
3
4
5
CH2
NC
1, 3, 7, 9
2, 4, 6, 8, 10
5
Input/Output lines
No connection
VP
8
CH3
NC
GND
7
CH4
NC
Center Tab
Ground
6
VP
DFN-10
(Top View)
Absolute Maximum Ratings
Exceeding the Absolute Maximum ratings may damage the device.
Parameter
Rating
VP – GND
3.3 V
25 A
Peak Pulse Current (IPP), tP = 8/20 µs
Peak Power Dissipation (8 x 20 µs@ 25 °C)
Storage Temperature (TS)
ESD Rating per IEC61000-4-2, Contact(1)
ESD Rating per IEC61000-4-2, Air(1)
ESD Rating per Human Body Model(2)
400 W
-65 °C to +150 °C
±30 kV
±30 kV
±30 kV
Notes:
1. IEC 61000-4-2 discharge with CDischarge = 150 pF, RDischarge = 330 Ω.
2. Human Body Discharge per MIL-STD-883, Method 3015 CDischarge = 100 pF, RDischarge = 1.5 kΩ.
Maximum Operating Ratings
Parameter
Rating
Junction Temperature (TJ)
-40 °C to +85 °C
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AOZ8304A
Electrical Characteristics
TA = 25°C unless otherwise specified. Specifications in BOLD indicate a temperature range of -40 °C to +85 °C.
Symbol
Parameter
Conditions
Between pin 5 and GND(4)
VRWM = 3.3 V, between pins 5 and GND
Min.
Typ.
Max.
Units
VRWM
IR
Reverse Working Voltage
Reverse Leakage Current
3.3
5
V
µA
V
VBR
VCL
Reverse Breakdown Voltage VBR = 1 mA
3.5
5.6
Channel Clamp Voltage
Positive Transients
Negative Transient
Channel Clamp Voltage
Positive Transients
Negative Transient
Channel Clamp Voltage
Positive Transients
Negative Transient
Junction Capacitance
IPP = 5 A, tp = 100 ns, any I/O pin to
Ground(3)(6)(8)
7.00
V
V
-3.00
IPP = 10 A, tp = 100 ns, any I/O pin to
Ground(3)(6)(8)
8.00
V
V
-4.00
IPP = 25 A, tp = 100 ns, any I/O pin to
Ground(3)(6)(8)
10.00
-5.00
5
V
V
Cj
VR = 0 V, f = 1 MHz, any I/O pin to Ground(3)(7)
VR = 0 V, f = 1 MHz, between I/O pins(3)(7)
VR = 0 V, f = 1 MHz, any I/O pin to Ground(3)(6)
VR = 0 V, f = 1 MHz, between I/O pins(3)(6)
pF
pF
pF
pF
1.25
5
6
2.5
Notes:
3. These specifications are guaranteed by design.
4. The working peak reverse voltage, VRWM, should be equal to or greater than the DC or continuous peak operating voltage level.
5. VBR is measured at the pulse test current IT.
6. Measurements performed with no external capacitor on VP (pin 5 floating).
7. Measurements performed with VP biased to 3.3 Volts.
8. Measurements performed using a 100 ns Transmission Line Pulse (TLP) system.
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AOZ8304A
Typical Performance Characteristics
Forward Voltage vs. Forward Current
(tperiod = 100ns, tr = 1ns)
Clamping Voltage vs. Peak Pulse Current
(tperiod = 100ns, tr = 1ns)
12
6
5
4
3
2
1
0
10
8
6
4
5
10
15
20
25
5
10
15
20
25
Forward Current (A)
Peak Pulse Current, I (A)
PP
I/O – Gnd Insertion Loss (S21) vs. Frequency
Analog Crosstalk (I/O–I/O) vs. Frequency
5
0
0
-10
20
-5
-30
-40
-50
-60
-70
-80
-10
-15
-20
-25
-30
1
10
100
1,000
10,000
1
10
100
1,000
10,000
Frequency (MHz)
Frequency (MHz)
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AOZ8304A
Application Information
The AOZ8304A TVS is design to protect four data lines
from fast damaging transient over-voltage by clamping
the over-voltage to a reference. When the transient on a
protected data line exceeds the reference voltage, the
steering diode is forward bias and conducts harmful ESD
transients away from the sensitive circuitry under
protection.
clamping voltage. The inductance of the PCB can be
reduced by using short trace lengths and multiple layers
with separate ground and power planes. One effective
method to minimize loop problems is to incorporate a
ground plane in the PCB design. The AOZ8304A low
capacitance TVS is designed to protect four high speed
data transmission lines from transient over-voltages by
clamping them to a fixed reference. The low inductance
and construction minimizes voltage overshoot during
high current surges. When the voltage on the protected
line exceeds the reference voltage the internal steering
diodes are forward biased, conducting the transient
current away from the sensitive circuitry.
PCB Layout Guidelines
Printed circuit board layout is the key to achieving the
highest level of surge immunity on power and data lines.
The location of the protection devices on the PCB is the
simplest and most important design rule to follow. The
AOZ8304A devices should be located as close as
possible to the noise source. The placement of the
AOZ8304A devices should be used on all data and
power lines that enter or exit the PCB at the I/O
Good circuit board layout is critical for the suppression
of ESD induced transients. The following guidelines are
recommended:
connector. In most systems, surge pulses occur on data
and power lines that enter the PCB through the I/O
connector. Placing the AOZ8304A devices as close as
possible to the noise source ensures that a surge voltage
will be clamped before the pulse can be coupled into
adjacent PCB traces. In addition, the PCB should use the
shortest possible traces. A short trace length equates to
low impedance, which ensures that the surge energy will
be dissipated by the AOZ8304A device. Long signal
traces will act as antennas to receive energy from fields
that are produced by the ESD pulse. By keeping line
lengths as short as possible, the efficiency of the line to
act as an antenna for ESD related fields is reduced.
1. Place the TVS near the I/O terminals or connectors
to restrict transient coupling.
2. Fill unused portions of the PCB with ground plane.
3. Minimize the path length between the TVS and the
protected line.
4. Minimize all conductive loops including power and
ground loops.
5. The ESD transient return path to ground should be
kept as short as possible.
6. Never run critical signals near board edges.
7. Use ground planes whenever possible.
Minimize interconnecting line lengths by placing devices
with the most interconnect as close together as possible.
The protection circuits should shunt the surge voltage to
either the reference or chassis ground. Shunting the
surge voltage directly to the IC’s signal ground can cause
ground bounce. The clamping performance of TVS
diodes on a single ground PCB can be improved by
minimizing the impedance with relatively short and wide
ground traces. The PCB layout and IC package parasitic
inductances can cause significant overshoot to the TVS’s
8. Avoid running critical signal traces (clocks, resets,
etc.) near PCB edges.
9. Separate chassis ground traces from components
and signal traces by at least 4 mm.
10. Keep the chassis ground trace length-to-width ratio
< 5:1 to minimize inductance.
11. Protect all external connections with TVS diodes.
TPBIASx
1μF
56Ω
56Ω
IEEE 1394
Connector
TPAx+
IEEE 1394
PHY
TPAx-
TPBx+
TPBx-
GND
56Ω
5.1kΩ
56Ω
270pF
AOZ8304A
IEEE1394 Port Connection
Rev. 1.1 August 2011
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AOZ8304A
Package Dimensions, DFN 2.6 x 2.6, 10L
A
D1
D
D1/2
B
D/2
e
L
K
E/2
E1/2
E
E1
Pin #1 ID
Chamfer 0.30x45°
Pin #1 Dot
by Marking
TOP VIEW
BOTTOM VIEW
Dimensions in millimeters
Dimensions in inches
Symbols Min. Nom. Max.
Symbols Min. Nom. Max.
b
A
A1
b
0.50
0.00
0.20
0.55
—
0.60
0.05
0.30
A
A1
b
0.020 0.022 0.024
0.000 0.002
A
—
A1
0.25
0.008 0.010 0.012
0.006 REF.
c
0.152 REF.
2.60
c
D
2.55
2.10
2.55
1.21
2.65
2.20
2.65
1.31
D
0.100 0.102 0.104
0.083 0.085 0.087
0.100 0.102 0.104
0.048 0.050 0.052
0.050 BSC
SIDE VIEW
c
D1
E
2.15
D1
E
2.60
E1
e
1.26
E1
e
0.50 BSC
0.32 REF
0.35
RECOMMENDED LAND PATTERN
K
K
0.013 BSC
L
0.30
0.40
L
0.012 0.014 0.016
2.35
1.75
0.50
0.45
0.32
1.175
0.63
1.26
2.35
Pin #1 ID
Chamfer 0.20x45°
UNIT: mm
0.25
Note:
1. Controlling dimension is millimeter. Coverted inch dimensions are not necessarily exact
Rev. 1.1 August 2011
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AOZ8304A
Tape and Reel Dimensions, DFN 2.6 x 2.6, 10L
Carrier Tape
P1
D0
D1
P2
K0
E1
E2
R0.3
Max.
E
B0
A0
P0
T
R0.3 Typ.
Feeding Direction
UNIT: mm
Package
DFN
2.6x2.6
T
0.30
0.05
B0
2.80
0.10
A0
2.80
0.10
K0
1.10
D0
ø1.50
D1
ø1.50 12.0
0.3
E
E1
1.75
0.10
E2
5.50
0.05
P0
4.00
0.10
P1
4.00
0.10
P2
2.00
0.05
0.10 +0.1/-0.0 Min.
Reel
B
W1
S
K
60°
120°
M
N
H
Arbor Hole Detail A
Scale 2:1
2.24
W
2.84
Back View
B
Section B-B
Front View
S
2.0
0.2
UNIT: mm
Tape Size
12mm
Reel Size
ø180
M
N
W
13
0.5
W1
17.0
H
ø13.0
0.2
K
10.5
0.25
ø179
1.0
60
0.5
Leader / Trailer
& Orientation
Trailer Tape
300mm Min.
Components Tape
Orientation in Pocket
Leader Tape
500mm Min.
Rev. 1.1 August 2011
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Page 7 of 8
AOZ8304A
Part Marking
AOZ8304ADI
(DFN-10)
Assembly Location Code
Option Code
PNOA
YWLT
Part Number Code
Year & Week Code
Assembly Lot Code
This datasheet contains preliminary data; supplementary data may be published at a later date.
Alpha & Omega Semiconductor reserves the right to make changes at any time without notice.
LIFE SUPPORT POLICY
ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
Rev. 1.1 August 2011
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Page 8 of 8
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