AOZ8308 [AOS]

Low Capacitance 2.5 V TVS Diode;
AOZ8308
型号: AOZ8308
厂家: ALPHA & OMEGA SEMICONDUCTORS    ALPHA & OMEGA SEMICONDUCTORS
描述:

Low Capacitance 2.5 V TVS Diode

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AOZ8308  
Low Capacitance 2.5 V TVS Diode  
General Description  
The AOZ8308 is a transient voltage suppressor array  
designed to protect high speed data lines from ESD and  
lightning.  
Features  
ESD protection for high-speed data lines:  
IEC 61000-4-2, level 4 (ESD) immunity test  
This AOZ8308 incorporates eight surge rated, low  
capacitance steering diodes and a TVS in a single  
package. During transient conditions, the steering  
diodes direct the transient to either the positive side of  
the power supply line or to ground. The AOZ8308  
may be used to meet the ESD immunity requirements of  
IEC 61000-4-2, Level 4 and IEC 61000-4-5. The TVS  
diodes provide effective suppression of ESD voltages:  
±30 kV (air discharge) and ±30 kV (contact discharge).  
±30 kV (air discharge) and ±30 kV (contact discharge)  
IEC 61000-4-4 (EFT) 40 A (5/50 ns)  
IEC 61000-4-5 (Lightning) 25 A  
Human Body Model (HBM) ±30 kV  
Protects four I/O lines  
Low clamping voltage  
Low operating voltage: 2.5 V  
Applications  
The AOZ8308 comes in a Halogen Free and RoHS  
compliant SO-8 package and is rated over a -40 °C to  
+85 °C ambient temperature range. The AOZ8308 is  
compatible with both lead free and SnPb assembly  
techniques. The small size, low capacitance and high  
ESD protection makes the AOZ8308 ideal for protecting  
high speed video and data communication interfaces.  
10/100 Ethernet  
USB 2.0 power and data line protection  
Video graphics cards  
Monitors and flat panel displays  
Digital Video Interface (DVI)  
T1/E1 telecom ports  
Typical Application  
AOZ8308  
TX+  
1
2
3
4
8
7
6
5
10/100  
RJ45  
Connector  
TX-  
Ethernet  
RX+  
PHY  
RX-  
VCC  
75Ω 75Ω  
Figure 1. 10/100 Ethernet Port Connection  
Rev. 1.0 February 2015  
www.aosmd.com  
Page 1 of 7  
AOZ8308  
1
2
3
4
8
7
6
5
Line 1  
Line 2  
Line 1  
Pin 1, 3  
Pin 6, 8  
Pin 5, 7  
Line 2  
Line 3  
Line 4  
Line 3  
Line 4  
Pin 2, 4  
Figure 2. Circuit Diagram  
Figure 3. Low Capacitance Protection  
of Two Differential Line Pairs  
Part Number  
Ambient Temperature Range  
Package  
SO-8  
Environmental  
AOZ8308SO-02  
-40 °C to +85 °C  
Green Product  
AOS Green Products (with “L” suffix) use reduced levels of Halogens, and are also RoHS compliant.  
Please visit www.aosmd.com/media/AOSGreenPolicy.pdf for additional information.  
Pin Configuration  
1
2
3
4
8
7
6
5
SO-8  
(Top View)  
Rev. 1.0 February 2015  
www.aosmd.com  
Page 2 of 7  
AOZ8308  
Absolute Maximum Ratings  
Exceeding the Absolute Maximum ratings may damage the device.  
Parameter  
Rating  
VP – GND  
2.5 V  
25 A  
Peak Pulse Current (IPP), tP = 8/20 µs  
Peak Power Dissipation (8 x 20 µs@ 25 °C)  
Storage Temperature (TS)  
ESD Rating per IEC61000-4-2, Contact(1)  
ESD Rating per IEC61000-4-2, Air(1)  
ESD Rating per Human Body Model(2)  
450 W  
-65 °C to +150 °C  
±30 kV  
±30 kV  
±30 kV  
Notes:  
1. IEC 61000-4-2 discharge with CDischarge = 150 pF, RDischarge = 330 .  
2. Human Body Discharge per MIL-STD-883, Method 3015 CDischarge = 100 pF, RDischarge = 1.5 k.  
Maximum Operating Ratings  
Parameter  
Rating  
Junction Temperature (TJ)  
-40 °C to +125 °C  
Electrical Characteristics  
TA = 25°C unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Between pins 1 and 2(4)  
VRWM = 2.5 V, between pins 1 and 2  
Min. Typ.  
Max. Units  
VRWM  
IR  
Reverse Working Voltage  
Reverse Leakage Current  
2.5  
0.1  
V
µA  
V
VBR  
VCL  
Reverse Breakdown Voltage IT = 100 µA  
2.8  
Channel Clamp Voltage  
Each Line  
IPP = 5 A, tp = 8/20 µs(3)  
5.5  
7.5  
V
V
Channel Clamp Voltage  
Each Line  
I
I
PP = 10 A, tp = 8/20 µs(3)  
PP = 25 A, tp = 8/20 µs(3)  
Channel Clamp Voltage  
Each Line  
15  
V
Cj  
Junction Capacitance  
VR = 0 V, f = 1 MHz, Each Line(3)  
1.2  
2.5  
pF  
Notes:  
3. These specifications are guaranteed by design.  
4. The working peak reverse voltage, VRWM, should be equal to or greater than the DC or continuous peak operating voltage level.  
5. VBR is measured at the pulse test current IT.  
Rev. 1.0 February 2015  
www.aosmd.com  
Page 3 of 7  
AOZ8308  
Typical Performance Characteristics  
Peak Pulse Current va. Clamping Voltage  
Typical Variation of CIN vs. VR  
(f = 1MHz, T = 25°C)  
(tr = 8μs, td = 20μs)  
25  
2.0  
1.5  
1.0  
0.5  
0
20  
15  
10  
5
0
4
6
8
10  
12  
14  
16  
18  
20  
0
0.5  
1.0  
1.5  
2.0  
2.5  
Clamping Voltage (V)  
Working Voltage (V)  
Rev. 1.0 February 2015  
www.aosmd.com  
Page 4 of 7  
AOZ8308  
Application Information  
The AOZ8308 TVS is design to protect four data lines  
from fast damaging transient over-voltage by clamping  
the over-voltage to a reference. When the transient on a  
protected data line exceeds the reference voltage, the  
steering diode is forward bias and conducts harmful ESD  
transients away from the sensitive circuitry under  
protection.  
clamping voltage. The inductance of the PCB can be  
reduced by using short trace lengths and multiple layers  
with separate ground and power planes. One effective  
method to minimize loop problems is to incorporate a  
ground plane in the PCB design. The AOZ8308 low  
capacitance TVS is designed to protect four high speed  
data transmission lines from transient over-voltages by  
clamping them to a fixed reference. The low inductance  
and construction minimizes voltage overshoot during  
high current surges. When the voltage on the protected  
line exceeds the reference voltage the internal steering  
diodes are forward biased, conducting the transient  
current away from the sensitive circuitry.  
PCB Layout Guidelines  
Printed circuit board layout is the key to achieving the  
highest level of surge immunity on power and data lines.  
The location of the protection devices on the PCB is the  
simplest and most important design rule to follow. The  
AOZ8308 devices should be located as close as possible  
to the noise source. The placement of the AOZ8308  
devices should be used on all data and power lines that  
enter or exit the PCB at the I/O connector. In most  
systems, surge pulses occur on data and power lines that  
enter the PCB through the I/O connector. Placing the  
AOZ8308 devices as close as possible to the noise  
source ensures that a surge voltage will be clamped  
before the pulse can be coupled into adjacent PCB  
traces. In addition, the PCB should use the shortest  
possible traces. A short trace length equates to low  
impedance, which ensures that the surge energy will be  
dissipated by the AOZ8308 device. Long signal traces  
will act as antennas to receive energy from fields that are  
produced by the ESD pulse. By keeping line lengths as  
short as possible, the efficiency of the line to act as an  
antenna for ESD related fields is reduced.  
Good circuit board layout is critical for the suppression  
of ESD induced transients. The following guidelines are  
recommended:  
1. Place the TVS near the I/O terminals or connectors  
to restrict transient coupling.  
2. Fill unused portions of the PCB with ground plane.  
3. Minimize the path length between the TVS and the  
protected line.  
4. Minimize all conductive loops including power and  
ground loops.  
5. The ESD transient return path to ground should be  
kept as short as possible.  
6. Never run critical signals near board edges.  
7. Use ground planes whenever possible.  
Minimize interconnecting line lengths by placing devices  
with the most interconnect as close together as possible.  
The protection circuits should shunt the surge voltage to  
either the reference or chassis ground. Shunting the  
surge voltage directly to the IC’s signal ground can cause  
ground bounce. The clamping performance of TVS  
diodes on a single ground PCB can be improved by  
minimizing the impedance with relatively short and wide  
ground traces. The PCB layout and IC package parasitic  
inductances can cause significant overshoot to the TVS’  
8. Avoid running critical signal traces (clocks, resets,  
etc.) near PCB edges.  
9. Separate chassis ground traces from components  
and signal traces by at least 4 mm.  
10. Keep the chassis ground trace length-to-width ratio  
< 5:1 to minimize inductance.  
11. Protect all external connections with TVS diodes.  
Rev. 1.0 February 2015  
www.aosmd.com  
Page 5 of 7  
AOZ8308  
Package Dimensions, SO-8L  
D
Gauge Plane  
Seating Plane  
e
0.25  
8
L
E1  
E
h x 45  
1
C
θ
7 (4x)  
A2  
A
0.1  
A1  
b
RECOMMENDED LAND PATTERN  
Dimensions in millimeters  
Dimensions in inches  
Symbols Min.  
Nom. Max.  
Symbols Min.  
Nom. Max.  
0.053 0.065 0.069  
0.004 0.010  
0.049 0.059 0.065  
A
A1  
A2  
b
c
D
E
1.35  
0.10  
1.25  
0.31  
0.17  
4.80  
3.80  
1.65  
1.50  
1.75  
0.25  
1.65  
0.51  
0.25  
5.00  
4.00  
A
A1  
A2  
b
2.20  
0.012  
0.007  
0.020  
0.010  
c
4.90  
3.90  
1.27 BSC  
6.00  
D
E
e
0.189 0.193 0.197  
0.150 0.154 0.157  
0.050 BSC  
5.74  
e
2.87  
1.27  
E1  
h
L
5.80  
0.25  
0.40  
6.20  
0.50  
1.27  
E1  
h
L
0.228 0.236 0.244  
0.010  
0.016  
0.020  
0.050  
8°  
θ
0
°
8
°
θ
0
°
0.80  
UNIT: mm  
0.635  
Notes:  
1. All dimensions are in millimeters.  
2. Dimensions are inclusive of plating  
3. Package body sizes exclude mold flash and gate burrs. Mold flash at the non-lead sides should be less than 6 mils.  
4. Dimension L is measured in gauge plane.  
5. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.  
Rev. 1.0 February 2015  
www.aosmd.com  
Page 6 of 7  
AOZ8308  
Part Marking  
AOZ8308SO  
(SO-8)  
Z 8 3 0 8 S O  
F A Y W L T  
Part Number Code  
Assembly Lot Code  
Year Code and Week Code  
Fab Code & Assembly Location Code  
LEGAL DISCLAIMER  
Alpha and Omega Semiconductor makes no representations or warranties with respect to the accuracy or  
completeness of the information provided herein and takes no liabilities for the consequences of use of such  
information or any product described herein. Alpha and Omega Semiconductor reserves the right to make changes  
to such information at any time without further notice. This document does not constitute the grant of any intellectual  
property rights or representation of non-infringement of any third party’s intellectual property rights.  
LIFE SUPPORT POLICY  
ALPHA AND OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL  
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.  
As used herein:  
1. Life support devices or systems are devices or  
systems which, (a) are intended for surgical implant into  
the body or (b) support or sustain life, and (c) whose  
failure to perform when properly used in accordance  
with instructions for use provided in the labeling, can be  
reasonably expected to result in a significant injury of  
the user.  
2. A critical component in any component of a life  
support, device, or system whose failure to perform can  
be reasonably expected to cause the failure of the life  
support device or system, or to affect its safety or  
effectiveness.  
Rev. 1.0 February 2015  
www.aosmd.com  
Page 7 of 7  

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