AOZ8903 [AOS]
Ultra-Low Capacitance TVS Diode Array;
| 型号： | AOZ8903 |
| 厂家： | 
ALPHA & OMEGA SEMICONDUCTORS |
| 描述： | Ultra-Low Capacitance TVS Diode Array 电视 |
| 文件： | 总8页 (文件大小：360K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AOZ8903
Ultra-Low Capacitance TVS Diode Array
General Description
Features
The AOZ8903 is a transient voltage suppressor array
designed to protect high speed data lines from Electro
Static Discharge (ESD) and lightning.
ESD protection for high-speed data lines:
– IEC 61000-4-2 (ESD) ±20kV (air), ±15kV (contact)
– IEC 61000-4-5 (Lightning) 4A (8/20µs)
– IEC 61000-4-4 (EFT) 40A (5/50nS)
– Human Body Model (HBM) ±24kV
Protects four I/O lines
This device incorporates eight surge rated, low
capacitance steering diodes and a Transient Voltage
Suppressor (TVS) in a single package. During transient
conditions, the steering diodes direct the transient to
either the positive side of the power supply line or to
ground. They may be used to meet the ESD immunity
requirements of IEC 61000-4-2, Level 4 (±15kV air,
±8kV contact discharge).
Low clamping voltage
Low operating voltage: 5.0V
Applications
USB 2.0 Power and Data Line Protection
Video Graphics Cards
The AOZ8903 comes in RoHS compliant SOT-23
package. It is rated over a -40°C to +85°C ambient
temperature range.
Monitors and Flat Panel Displays
Digital Video Interface (DVI)
Typical Application
USB Host
Controller
Downstream
Ports
+5V
VBUS
R
R
T
T
D+
D-
VBUS
GND
AOZ8903
+5V
VBUS
R
R
T
T
D+
D-
GND
Figure 1. 2 USB High Speed Ports
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AOZ8903
Ordering Information
Part Number
Ambient Temperature Range
-40°C to +85°C
Package
Environmental
AOZ8903CI
SOT23-6
RoHS Compliant
Green Product
AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/media/AOSGreenPolicy.pdf for additional information.
Pin Configuration
1
2
3
6
5
4
CH1
VN
CH4
VP
CH2
CH3
SOT23-6
(Top View)
Absolute Maximum Ratings
Exceeding the Absolute Maximum ratings may damage the device.
Parameter
Rating
VP – VN
6V
Peak Pulse Current (IPP), tP = 8/20µs
Peak Power Dissipation (8/20µs) @ 25°C
Storage Temperature (TS)
ESD Rating per IEC61000-4-2, contact(1)
ESD Rating per IEC61000-4-2, air(2)
ESD Rating per Human Body Model(2)
Junction Temperature (TJ)
4A
40W
-65°C to +150°C
±15kV
±20kV
±24kV
-40°C to +125°C
Notes:
1. IEC 61000-4-2 discharge with CDischarge = 150pF, RDischarge = 330Ω.
2. Human Body Discharge per MIL-STD-883, Method 3015 CDischarge = 100pF, RDischarge = 1.5kΩ.
Rev. 1.0 December 2014
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AOZ8903
Electrical Characteristics
TA = 25°C unless otherwise specified
Symbol
Parameter
Conditions
Between pin 5 and 2(4)
Min.
Typ.
Max. Units
VRWM
VBR
IR
Reverse Working Voltage
5.5
V
V
Reverse Breakdown Voltage IT = 1mA, between pins 5 and 2(5)
6.0
0.6
Reverse Leakage Current
Diode Forward Voltage
VRWM = 5V, any I/O pin to Ground
If = 15mA, any I/O pin to Ground
1.0
1.0
µA
V
VF
VCL
Channel Clamp Voltage
Positive Transients
IPP = 1A, tp = 100ns, any I/O pin to
Ground(3)(6)
3.0
4.5
V
V
Channel Clamp Voltage
Positive Transients
IPP = 5A, tp = 100ns, any I/O pin to
Ground(3)(6)
Channel Clamp Voltage
Positive Transients
IPP = 12A, tp = 100ns, any I/O pin to
Ground(3)(6)
7.0
V
Cj
Junction Capacitance
VR = 0V, f = 1Mhz, any I/O pin to Ground(3)
VR = 0V, f = 1Mhz, between I/O pins(3)
0.5
0.75
0.03
pF
pF
Cj
Channel Input Capacitance
Matching
Notes:
3. These specifications are guaranteed by design.
4. The working peak reverse voltage, VRWM, should be equal to or greater than the DC or continuous peak operating voltage level.
5. VBR is measured at the pulse test current IT.
6. Measurements performed using a 100 nSec Transmission Line Pulse (TLP) system.
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AOZ8903
Typical Performance Characteristics
TLP Current vs. Clamping Voltage
Forward Current vs. Forward Voltage
(tperiod = 100nS, tr = 1ns)
0
-5
30
25
20
15
10
5
-10
-15
-20
-25
-30
0
0
2
4
6
8
10
12
-15
-12
-9
-6
-3
0
Clamping Voltage (V)
Forward Voltage (V)
Typical Variation of CIN vs. VIN
(f = 1MHz, T = 25°C)
1.0
0.8
0.6
0.4
0.2
0
0
1
2
3
4
5
Working Voltage (V)
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AOZ8903
clamping voltage. The inductance of the PCB can be
Application Information
reduced by using short trace lengths and multiple layers
with separate ground and power planes. One effective
method to minimize loop problems is to incorporate a
ground plane in the PCB design. The AOZ8903 ultra-low
capacitance TVS is designed to protect four high speed
data transmission lines from transient over-voltages by
clamping them to a fixed reference. The low inductance
and construction minimizes voltage overshoot during
high current surges. When the voltage on the protected
line exceeds the reference voltage the internal steering
diodes are forward biased, conducting the transient
current away from the sensitive circuitry.
The AOZ8903 TVS is design to protect four data lines
from fast damaging transient over-voltage by clamping it
to a reference. When the transient on a protected data
line exceed the reference voltage the steering diode is
forward bias thus, conducting the harmful ESD transient
away from the sensitive circuitry under protection.
PCB Layout Guidelines
Printed circuit board layout is the key to achieving the
highest level of surge immunity on power and data lines.
The location of the protection devices on the PCB is the
simplest and most important design rule to follow. The
AOZ8903 devices should be located as close as possible
to the noise source. The placement of the AOZ8903
devices should be used on all data and power lines that
enter or exit the PCB at the I/O connector. In most
systems, surge pulses occur on data and power lines that
enter the PCB through the I/O connector. Placing the
AOZ8903 devices as close as possible to the noise
source ensures that a surge voltage will be clamped
before the pulse can be coupled into adjacent PCB
traces. In addition, the PCB should use the shortest
possible traces. A short trace length equates to low
impedance, which ensures that the surge energy will be
dissipated by the AOZ8903 device. Long signal traces
will act as antennas to receive energy from fields that are
produced by the ESD pulse. By keeping line lengths as
short as possible, the efficiency of the line to act as an
antenna for ESD related fields is reduced. Minimize
interconnecting line lengths by placing devices with the
most interconnect as close together as possible. The
protection circuits should shunt the surge voltage to
either the reference or chassis ground. Shunting the
surge voltage directly to the IC’s signal ground can cause
ground bounce. The clamping performance of TVS
diodes on a single ground PCB can be improved by
minimizing the impedance with relatively short and wide
ground traces. The PCB layout and IC package parasitic
inductances can cause significant overshoot to the TVS’s
Good circuit board layout is critical for the suppression
of ESD induced transients. The following guidelines are
recommended:
1. Place the TVS near the IO terminals or connectors to
restrict transient coupling.
2. Fill unused portions of the PCB with ground plane.
3. Minimize the path length between the TVS and the
protected line.
4. Minimize all conductive loops including power and
ground loops.
5. The ESD transient return path to ground should be
kept as short as possible.
6. Never run critical signals near board edges.
7. Use ground planes whenever possible.
8. Avoid running critical signal traces (clocks, resets,
etc.) near PCB edges.
9. Separate chassis ground traces from components
and signal traces by at least 4mm.
10. Keep the chassis ground trace length-to-width ratio
<5:1 to minimize inductance.
11. Protect all external connections with TVS diodes.
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AOZ8903
Package Dimensions, SOT23-6L
Gauge Plane
c
Seating Plane
0.25mm
D
e1
L
E
E1
θ1
b
e
A2
A
.010mm
A1
Dimensions in millimeters
Dimensions in inches
Symbols Min.
Nom. Max.
Symbols Min.
Nom. Max.
RECOMMENDED LAND PATTERN
A
A1
A2
b
c
D
E
E1
e
0.90
0.00
0.70
0.30
0.08
2.70
2.50
1.50
—
—
1.10
0.40
0.13
2.90
2.80
1.60
1.25
0.15
1.20
0.50
0.20
3.10
3.10
1.70
A
A1
A2
b
c
D
E
E1
e
0.035
0.00
—
—
0.049
0.006
1.20
0.028 0.043 0.047
0.012 0.016 0.020
0.003 0.005 0.008
0.106 0.114 0.122
0.098 0.110 0.122
0.059 0.063 0.067
0.037 BSC
2.40
0.80
0.95
0.63
0.95 BSC
1.90 BSC
—
UNIT: mm
e1
L
θ1
e1
L
θ1
0.075 BSC
0.30
0°
0.60
8°
0.012
0°
—
—
0.024
8°
—
Notes:
1. Package body sizes exclude mold flash and gate burrs. Mold flash at the non-lead sides should be less than 5 mils each.
2. Dimension “L” is measured in gauge plane.
3. Tolerance 0.100 mm (4 mil) unless otherꢀise specified.
4. Folloꢀed from JEDEC MO-178C & MO-193C.
5. Controlling dimension is millimeter. Converted inch dimensions are not necessarily exact.
Rev. 1.0 December 2014
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AOZ8903
Tape and Reel Dimensions, SOT23-6L
P2
Tape
A
P1
D1
A–A
D0
E1
E2
K0
B0
A0
P0
T
E
A
Feeding Direction
Unit: mm
Package
SOT-23
A0
B0
K0
D0
D1
1.00
E
E1
E2
P0
P1
P2
T
3.15
0.10
3.20
0.10
1.40
0.10
1.50
0.05
8.00
0.30
1.75
0.10
3.50
0.05
4.00
0.10
4.00
0.10
2.00
0.05
0.23
0.03
0.10/-0.0
W1
Reel
S
R
K
M
J
H
N
Unit: mm
Tape Size
8 mm
Reel Size
M
N
W1
8.40
H
S
K
R
J
ø177.80
ø13.00
12.70
4.00
+0.10/-0.10
ø177.80
MAX.
ø55.00
MIN.
1.50 10.10
MIN. MIN.
+1.50/-0.00 +0.50 / -0.20
Leader/Trailer and Orientation
Unit Per Reel:
3000pcs
Trailer Tape
300mm min.
Components Tape
Orientation in Pocket
Leader Tape
500mm min.
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AOZ8903
Part Marking
AOZ8903CI
(SOT-23)
Lot Number
BUOW
Assembly Date
Otption & Assembly Location
Part Number
LEGAL DISCLAIMER
Alpha and Omega Semiconductor makes no representations or warranties with respect to the accuracy or
completeness of the information provided herein and takes no liabilities for the consequences of use of such
information or any product described herein. Alpha and Omega Semiconductor reserves the right to make changes
to such information at any time without further notice. This document does not constitute the grant of any intellectual
property rights or representation of non-infringement of any third party’s intellectual property rights.
LIFE SUPPORT POLICY
ALPHA AND OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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