24AA256T-EP [ARTSCHIP]

I2C CMOS Serial EEPROM;


型号：	24AA256T-EP
厂家：	Artschip
描述：	I2C CMOS Serial EEPROM 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总9页 (文件大小：381K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

24LC256

256K I²C^TMCMOS Serial EEPROM

DEVICE SELECTION TABLE

Part

VCC

Max Clock Temp

Frequency Ranges

PACKAGE TYPE

PDIP

Number

24AA256

24LC256

Range

1.8-5.5V

400kHz†

400kHz

I,E

† 100kHz for Vcc < 2.5V.

100kHz for E temperature range.

FEATURES

z Low power CMOS technology

-Maximum write current 3mA at 5.5V

-Maximum read current 400µA at 5.5V

-Standby current 100nA typical at 5.5V

z 2-wire serial interface bus, I²C compatible

z Cascadable for up to eight devices

z Self-timed ERASE/WRITE cycle

z 64-byte page-write mode available

z 5 ms max write-cycle time

SOIC

z Hardware write protect for entire array

z Schmitt trigger inputs for noise suppression

z 100,000 erase/write cycles guaranteed

z Electrostatic discharge protection > 4000V

z Data retention > 200 years

BLOCK DIAGRAM

z 8-pin PDIP and SOIC (208 mil) packages

z Temperature ranges:

-Industrial (I): -40℃ to +85℃

-Automotive (E): -40℃ to +125℃

DESCRIPTION

The Artschip technology Inc. 24AA256/24LC256 (24xx256*) is

a 32K x 8 (256k bit) Serial Electrically Erasable PROM,

capable of operation across a broad voltage range (1.8V to

5.5V). it has been developed for advanced, low power

applications such as personal communications or data

acquisition. This device also has a page-write capability of up

to 64 bytes of data. This device is capable of both random and

sequential reads up to the 256k boundary. Functional address

lines allow up to eight devices on the same bus, for up to 2

Mbit address space. This device is available in the standard

8-pin plastic DIP, and 8-pin SOIC (208 mil) packages.

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24LC256

256K I²C^TMCMOS Serial EEPROM

1.0 ELECTRICAL CHARACTERISTICS

1.1 Maximum Ratings*

TABLE 1-1 PIN FUNCTION TABLE

Vcc……………………………………………………7.0V

All inputs and outputs w.r.t. Vss………-0.6V to Vcc +1.0V

Storage temperature ………………….-65℃ to +150℃

Ambient temp. with power applied……-65℃ to +125℃

Soldering temperature of leads (10 seconds)……+300℃

ESD protection on all pins……………………….. ≥4kV

*Notice: Stresses above those listed under “maximum

Ratings” may cause permanent damage to the device. This is

a stress rating only and functional operation of the device at

those or any other conditions above those indicated in the

operational listings of this specification is not implied.

Exposure to maximum rating conditions for external periods

may affect device reliability.

Name

Function

A0,A1,A2

VSS

SDA

SCL

Vcc

User Configurable Chip Selects

Ground

Serial Data

Serial Clock

Write Protect input

+1.8 to 5.5 (24AA256)

+1.8 to 5.5V (24LC256)

TABLE 1-2 DC CHARACTERISTICS

All parameters apply across the Industrial (I): Vcc=+1.8V to 5.5V

Tamb = -40℃ to +85℃

specified operating ranges unless Automotive (E): Vcc=+4.5V to 5.5V Tamb=-40℃ to 125℃

otherwise noted.

Parameter

Symbol

Min

Max

Units

Conditions

A0,A1,A2,

SCL, SDA, and WP pins:

High level input voltage

Low level input voltage

V_IH

V_IL

0.7Vcc

0.3Vcc

0.2Vcc

Vcc ≥2.5V

Vcc <2.5V

Vcc ≥2.5V (Note)

Hysteresis of Schmitt Trigger Y_HYS

Inputs (SDA, SCL pins)

0.05 Vcc

Low level output voltage

V_OL

0.40

I_OL=3.0mA @ Vcc=4.5V

I_OL=2.1mA @ Vcc=2.5V

V_IN= Vss or Vcc, WP=Vss

V_IN=Vss or Vcc, WP=Vcc

V_OUT=Vss or Vcc

Input leakage current

I_LI

-10

µA

Output leakage current

Pin capacitance

I_LO

C_IN, C_OUT

-10

µA

Vcc=5.0V (Note)

(all inputs/outputs)

Operating Current

Tamb=25℃, fc=1MHz

Vcc=5.5V

Vcc=5.5V, S_CL=400kHz

S_CL=S_DA=Vcc=5.5V

A0,A1,A2,WP=Vss

Icc Write

Icc Read

Iccs

400

µA

Standby current

Note: This parameter is periodically sampled and not 100% tested..

FIGURE 1-1: BUS TIMING DATA

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24LC256

256K I²C^TMCMOS Serial EEPROM

TABLE 1-3 AC CHARACTERISTICS

All parameters apply across the Industrial (I): Vcc=+1.8V to 5.5V

Tamb = -40℃ to +85℃

specified

operating

ranges Automotive (E): Vcc=+4.5V to 5.5V Tamb=-40℃ to 125℃

unless otherwise noted.

Parameter

Clock frequency

Symbol

F_CLIK

Min

Max

100

Units

kHz

Conditions

4.5V≤Vcc≤5.5V (E Temp range)

1.8V≤Vcc≤2.5V

400

2.5V≤Vcc≤5.5V

Clock high time

Clock low time

T_HIGH

T_LOW

4000

600

4700

1300

4.5V≤Vcc≤5.5V (E Temp range)

1.8V≤Vcc≤2.5V

2.5V≤Vcc≤5.5V

4.5V≤Vcc≤5.5V (E Temp range)

1.8V≤Vcc≤2.5V

2.5V≤Vcc≤5.5V

SDA and SCL rise time

(Note 1)

1000

4.5V≤Vcc≤5.5V (E Temp range)

1.8V≤Vcc≤2.5V

300

2.5V≤Vcc≤5.5V

SDA and SCL fall Time

START condition hold time

T_HD:STA

300

(Note 1)

4.5V≤Vcc≤5.5V (E Temp range)

1.8V≤Vcc≤2.5V

2.5V≤Vcc≤5.5V

4.5V≤Vcc≤5.5V (E Temp range)

1.8V≤Vcc≤2.5V

2.5V≤Vcc≤5.5V

(Note 2)

4.5V≤Vcc≤5.5V (E Temp range)

1.8V≤Vcc≤2.5V

2.5V≤Vcc≤5.5V

4.5V≤Vcc≤5.5V (E Temp range)

1.8V≤Vcc≤2.5V

2.5V≤Vcc≤5.5V

4.5V≤Vcc≤5.5V (E Temp range)

1.8V≤Vcc≤2.5V

2.5V≤Vcc≤5.5V

4.5V≤Vcc≤5.5V (E Temp range)

1.8V≤Vcc≤2.5V

2.5V≤Vcc≤5.5V

4.5V≤Vcc≤5.5V (E Temp range)

1.8V≤Vcc≤2.5V

2.5V≤Vcc≤5.5V

4000

600

4700

600

250

100

4000

600

4000

600

4700

1300

START condition setup time

T_HD:STA

Data input hold time

Data input setup time

T_HD:DAT

T_SU:DAT

STOP condition setup time

WP setup time

T_HD:STO

T_SU:WP

T_HD:WP

T_AA

WP hold time

Output valid from clock

(Note 2)

3500

900

Bus free time: Time the bus T_BUF

must be free before a new

transmission can start

Output fall time from V_IH

Minimum to V_ILmaximum

Input filter spike suppression

(SDA and SCL pins)

4700

1300

4.5V≤Vcc≤5.5V (E Temp range)

1.8V≤Vcc≤2.5V

2.5V≤Vcc≤5.5V

T_OF

T_SP

T_WC

250

C_B≤100pF (Note 1)

(Notes 1 and 3)

Write cycle time (byte or page)

Endurance

cycles

100,000

25℃, Vcc=5.0V, Block Mode (Note 4)

Note 1: Not 100% tested. C_B=total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns)

of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3. The combined T_SPand V_HYSspecifications are due to new Schmitt trigger inputs which provide improved noise spike

suppression. This eliminates the need for a TI specification for standard operation.

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please

consult the Total Endurance Model Which can be obtained on artschip’s website.

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24LC256

256K I²C^TMCMOS Serial EEPROM

2.0 PIN DESCRIPTIONS

2.1 A0,A1,A2 Chip Address Inputs

while the clock line is HIGH will be interpreted as a START or

STOP condition.

The A0, A1,A2 inputs are used by the 24XX256 for multiple

device operation. The levels on these inputs are compared

with the corresponding bits in the slave address. The chip is

selected if the compare is true.

Accordingly, the following bus conditions have been defined

(Figure 4-1).

4.1 Bus not Busy (A)

Both data and clock lines remain HIGH.

Up to eight device may be connected to the same bus by

using different chip select bit combinations. If left unconnected,

these inputs will be pulled down internally to Vss.

2.2 SDA Serial Data

4.2 Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the clock (SCL)

is HIGH determines a START condition. All commands must

be preceded by a START condition.

This is a bi-directional pin used to transfer addresses and data

into and data out of the device. It is an opendrain terminal,

therefore, the SDA bus requires a pull up resistor to Vcc

(typical 10 kΩ for 100kHz,2kΩ for 400kHz)

4.3 Stop Data Transfer (C)

A Low to HIGH transition of the SDA line while the clock (SCL)

is HIGH determines a STOP condition. All operations must

end with a STOP condition.

For normal data transfer SDA is allowed to change only during

SCL low. Changes during SCL high are reserved for indicating

the START and STOP conditions.

4.4 Data Valid (D)

The state of the data line represents valid data when, after a

START condition, the data line is stable for the duration of the

HIGH period of the clock signal.

2.3 SCL Serial Clock

This input is used to synchronize the data transfer from and to

the device.

2.4 WP

This pin can be connected to either Vss, Vcc or left floating.

An internal pull-down on this pin will keep the device in the

unprotected state if left floating. If tied to Vss or left floating,

normal memory operation is enabled (read/write the entire

memory 0000-7FFF).

The data on the line must be changed during the LOW period

of the clock signal. There is one bit of data per clock pulse.

Each data transfer is initiated with a START condition and

terminated with a STOP condition. The number of the data

bytes transferred between the START and STOP conditions is

determined by the master device.

4.5 Acknowledge

Each receiving device, when addressed, is obliged to

generate an acknowledge signal after the reception of each

byte. The master device must generate an extra clock pulse

which is associated with this acknowledge bit.

Note: The 24xx256 does not generate any acknowledge bits if

an internal programming cycle is in progress.

A device that acknowledges must pull down the SDA line

during the acknowledge clock pulse in such a way that the

SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse. Of course, setup and hold

times must be taken into account. During reads, a master

must signal an end of data to the slave by NOT generating an

acknowledge bit on the last byte that has been clocked out of

the slave. In this case, the slave (24xx256) will leave the data

line HIGH to enable the master to generate the STOP

condition.

If tied to Vcc, WRITE operations are inhibited. Read

operations are not affected.

3.0 FUNCTIONAL DESCRIPTION

The 24xx256 supports a bi-directional 2-wire bus and data

transmission protocol. A device that sends data onto the bus

is defined as a transmitter, and a device receiving data as a

receiver. The bus must be controlled by a master device

which generates the serial clock (SCL), controls the bus

access, and generates the START and STOP conditions while

the 24xx256 works as a slave. Both master and slave can

operate as a transmitter or receiver, but the master device

determines which mode is activated.

4.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

.Data transfer may be initiated only when the bus is not busy.

.During data transfer, the data line must remain stable

whenever the clock line is HIGH. Changes in the data line

FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

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24LC256

256K I²C^TMCMOS Serial EEPROM

FIGURE 4-2: ACKNOWLEDGE TIMING

5.0 DEVICE ADDRESSING

A control byte is the first byte received following the start condition from the master device (Figure 5-1). The control byte consists

of a 4-bit control code; for the 24xx256 this is set as 1010 binary for read and write operations. The next three bits of the control

byte are the chip select bits (A2, A1, A0). The chip select bits allows the use of up to select which device is accessed. The chip

select bits in the control byte must correspond to the logic levels on the corresponding A2, A1, and A0 pins for the device to

respond. These bits are in effect the three most significant bits of the word address.

The last bit of the control byte defines the operation to be performed. When set to a one a read operation is selected, and when

set to a zero a write operation is selected. The next two bytes received define the address of the first data byte (Figure 5-2).

Because only A14…A0 are used, the upper address bit is a don’t care bit. The upper address bits are transferred first, followed by

the less significant bits.

Following the start condition, the 24xx256 monitors the SDA bus checking the control byte being transmitted. Upon receiving a

1010 code and appropriate device select bits, the salve device outputs and acknowledge signal on the SDA line. Depending on

the state of the

bit, the 24xx256 will select a read or write operation.

FIGURE 5-1: CONTROL BYTE FORMAT

5.1 Contiguous Addressing Across Multiple Devices

The chip select bits A2, A1,A0 can be used to expand the contiguous address space for up to 2 Mbit by adding up to eight

24xx256’s on the same bus. In this case, software can use A0 of the control byte as address bit A15; A1, as address bit A16; and

A2, as address bit A17. It is not possible to read or write across device boundaries.

FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS

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24LC256

256K I²C^TMCMOS Serial EEPROM

6.0 WRITE OPERATIONS

6.1 Byte Write

Following the start condition from the master, the control code (four bits), the chip select (three bits), and the

bit (which is a

logic low) are clocked onto the bus by the master transmitter. This indicates to the addressed slave receiver that the address high

byte will follow after is has generated an acknowledge bit during the ninth clock cycle. Therefore the next byte transmitted by the

master is the high-order byte of the word address and will be written into the address pointer of the 24xx256. The next byte is the

least significant address byte. After receiving another acknowledge signal from the 24xx256, the master device will transmit the

data word to be written into the addressed memory location. The 24xx256 acknowledges again and the master generates a stop

condition. This initiates the internal write cycle, and, during this time, the 24xx256 will not generate acknowledge signals (Figure

6-1). If an attempt is made to write to the array with the WP pin held high, the device will acknowledge the command but no write

cycle will occur, no data will be written, and the device will immediately accept a new command. After a byte write command, the

internal address counter will point to the address location following the one that was just written.

6.2 Page Write

The write control byte, word address, and the first data byte are transmitted to the 24xx256 in the same way as in a byte write. But

instead of generating a stop condition, the master transmits up to 63 additional bytes, which are temperately stored in the on-chip

page buffer and will be written into memory after the master has transmitted a stop condition. After receipt of each word, the six

lower address pointer bits are internally incremented by one. If the master should transmit more than 64 bytes prior to generating

the stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write

operation, once the stop condition is received, an internal write cycle will begin (Figure 6-2). If an attempt is made to write to the

array with the WP pin held high, the device will acknowledge the command but no write cycle will occur, no data will be written,

and the device will immediately accept a now command subject to T_BUF

6.3 Write Protection

The WP pin allows the user to write-protect the entire array (0000-7FFF) when the pin is tied to Vcc. If tied to Vss or left floating,

the write protection is disabled. The WP pin is sampled at the STOP bit for every write command (Figure 1-1) Toggling the WP pin

after the STOP bit will have no effect on the execution of the write cycle.

FIGURE 6-1: BYTE WRITE

FIGURE 6-2: PAGE WRITE

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24LC256

256K I²C^TMCMOS Serial EEPROM

7.0 ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write cycle,

this can be used to determine when the cycle is complete (this

feature can be used to maximize bus throughput.) Once the

stop condition for a write command has been issued from the

master, the device initiates the internally timed write cycle.

ACK polling can be initiated immediately. This involves the

master sending a start condition, followed by the control byte

FIGURE 7-1: ACKNOWLEDGE POLLING FLOW

for a write command(

=0). If the device is still busy with

the write cycle, then no ACK will be returned. If no ACK if

returned, then the start bit and control byte must be resent. If

the cycle is complete, then the device , See Figure 7-1 for flow

diagram.

8.0 READ OPERATION

Read operations are initiated in the same way as write operations with the exception that the

bit of the control byte is set to

one. There are three basic types of read operations: current address read, random read, and sequential read.

8.1 Current Address Read

The 24xx256 contains an address counter that maintains the address of the last word accessed, internally incremented by one.

Therefore, if the previous read access was to address n (n is any legal address), the next current address read operation would

access data from address n+1.

Upon receipt of the control byte with

bit set to one, the 24xx256 issues an acknowledge and transmits the 8-bit data word.

The master will not acknowledge the transfer but does generate a stop condition and the 24xx256 discontinues transmission

(Figure 8-1)

FIGURE 8-1: CURRENT ADDRESS READ

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24LC256

256K I²C^TMCMOS Serial EEPROM

8.2 Random Read

Random read operations allow the master to access any memory location in a random manner. To perform this type of read

operation, first the word address must be set. This is done by sending the word address to the 24xx256 as part of a write

operation (

This terminates the write operation, but not before the internal address pointer is set. Then, the master issues the control byte

again but with the bit set to a one. The 24xx256 will then issue an acknowledge and transmit the 8-bit data word. The

bit set to 0). After the word address is sent, the master generates a start condition following the acknowledge.

master will not acknowledge the transfer but does generate a stop condition which causes the 24xx256 to discontinue

transmission (Figure 8-2). After a random read command, the internal address counter will point to the address location following

the one that was just read.

8.3 Sequential Read

Sequential reads are initiated in the same way was a random read except that after the 24xx256 transmits the first data byte, the

master issues an acknowledge as opposed to the stop condition used in a random read. This acknowledge directs the 24xx256 to

transmit the next sequentially addressed 8-bit word (Figure 8-3). Following the final byte transmitted to the master, the master will

NOT generate an acknowledge but will generate a stop condition. To provide sequential reads, the 24xx256 contains an internal

address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory

contents to be serially read during one operation. The internal address pointer will automatically roll over from address 7FFF to

address 0000 if the master acknowledges the byte received from the array address 7FFF.

FIGURE 8-2: RANDOM READ

FIGURE 8-3: SEQUENTIAL READ

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24LC256

256K I²C^TMCMOS Serial EEPROM

24xx256 PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to factory or the listed sales office.

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24AA256T-EP [ARTSCHIP]

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