DS1743P-100 [ARTSCHIP]
Y2KC Nonvolatile Timekeeping RAM;
| 型号： | DS1743P-100 |
| 厂家： | 
Artschip |
| 描述： | Y2KC Nonvolatile Timekeeping RAM |
| 文件： | 总15页 (文件大小：497K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1743/DS1743P
Y2KC Nonvolatile Timekeeping RAM
FEATURES
PIN ASSIGNMENT
z Integrated NV SRAM, real time clock, crystal, power-fail
control circuit and lithium energy source
z Clock registers are accessed identical to the static RAM.
These registers are resident in the eight top RAM locations.
z Century byte register
z Totally nonvolatile with over 10 year of operation in the
absence of power
z BCD coded century, year, month, date, day, hours, minutes,
and seconds with automatic leap year compensation valid
up to the year 2100
z Battery voltage level indicator flag
z Power-fail write protection allows for ±10% Vcc power
supply tolerance
z Lithium energy source is electrically disconnected to retain
freshness until power is applied for the first time
z DIP Module only
-
Standard JEDEC bytewide 8k x 8 static RAM pinout
z PowerCap ® Module Board only
-
Surface mountable package for direct connection to
PowerCap containing battery and crystal
Replaceable battery (PowerCap)
Power-On Reset Output
Pin for pin compatible with other densities of DS174XP
Timekeeping RAM
-
-
-
ORDERING INFORMATION
PIN DESCRIPTION
A0-A12
-Address Input
-Chip Enable
CE2
-Chip Enable 2 (DIP Module only)
-Output Enable
-Write Enable
Vcc
-Power Supply Input
-Ground
GND
DQ0-DQ7 -Data Input/Output
NC
-No Connection
-Power-On Reset Output
(PowerCap Module board only)
-Crystal Connection
X1,X2
VBAT
-Battery Connection
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1
DS1743/DS1743P
Y2KC Nonvolatile Timekeeping RAM
DESCRIPTION
The DS1743 is a full function, year 2000-compliant (Y2KC), real-time clock/calendar (RTC) and 8k x 8 non-volatile static RAM.
User access to all registers within the DS1743 is accomplished with a bytewide interface as shown in Figure 1. The Real Time
Clock (RTC) information and control bits reside in the eight uppermost RAM locations. The RTC registers contain century, year,
month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the day of the month and leap year
are made automatically. The RTC clock registers are double buffered to avoid access of incorrect data that can occur during clock
update cycles. The double buffered system also prevents time loss as the timekeeping countdown continues unabated by access
to time register data. The DS1743 also contains its own power-fail circuitry, which deselects the device when the Vcc supply is in
an out of tolerance condition. This feature prevents loss of data from unpredictable system operation brought on by low Vcc as
errant access and update cycles are avoided.
PACKAGES
The DS1743 is available in two packages (28-pin DIP and 34-pin PowerCap module). The 28-pin DIP style module integrates the
crystal, lithium energy source, and silicon all in one package. The 34-pin PowerCap Module Board is designed with contacts for
connection to a separate PowerCap (DS9034PCX) that contains the crystal and battery. This design allows the PowerCap to be
mounted on top of the DS1743P after the completion of the surface mount process. Mounting the PowerCap after the surface
mount process prevents damage to the crystal and battery due to the high temperatures required for solder reflow. The PowerCap
is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap are ordered separately and shipped in
separate containers. The part number for the PowerCap is DS9034PCX.
CLOCK OPERATIONS-READING THE CLOCK
While the double buffered register structure reduces the chance of reading incorrect data, internal updates to
the DS1743 clock registers should be halted before clock data is read to prevent reading of data in transition.
However, halting the internal clock register updating process does not affect clock accuracy. Updating is halted
when a 1 is written into the read bit, bit 6 of the century register, see Table 2. As long as a 1 remains in that
position, updating is halted. After a halt is issued, the registers reflect the count,that is day, date, and time that
was current at the moment the halt command was issued. However, the internal clock registers of the
double-buffered system continue to update so that the clock accuracy is not affected by the access of data. All
of the DS1743 registers are updated simultaneously after the internal clock register updating process has been
re-enabled. Updating is within a second after the read bit is written to 0.
The READ bit must be a zero for a minimum of 500 µs to ensure the external registers will be updated.
DS1743 BLOCK DIAGRAM Figure 1
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2
DS1743/DS1743P
Y2KC Nonvolatile Timekeeping RAM
DS1743 TRUTH TABLE Table 1
Vcc
CE2
X
MODE
DQ
POWER
Vcc>VPF
VIH
X
X
X
DESELECT
DESELECT
WRITE
HIGH-Z
HIGH-Z
DATA IN
DATA OUT
HIGH-Z
HIGH-Z
HIGH-Z
STANDBY
STANDBY
ACTIVE
VIL
VIH
VIH
VIH
X
X
X
VIL
VIL
VIL
X
X
VIL
VIH
VIH
X
VIL
VIH
X
READ
ACTIVE
READ
ACTIVE
VSO<VCC<VPF
DESELECT
DESELECT
CMOS STANDBY
DATA RETENTION
MODE
VCC < VSO <VPF
X
X
X
X
SETTING THE CLOCK
As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a 1, like the read bit, halts updates to the
DS1743 registers. The user can then load them with the correct day, date and time data in 24-hour BCD format. Resetting the
write bit to a 0 then transfers those values to the actual clock counters and allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off to minimize current drain
from the battery. The
bit is the MSB (bit 7) of the seconds registers, see Table 2. Setting it to a 1 stops the oscillator.
FREQUENCY TEST BIT
As shown in table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and the oscillator is
running, the LSB of the seconds register will toggle at 512 Hz. When the seconds register is being read, the DQ0 line will toggle at
the 512 Hz frequency as long as conditions for access remain valid (i.e.,
register remain valid and stable).
low,
low,
high, and address for seconds
CLOCK ACCURACY (DIP MODULE)
The DS1743 is guaranteed to keep time accuracy to within ±1 minute per month at 25℃. The RTC is calibrated at the factory by
ARTSCHIP Semiconductor using nonvolatile tuning elements, and does not require additional For this reason, methods of field
clock calibration are not available and not necessary. Clock accuracy is also effected by the electrical environment and caution
should be taken to place the RTC in the lowest level EMI section of the PCB layout. For additional information please see
application note 58.
CLOCK ACCURACY (POWERCAP MODULE)
The DS1743 and DS9034PCX are each individually tested for accuracy. Once mounted together, the module will typically keep
time accuracy to within ±1.53 minutes per month (35 ppm) at 25℃. Clock accuracy is also effected by the electrical environment
and caution should be taken to place the RTC in the lowest level EMI section of the PCB layout. For additional information please
see application note 58.
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3
DS1743/DS1743P
Y2KC Nonvolatile Timekeeping RAM
DS1743 REGISTER MAP Table 2
ADDRESS
DATA
FUNCTION/RANGE
B7
B6
B5
B4
B3
B2
B1
B0
1FFF
1FFE
1FFD
1FFC
1FFB
1FFA
1FF9
1FF8
10 Year
YEAR
MONTH
DATE
X
YEAR
00-99
01-12
01-31
01-07
00-23
00-59
00-59
00-39
X
X
X
10Mo
MONTH
DATE
X
X
10 Date
X
BF
X
FT
X
X
DAY
DAY
10 HOUR
HOUR
HOUR
X
10 MINUTES
10 MINUTES
MINUTES
SECONDS
MINUTES
SECONDS
CONTROL
W
R
10 CENTURY CENTURY
=STOP BIT
R=READ BIT
FT=FREQUENCY TEST
BF=BATTERY FLAG
W=WRITE BIT
X=SEE NOTE BELOW
NOTE:
All indicate “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1743 is in the read mode whenever
The device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid data will be available
at the DQ pins within tAA after the last address input is stable, providing that the , and access times and states are
satisfied. If , or access times and states are not met, valid data will be available at the latter of chip enable access (tCEA
or at output enable access time (tCEA). The state of the data input/output pins (DQ) is controlled by , and . If the outputs are
activated before tAA, the data lines are driven to an intermediate state until tAA. If the address inputs are changed while , and
remain valid, output data will remain valid for output data hold time (tOH) but will then go indeterminate until the next address
access.
(output enable) is low,
(write enable) is high, and
(chip enable) is low.
)
WRITING DATA TO RAM OR CLOCK
The DS1743 is in the write mode whenever
, and
are in their active state. The start of a write is referenced to the latter
or must return inactive for a
minimum of tWR prior to the initiation of another read or write cycle. Data in must be valid tDS prior to the end of write and remain
occurring transition of
, on
. The addresses must be held valid throughout the cycle.
valid for tDH afterward. In a typical application, the
signal will be high during a write cycle. However,
can be active
provided that care is taken with the data bus to avoid bus contention. If
become active with read data defined by the address inputs. A low transition on
goes active.
is low prior to
transitioning low the data bus can
will then disable the outputs tWEZ after
DATA RETENTION MODE
The 5-volt device is fully accessible and data can be written or read only when Vcc is greater than VPF. However, when Vcc is
below the power fail point, VPF, (point at which write protection occurs) the internal clock register and SRAM are blocked from any
access. At this time (PowerCap only) the power fail reset output signal (
) is driven active and will remain active until Vcc
returns to nominal levels.The 3.3-volt device is fully accessible and data can be written or read only when Vcc is greater than VPF.
When Vcc falls below the power fail point, VPF, access to the device is inhibited. At this time the power fail reset output signal (
is driven active and will remain active until Vcc returns to nominal levels. If VPF is less than VSO, the device power is switched from
Vcc to the backup supply (VBAT) when Vcc drops below VPF. If VPF is greater than VSO, the device power is switched from Vcc to
the backup supply (VBAT) when Vcc drops below Vso. RTC operation and SRAM data are maintained from the battery until Vcc is
)
returned to nominal levels. The
(PowerCap only) signal is an open drain output and requires a pull up. Except for the
,
all control, data, and address signals must be powered down when Vcc is powered down.
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DS1743/DS1743P
Y2KC Nonvolatile Timekeeping RAM
BATTERY LONGEVITY
The DS1743 has a lithium power source that is designed to provide energy for clock activity and clock and RAM data retention
when the Vcc supply is not present. The capability of this internal power supply is sufficient to power the DS1743 continuously for
the life of the equipment in which it is installed. For specification purposes, the life expectancy is 10 years at 25℃ with the internal
clock oscillator running in the absence of Vcc power. Each DS1743 is shipped from ARTSCHIP Semiconductor with its lithium
energy source disconnected, guaranteeing full energy capacity. When Vcc is first applied at a level greater than VPF, the lithium
energy source is enabled for battery backup operation. Actual life expectancy of the DS1743 will be much longer than 10 years
since no lithium battery energy is consumed when Vcc is present.
BATTERY MONITOR
The DS1743 constantly monitors the battery voltage of the internal battery. The battery Flag bit (bit 7) of the day register is used to
indicate the voltage level range of the battery. This bit is not writable and should always be a 1 when read. If a 0 is ever present,
an exhausted lithium energy source is indicated and both the contents of the RTC and RAM are questionable.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
-0.3V to +6.0V
0℃ to 70℃
Storage Temperature
-40℃ to +85℃
Soldering Temperature
See J-STD-020A Specification (See Note 8)
*This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of
time may affect reliability.
OPERATING RANGE
Range
Temperature
Vcc
Commercial
0℃ to +70℃
3.3V ±10% or 5V ±10%
RECOMMENDED DC OPERATING CONDITIONS
(Over the Operating Range)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Logic 1 Voltage All Inputs
Vcc=5V ±10%
VIH
2.2
Vcc+0.3V
V
1
VIH
2.0
Vcc+0.3V
V
1
Vcc=3.3V ±10%
Logic 0 Voltage All Inputs
Vcc =5V ±10%
VIL
VIL
-0.3
-0.3
0.8
0.6
V
V
1
1
Vcc =3.3V ±10%
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DS1743/DS1743P
Y2KC Nonvolatile Timekeeping RAM
DC ELECTRICAL CHARACTERISTICS
(Over the Operating Range; Vcc=5.0V±10% )
PARAMETER
SYMBOL
Icc
MIN
TYP
15
1
MAX
50
UNITS
mA
NOTES
2,3
Active Supply Current
TTL Standby Current
Icc1
3
mA
2,3
(
=VIH, CE2=VIL)
CMOS Standby Current
≥Vcc –0.2V, CE2 = GND +0.2V)
ICC2
1
3
mA
2,3
(
Input Leakage Current (any input)
Output Leakage Current (and input)
Output Logic 1 Voltage (IOUT=-1.0mA)
Output Logic 0 Voltage (IOUT=2.1mA)
Write Protection Voltage
IIL
-1
+1
+1
µA
µA
IOL
-1
VOH
VOL1
VPF
VSO
2,4
1
0.4
1
4.25
4.50
V
1
Battery Switch-over Voltage
VBAT
1,4
DC ELECTRICAL CHARACTERISTICS
(Over the Operating Range: Vcc=3.3V ±10%)
PARAMETER
SYMBOL
ICC
MIN
TYP
10
MAX
30
2
UNITS
mA
NOTES
2,3
Active Supply Current
TTL Standby Current (
CMOS Standby Current
= VIH)
ICC1
0.7
0.7
mA
2,3
ICC2
2
mA
2,3
(
≥ Vcc –0.2V, CE2=GND+0.2V)
Input Leakage Current (any input)
Output Leakage current (any output)
Output Logic 1 Voltage (IOUT=-1.0 mA)
Output Logic 0 Voltage (IOUT=2.1mA)
Write Protection Voltage
IIL
-1
+1
+1
µA
µA
IOL
-1
VOH
VOL1
VPF
VSO
2.4
1
0.4
1
2.80
2.97
V
V
1
Battery Switch-over Voltage
VBAT
1,4
Or VPF
READ CYCLE, AC CHARACTERISTICS
(Over the Operating Range; Vcc =5.0V ±10%)
70 ns access 100ns access
PARAMETER
SYMBOL
UNITS
ns
NOTES
MIN
MAX
MIN
MAX
Read Cycle Time
Address Access Time
tRC
70
100
5
5
5
5
5
5
5
5
5
5
tAA
70
100
ns
tCEL
tCEA
tCE2A
tCEZ
tOEL
tOEA
tOEZ
tOH
5
5
ns
to CE2 to DQ Low-Z
Access Time
70
80
25
100
105
35
ns
CE2 Access Time
ns
ns
and CE2 Data Off time
to DQ Low-Z
5
5
6
5
5
ns
35
25
55
35
ns
Access Time
ns
Data off Time
Output Hold from Address
ns
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DS1743/DS1743P
Y2KC Nonvolatile Timekeeping RAM
READ CYCLE, AC CHARACTERISTIC
(Over the Operating Range; Vcc=3.3V ±10%)
120 ns access
150 ns access
PARAMETER
SYMBOL
UNITS
ns
NOTES
MIN
MAX
MIN
MAX
Read Cycle Time
Address Access Time
tRC
120
150
5
5
5
5
5
5
5
5
5
tAA
120
150
ns
tCEL
tCEA
tCEZ
tOEL
tOEA
tOEZ
tOH
5
5
5
5
5
5
ns
and CE2 Low to DQ Low-Z
and CE2 Access time
and CE2 Data Off time
Low to DQ Low-Z
120
40
150
50
ns
ns
ns
100
35
130
35
ns
Access Time
ns
Data Off Time
Output Hold from Address
ns
READ CYCLE TIMING DIAGRAM
SEE NOTES
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DS1743/DS1743P
Y2KC Nonvolatile Timekeeping RAM
WRITE CYCLE, AC CHARACTERISTICS
(Over the Operating Range; Vcc=5.0V ±10%)
70 ns access
100 ns access
PARAMETER
SYMBOL
tWC
tAS
UNITS NOTES
MIN
70
0
MAX
MIN
100
0
MAX
Write Cycle Time
Address Setup Time
Pulse Width
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
5
5
5
5
5
5
5
5
5
tWEW
tCEW
tCE2W
tDS
50
60
65
30
0
70
75
Pulse Width
CE2 Pulse Width
Data Setup Time
Data Hold time
85
25
40
0
tDH
Address Hold Time
Data Off Time
tAH
5
5
tWEZ
tWR
35
Write Recovery Time
5
5
WRITE CYCLE, AC CHARACTERISTICS
(Over the operating Range; Vcc =3.3V ±10%)
120 ns access 150 ns access
PARAMETER
SYMBOL
tWC
tAS
UNITS NOTES
MIN
120
0
MAX
MIN
150
0
MAX
Write Cycle Time
Address Setup Time
Pulse Width
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
5
5
5
5
5
5
5
5
tWEW
tCEW
tDS
100
110
80
0
130
140
90
0
and CE2 Pulse Width
Data Setup Time
Data Hold Time
tDH
Address Hold time
Data Off Time
tAH
0
0
tWEZ
tWR
40
50
Write Recovery Time
10
10
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DS1743/DS1743P
Y2KC Nonvolatile Timekeeping RAM
WRITE CYCLE TIMING, WRITE ENABLE CONTROLLED (SEE NOTE 5)
WRITE CYCLE TIMING,
, CE2 CONTROLLED (SEE NOTE 5)
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DS1743/DS1743P
Y2KC Nonvolatile Timekeeping RAM
POWER-UP/DOWN CHARACTERISTICS
(Over the Operating Range; Vcc=5.0V ±10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
or
at VIH, CE2 at VIL,
tPD
0
µs
Before Power-Down
Vcc Fall Time: VPF (MAX) to
VPF(Min)
tF
300
µs
Vcc Fall time : VPF (MIN) to Vso tFB
10
0
µs
µs
Vcc Rise Time: VPF (MIN) to
VPF(MAX)
tR
Power-up Recover Time
Expected Data Retention Time
(Oscillator On)
tREC
tDR
35
ms
10
years
6,7
POWER-UP/POWER-DOWN TIMING 5-VOLT DEVICE
POWER-UP/DOWN CHARACTERISTICS
(Over the Operating Range; Vcc=3.3V ±10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
µs
µs
µs
tPD
0
or
at VIH, Before
Power-Down
Vcc Fall Time: VPF(MAX) to
VPF(Min)
tF
300
0
Vcc Rise Time: VPF(MIN) to
VPF(MAX)
tR
tREC
35
ms
VPF to
High
Expected Data Retention Time tDR
(Oscillator On)
10
years
6,7
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10
DS1743/DS1743P
Y2KC Nonvolatile Timekeeping RAM
POWER-UP/DOWN WAVEFORM TIMING 3.3-VOLT DEVICE
CAPACITANCE
(tA=25℃)
UNITS
pF
PARAMETER
SYMBOL
CIN
MIN
TYP
MAX
7
NOTES
Capacitance on all input pins
Capacitance on all output pins
CO
10
pF
AC TEST CONDITIONS
Output Load:
100pF +1TTL Gate
Input Pulse Levels:
0.0 to 3.0V
Timing Measurement Reference Levels:
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5ns
NOTE:
1. Voltages are referenced to ground.
2. Typical values are at 25℃ and nominal supplies.
3. Outputs are open.
4. Battery switchover occurs at the lower of either the battery terminal voltage or VPF.
5. The CE2 control signal functions exactly the same as the
are opposite.
signal except that the logic levels for active and inactive levels
6. Data retention time is at 25℃.
7. Each DS1743 has a built-in switch that disconnects the lithium source until Vcc is first applied by the user. The expected t DR
is defined for DIP modules as a cumulative time in the absence of Vcc starting from the time power is first applied by the user.
8. Real-Time Clock Modules (DIP) can be successfully processed through conventional wave-soldering techniques as long as
temperatures as long as temperature exposure to the lithium energy source contained within does not exceed +85℃.
Post-solder cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used.
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11
DS1743/DS1743P
Y2KC Nonvolatile Timekeeping RAM
DS1743 28-PIN PACKAGE
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12
DS1743/DS1743P
Y2KC Nonvolatile Timekeeping RAM
DS1743P
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13
DS1743/DS1743P
Y2KC Nonvolatile Timekeeping RAM
DS1743P WITH DS9034PCX ATTACHED
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DS1743/DS1743P
Y2KC Nonvolatile Timekeeping RAM
RECOMMENDED POWERCAP MODULE LAND PATTERN
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