5962-9760702MYA [ATMEL]
RISC Microprocessor, 32-Bit, 33MHz, CMOS, CQFP240, CERAMIC, LCC-240;
| 型号： | 5962-9760702MYA |
| 厂家： | 
ATMEL |
| 描述： | RISC Microprocessor, 32-Bit, 33MHz, CMOS, CQFP240, CERAMIC, LCC-240 时钟 外围集成电路 |
| 文件： | 总83页 (文件大小：999K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• CPU32+ Processor (4.5 MIPS at 25 MHz)
– 32-bit Version of the CPU32 Core (Fully Compatible with the CPU32)
– Background Debug Mode
– Byte-misaligned Addressing
• Up to 32-bit Data Bus (Dynamic Bus Sizing for 8 and 16 Bits)
• Up to 32 Address Lines (At Least 28 Always Available)
• Complete Static Design (0 - 25 MHz Operation)
• Slave Mode to Disable CPU32+ (Allows Use with External Processors)
– Multiple QUICCs Can Share One System Bus (One Master)
– TS68040 Companion Mode Allows QUICC to be a TS68040 Companion Chip and
Intelligent Peripheral (22 MIPS at 25 MHz)
– Peripheral Device of TSPC603e (see DC415/D note)
• Four General-purpose Timers
32-bit Quad
Integrated
Communication
Controller
– Superset of MC68302 Timers
– Four 16-bit Timers or Two 32-bit Timers
– Gate Mode Can Enable/Disable Counting
• Two Independent DMAs (IDMAs)
TS68EN360
• System Integration Module (SIM60)
• Communications Processor Module (CPM)
• Four Baud Rate Generators
• Four SCCs (Ethernet/IEEE 802.3 Optional on SCC1-Full 10 Mbps Support)
• Two SMC
• VCC = +5V ± 5%
• fmax = 25 MHz and 33 MHz
• Military Temperature Range: -55°C < TC < +125°C
• PD = 1.4W at 25 MHz; 5.25V
2W at 33 MHz; 5.25V
Description
The TS68EN360 QUad Integrated Communication Controller (QUICC™) is a versatile
one-chip integrated microprocessor and peripheral combination that can be used in a
variety of controller applications. It particularly excels in communications activities.
The QUICC (pronounced “quick”) can be described as a next-generation TS68302
with higher performance in all areas of device operation, increased flexibility, major
extensions in capability, and higher integration. The term “quad” comes from the fact
that there are four serial communications controllers (SCCs) on the device; however,
there are actually seven serial channels: four SCCs, two serial management control-
lers (SMCs), and one serial peripheral interface (SPI).
Screening/Quality
This product is manufactured in full compliance with:
• QML (class Q)
• or according to Atmel standards
2113B–HIREL–06/05
R suffix
PGA 241
A suffix
CERQUAD 240
Ceramic Pin Grid Array Cavity Up
Ceramic Leaded Chip Carrier Cavity Down
1. Introduction
1.1
QUICC Architecture Overview
The QUICC is 32-bit controller that is an extension of other members of the TS68300 family.
Like other members of the TS68300 family, the QUICC incorporates the intermodule bus (IMB).
The TS68302 is an exception, having an 68000 bus on chip. The IMB provides a common inter-
face for all modules of the TS68300 family, which allows the development of new devices more
quickly by using the library of existing modules. Although the IMB definition always included an
option for an on-chip 32-bit bus, the QUICC is the first device to implement this option.
The QUICC is comprised of three modules: the CPU32+ core, the SIM60, and the CPM. Each
module utilizes the 32-bit IMB. The TS68EN360 QUICC block diagram is shown in Figure 1-1.
Figure 1-1. QUICC Block Diagram
SIM 60
JTAG
SYSTEM
PROTECTION
BREAKPOINT
LOGIC
PERIODIC
TIMER
CPU32+
CORE
CLOCK
GENERATION
DRAM
CONTROLLER
AND
OTHER
FEATURES
CHIP SELECTS
SYSTEM
I/F
EXTERNAL
BUS
IMB (32 BIT)
INTERFACE
CPM
COMMUNICATIONS PROCESSOR
2.5-KBYTE
DUAL-PORT
RAM
RISC
CONTROLLER
FOUR
GENERAL-
PURPOSE
TIMERS
TWO
IDMAs
FOURTEEN SERIAL
DMAs
INTERRUPT
CONTROLLER
SEVEN
SERIAL
CHANNELS
OTHER
FEATURES
TIMER SLOT
ASSIGNER
2
TS68EN360
2113B–HIREL–06/05
TS68EN360
2. Pin Assignments
Figure 2-1. 241-lead Pin Grid Array (PGA)
T
S
R
Q
P
N
M
L
PA15 PA12 PA9 PA6 PA3 PA2 PB17 PB15 PB12 PB11 PB8 PB5 PB2 PC11 PC9 PC6 PC5 PC2
D2
D4
D0 PA13 PA10 PA7 PA5 PA1 PB16 PB13 PB10 PB7 PB4 PB1 PC10 PC7 PC3 PC1 IRQ2
D3
D6
D9
D1 PA14 PA11 PA8 PA4 PA0 PB14 PB9 PB6 PB3 PB0 PC8 PC4 PC0 IRQ3 IRQ1
D7
D5
D8
GND GND GND Vcc
GND Vcc GND
Vcc GND GND Vcc
NC
Vcc GND GND GND IRQ5 BERR RESETS
Vcc GND GND HALT RMC PERR
GND GND AVEC TDO TMS
D10
D13 D12
D11 GND GND
D16 D15 D14 GND
Vcc
TD1 TCK RESETH
D19 D18 D17
Vcc
GND TRST BKPT IRQ6
Vcc IRQ4 BGACK BG
K
J
TS68EN360
CLKO2 Vcc GND Vccclk GNDclk
CLKO1 D20 D22 GND Vcc
D21 D23 D25 GND
Vcc
(BOTTOM VIEW)
GND GND IFETCH NC1
BR
H
G
F
GNDs2 NC2 BCLRO OE
Vcc IPIPE0 AS IPIPE1
D24 D26 D28
Vcc
D27 D29 D31 GND GND
Vcc GND PRTY2 PRTY1 PRTY0
Vcc GNDs1 Vcc NC3 DSACK1 PRTY3
E
D
C
B
A
D30 FC3 FC0 A31 Vccsyn GNDsyn
FC2 FC1 A30 XFC Vcc GND GND Vcc
GND
Vcc GND GND GND GND Vcc GND CAS0 R/W DSACK0
SIZ1 A29 EXTAL MODCK1 A27
SIZ0 A28 MODCK0 GND A25
A23
A22
A20
A19
A17
A16
A14
A13
A8
A4
A7
A0
A5
CS7 CS4 CS1 CAS3 FREEZE DS
A10
A1
IRQ7 CS5 CS2 CAS2 CAS1
XTAL NC4 A26
A24
5
A21
6
A18
7
A15
8
A12
9
A11
10
A9
11
A6
12
A3
13
A2
14
TRIS CS6 CS3 CS0
15 16 17 18
1
2
3
4
Note:
Pin P9 “NC” is for guide purposes only.
3
2113B–HIREL–06/05
Figure 2-2. 240-lead Cerquad
180
181
170
160
150
140
130
121
120
GNDs1
CAS3
CAS2
Vcc
CAS1
GND
A28
A29
GND
A30
A31
Vcc
CAS0
FREEZE
DS
SIZ0
SIZ1
FC0
GND
FC1
FC2
FC3
Vcc
GND
D31
D30
D29
GND
D28
D27
D26
Vcc
D25
D24
D23
GND
D22
D21
D20
CLKO1
Vccclk
GNDclk
CLKO2
D19
D18
D17
GND
D16
D15
Vcc
D14
D13
D12
GND
D11
D10
D9
D8
D7
GND
D6
D5
Vcc
D4
D3
D2
GND
D1
D0
GND
R/W
NC3
Vcc
190
200
210
220
230
240
110
100
90
DSACK0
GND
DSACK1
GND
PRTY3
PRTY2
GND
Vcc
PRTY1
PRTY0
IPIPE0
AS
GNDs2
IPIPE1
Vcc
NC2
BCLRO
GND
OE
IFETCH
NC1
BR
Vcc
GND
BG
BGACK
Vcc
IRQ4
IRQ6
GND
BKPT
RESETH
TRST
TCK
TMS
TDI
TDO
PERR
GND
AVEC
RMC
Vcc
RESETS
HALT
GND
TS68EN360
(TOP VIEW)
80
70
61
PIN ONE INDICATOR
BERR
IRQ1
1
10
20
30
40
50
60
4
TS68EN360
2113B–HIREL–06/05
TS68EN360
3. Signal Description
3.1
Functional Signal Group
Figure 3-1. QUICC Functional Signal Groups
ADDRESS BUS
Aꢀ7 AE
A31 Aꢀ28/WE /W3
FCꢀ FCE8TMꢀ TME
FC38TTE
PORT A
DATA BUS
D31 D1ꢁ
D15 DE
RXD18PAE
TXD18PA1
RXDꢀ8PAꢀ
TXDꢀ8PA3
PRTY1 PRTYꢀ8IOUT1 IOUTꢀ
PRTYꢀ8IOUTE8RQOUT
L1TXDB8RXD38PA4
L1RXDB8TXD38PA5
PRTY381ꢁBM
BUS CONTROL
SIZE
L1TXDA8RXD48PAꢁ
L1RXDA8TXD48PA7
SIZ1
DSACKE8TBI
TIMERs/SCCs/SIs/CLOCKs/BRG
TIN18L1RCLKA8BRGO18CLK18PA2
DSACK18TA
R8/
BRGCLK18TOUT18CLKꢀ8PA9
AS
TINꢀ8L1TCLKA8BRGOꢀ8CLK38PA1E
TOUTꢀ8CLK48PA11
DS8TT1
OW8AMUX
TIN38BRGO38CLK58PA1ꢀ
BRGCLKꢀ8L1RCLKB8TOUT38CLKꢁ8PA13
TIN48BRGO48CLK78PA14
BUS ARBITRATION
RMC8CONFIGE8LOCK
L1TCLKB8TOUT48CLK28PA15
BR
BG
PORT B (PIP)
BGACK8BB
RRJCT18SPISWL8PBE
RSTRTꢀ8SPICLK8PB1
BCLRO8CONFIG18RASꢀDD
RRJCTꢀ8SPIMOSI(SPITXD)8PBꢀ
BRGO48SPIMISO(SPIRXD)8PB3
DRWQ18BRGO18PB4
SYSTEM CONTROL
RWSWTH
RWSWTS
QUICC
TSꢁ23ꢁE
ꢀ4E PINS
DACK18BRGOꢀ8PB5
HALT
BWRR8TWA
DONW18SMTXD18PBꢁ
DONWꢀ8SMRXD18PB7
DRWQꢀ8SMSYN18PB2
DACKꢀ8SMSYNꢀ8PB9
PWRR
INTERRUPT CONTROL
IRQ18OUTE8RQOUT
L1CLKOB8SMTXDꢀ8PB1E
L1CLKOA8SMRXDꢀ8PB11
L1ST18RTS18PB1ꢀ
IRQ48OUT1
IRQꢁ8OUTꢀ
IRQꢀ636567
L1STꢀ8RTSꢀ8PB13
AVWC8IACK58AVWCO
L1ST38L1RQB8RTS38PB14
L1ST48L1RQA8RTS48PB15
STRBO8BRGO38PB1ꢁ
STRBI8RSTRT18PB17
MEMORY CONTROLLER
CSꢁ CSE8RASꢁ RASE
CS8RAS78IACK7
CAS3 CASE8IACKꢁ636ꢀ61
PORT C (INTERRUPT PARALLEL I/O)
L1ST18RTS18PCE
TEST
L1STꢀ8RTSꢀ8PC1
TRIS8TS
L1ST38L1RQB8RTS38PCꢀ
L1ST48L1RQA8RTS48PC3
CTS18PC4
BKPT8BKPTE8DSCLK
FRWWZW8CONFIGꢀ8MBARW
IPIPW18RAS1DD8BCLRI
IPIPWE8BADDꢀ8DSO
TGATW18CD18PC5
CTSꢀ8PCꢁ
IFWTCH8BADD38DSI
TGATWꢀ8CDꢀ8PC7
TCK
TMS
TDI
SDACKꢀ8L1TSYNCB8CTS38PC2
L1RSYNCB8CD38PC9
SDACK18L1TSYNCA8CTS48PC1E
L1RSYNCA8CD48PC11
TDO
TRST
CLOCK
XTAL
WXTAL
XFC
MODCK1 MODCKE
CLKOꢀ CLKO1
5
2113B–HIREL–06/05
3.2
Signal Index
Table 1. System Bus Signal Index (Normal Operation)
Group
Signal Name
Mnemonic
Function
Address Bus
A27-A0
Lower 27 bits of address bus. (I/O)(1)
Address Bus/Byte Write
Enables
A31-A28
WE3-WE0
Upper four bits of address bus (I/O), or byte write enable
signals (O)(1) for accesses to external memory or peripherals.
Address
Identifies the processor state and the address space of the
current bus cycle. (I/O)
Function Codes
Data Bus 31 - 16
FC3-FC0
D31-D16
Upper 16-bit data bus used to transfer byte or word data.
Used in 16-bit bus mode. (I/O)
Data
Lower 16-bit data bus used to transfer 3-byte or long-word
data. (I/O)
Not used in 16-bit bus mode.
Data Bus 15 - 0
Parity 2 - 0
D15-D0
Parity signals for byte writes/reads from/to external memory
module. (I/O)
PRTY2-PRTY0
Parity
Parity signals for byte writes/reads from/to external memory
module or defines 16-bit bus mode. (I/O)
Parity 3/16BM
Parity Error
PRTY3/16BM
PERR
Indicates a parity error during a read cycle. (O)
Chip Select
Row Address Select 7
Interrupt Acknowledge 7
CS
RAS7
IACK7
Enables peripherals or DRAMs at programmed addresses (O)
or interrupt level 7 acknowledge line. (O)
Memory
Controller
Chip Select 6-0
Row Address Select 6-0
CS6-CS0
RAS6-RAS0
Enables peripherals or DRAMs at programmed addresses.
(O)
Column Address Select
3 - 0/Interrupt
Acknowledge 1, 2, 3, 6
CAS3-CAS0/
IACK6,3,2,1
DRAM column address select or interrupt level acknowledge
lines. (O)
Indicates that an external device requires bus mastership.
(I)(1)
Bus Request
BR
BG
Indicates that the current bus cycle is complete and the
QUICC has relinquished the bus. (O)
Bus Grant
Indicates that an external device has assumed bus
mastership. (I)
Bus Grand Acknowledge
BGACK
Bus Arbitration
Identifies the bus cycle as part of an indivisible
read-modify-write operation (I/O) or initial QUICC
configuration select. (I)
Read-Modify-Write Cycle
Initial Configuration 0
RMC
CONFIG0
Bus Clear Out/Initial
Configuration 1/Row
Address Select 2
Double-Drive
Indicates that an internal device requires the external bus
(Open-Drain O) or initial QUICC configuration select (I) or row
address select 2 double-drive output. (O)
BCLRO/CONFIG1/
RAS2DD
6
TS68EN360
2113B–HIREL–06/05
TS68EN360
Table 1. System Bus Signal Index (Normal Operation) (Continued)
Group
Signal Name
Mnemonic
Function
Provides asynchronous data transfer acknowledgement and
dynamic bus sizing (open-drain I/O but driven high before
three-stated)
Data and Size
Acknowledge
DSACK1 - DSACK0
Address Strobe
Data Strobe
AS
DS
Indicates that a valid address is on the address bus. (I/O)
During a read cycle, DS indicates that an external device
should place valid data on the data bus. During a write cycle,
DS indicates that valid data is on the data bus. (I/O)
Bus Control
Indicates the number of bytes remaining to be transferred for
this cycle. (I/O)
Size
SIZ1-SIZ0
R/W
Read/Write
Indicates the direction of data transfer on the bus. (I/O)
Active during a read cycle indicates that an external device
should place valid data on the data bus (O) or provides a
strobe for external address multiplexing in DRAM accesses if
internal multiplexing is not used. (O)
Output Enable Address
Multiplex
OE/AMUX
Interrupt Request
Level 7-1
Provides external interrupt requests to the CPU32+ at priority
levels 7-1. (I)
IRQ7-IRQ1
Interrupt
Control
Autovector/Interrupt
Acknowledge 5
Autovector request during an interrupt acknowledge cycle
(open-drain I/O) or interrupt level 5 acknowledge line. (O)
AVEC/IACK5
Soft Reset
Hard Reset
Halt
RESETS
RESETH
HALT
Soft system reset. (open-drain I/O)
Hard system reset. (open-drain I/O)
System
Control
Suspends external bus activity. (open-drain I/O)
Indicates an erroneous bus operation is being attempted.
(open-drain I/O)
Bus Error
BERR
System Clock Out 1
System Clock Out 2
CLKO1
CLKO2
Internal system clock output 1. (O)
Internal system clock output 2 - normally 2x CLKO1. (O)
Connections for an external crystal to the internal oscillator
circuit. EXTAL (I), XTAL (O)
Crystal Oscillator
EXTAL, XTAL
XFC
Connection pin for an external capacitor to filter the circuit of
the PLL. (I)
External Filter Capacitor
Clock Mode Select 1-0
Selects the source of the internal system clock. (I) THESE
PINS SHOULD NOT BE SET TO 00
MODCK1-MODCK0
Indicates when the CPU32+ is performing an instruction word
prefetch (O) or input to the CPU32+ background debug mode.
(I)
Instruction Fetch/
Development Serial Input
IFETCH/DSI
IPIPE0/DSO
Clock and Test
Instruction Pipe 0/
Development Serial
Output
Used to track movement of words through the instruction
pipeline (O) or output from the CPU32+ background debug
mode. (O)
Instruction Pipe 1/Row
Address Select 1
Double-Drive
Used to track movement of words through the instruction
pipeline (O), or a row address select 1 “double-drive” output
(O)
IPIPE1/RAS1DD
Breakpoint/Development
Serial Clock
Signals a hardware breakpoint to the QUICC (open-drain I/O),
or clock signal for CPU32+ background debug mode (I)
BKPT/DSCLK
Freeze/Initial
Configuration 2
Indicates that the CPU32+ has acknowledged a breakpoint
(O), or initial QUICC configuration select (I)
FREEZE/CONFIG2
7
2113B–HIREL–06/05
Table 1. System Bus Signal Index (Normal Operation) (Continued)
Group
Signal Name
Mnemonic
Function
Used to three-state all pins if QUICC is configured as a
master. Always Sampled except during system reset. (I)
Three-State
TRIS
Test Clock
TCK
TMS
Provides a clock for Scan test logic. (I)
Clock and Test
(Cont’d)
Test Mode Select
Test Data In
Controls test mode operations. (I)
TDI
Serial test instructions and test data signal. (I)
Serial test instructions and test data signal. (O)
Provides an asynchronous reset to the test controller. (I)
Power supply to the PLL of the clock synthesizer
Test Data Out
Test Reset
TDO
TRST
VCCSYN
Clock Synthesizer Power
Clock Synthesizer
Ground
GNDSYN
Ground supply to the PLL of the clock synthesizer
Clock Out Power
Clock Out Ground
VCCCLK
GNDCLK
Power supply to clock out pins
Ground supply to clock out pins
Power
Special ground for fast AC timing on certain system bus
signals
Special Ground 1
Special Ground 2
GNDS1
GNDS2
Special ground for fast AC timing on certain system bus
signals
System Power Supply
and Return
VCC, GND
NC4-NC1
Power supply and return to the QUICC
Four no-connect pins
--
No Connect
Note:
1. I denotes input, O denotes output and I/O is input/output.
8
TS68EN360
2113B–HIREL–06/05
TS68EN360
Table 3-1.
Group
Peripherals Signal Index
Signal Name
Mnemonic
RXD4-RXD1
TXD4-TXD1
Function
Receive Data
Serial receive data input to the SCCs. (I)
Transmit Data
Serial transmit data output from the SCCs. (O)
Request to send outputs indicate that the SCC is ready to
transmit data. (O)
Request to Send
Clear to Send
Carrier Detect
RTS4-RTS1
CTS4-CTS1
CD4-CD1
Clear to send inputs indicate to the SCC that data
transmission may begin. (I)
Carrier detect inputs indicate that the SCC should begin
reception of data. (I)
SCC
This output from SCC1 identifies the start of a receive frame.
Can be used by an Ethernet CAM to perform address
matching. (O)
Receive Start
RSTRT1
RRJCT1
This input to SCC1 allows a CAM to reject the current
Ethernet frame after it determines the frame address did not
match. (I)
Receive Reject
Input clocks to the SCCs, SCMs, SI, and the baud rate
generators. (I)
Clocks
CLK8-CLK1
DREQ2-DREQ1
DACK2-DACK1
DONE2-DONE1
TGATE2-TGATE1
TIN4-TIN1
A request (input) to an IDMA channel to start an IDMA
transfer. (I)
DMA Request
DMA Acknowledge
DMA Done
An acknowledgement (output) by the IDMA that an IDMA
transfer is in progress. (O)
IDMA
A bidirectional signal that indicates the last IDMA transfer in
a block of data. (I/O)
An input to a timer that enables/disables the counting
function. (I)
Timer Gate
Time reference input to the timer that allows it to function as
a counter. (I)
TIMER
Timer Input
Output waveform (pulse or toggle) from the timer as a result
of a reference value being reached. (O)
Timer Output
SPI Master In Slave Out
SPI Master Out Slave In
SPI Clock
TOUT4-TOUT1
SPIMISO
Serial data input to the SPI master (I); serial data output from
an SPI slave. (O)
Serial data output from the SPI master (O); serial data input
to an SPI slave. (I)
SPIMOSI
SPI
Output clock from the SPI master (O); input clock to the SPI
slave. (I)
SPICLK
SPI Select
SPISEL
SPI slave select input. (I)
SMC Receive Data
SMC Transmit Data
SMC Sync
SMRXD2-SMRXD1
SMTXD2-SMTXD1
SMSYN2-SMSYN1
Serial data input to the SMCs. (I)
Serial data output from the SMCs. (O)
SMC synchronization signal. (I)
SMC
9
2113B–HIREL–06/05
Table 3-1.
Group
Peripherals Signal Index (Continued)
Signal Name
Mnemonic
Function
Serial input to the time division multiplexed (TDM) channel A
or channel B
SI Receive Data
L1RXDA, L1RXDB
L1TXDA, L1TXDB
SI Transmit Data
SI Receive Clock
SI Transmit Clock
Serial output from the TDM channel A or channel B
L1RCLKA, L1RCLKB Input receive clock to TDM channel A or channel B
L1TCLKA, L1TCLKB
Input transmit clock to TDM channel A or channel B
L1TSYNCA,
L1TSYNCB
Input transmit data sync signal to TDM channel A or
channel B
SI Transmit Sync Signals
SI Receive Sync Signals
IDL Interface Request
SI Output Clock
SI
L1RSYNCA,
L1RSYNCB
Input receive data sync signal to TDM channel A or
channel B
IDL interface request to transmit on the D channel. Output
from the SI
L1RQA, L1RQB
Output serial data rate clock. Can output a data rate clock
when the input clock is 2x the data rate
L1CLKOA, L1CLKOB
Serial data strobe outputs can be used to gate clocks to
external devices that do not have a built-in time slot assigner
(TSA)
SI Data Strobes
L1ST4-L1ST1
Baud Rate Generator
Out 4-1
Baud rate generator output clock allows baud rate generator
to be used externally
BRGO4-BRGO1
BRG
Baud rate generator input clock from which BRG will derive
the baud rates
BRG Input Clock
Port B 15-0
CLK2, CLK6
PB15-BP0
STRBO
PIP Data I/O Pins
This input causes the PIP output data to be placed on the
PIP data pins
Strobe Out
PIP
This input causes data on the PIP data pins to be latched by
the PIP as input data
Strobe In
STRBI
SDMA output signals used in RISC receiver to mark fields in
the Ethernet receive frame
SDMA
SDMA Acknowledge 2-1
SDACK2-SDACK1
10
TS68EN360
2113B–HIREL–06/05
TS68EN360
4. Detailed Specification
This specification describes the specific requirements for the microcontroller TS68EN360 -
25 MHz and 33 MHz in compliance with MIL-STD-883 class B or Atmel standard screening.
5. Applicable Documents
1. MIL-STD-883: test methods and procedures for electronics
2. MIL-PRF-38535: general specifications for microcircuits
3. DESC 5962-SMD-97607
The microcircuits are in accordance with the applicable document and as specified herein.
5.1
Design and Construction
5.1.1
Terminal Connections
Depending on the package, the terminal connections shall be as shown in Figure 2-1 and Figure
2-2.
5.1.2
5.1.3
Lead Material and Finish
Lead material and finish shall be as specified in MIL-STD-883 (see enclosed ”Ordering Informa-
tion” on page 79)
Package
The macrocircuits are packaged in hermetically sealed ceramic packages which are conform to
case outlines of MIL-STD-1835 or as follow:
• PGA but see ”241-pin – PGA” on page 77
• CERQUAD
The precise case outlines are described at the end of the specification (”Package Mechanical
Data” on page 77) and into MIL-STD-1835.
5.2
Absolute Maximum Ratings
Table 5-1.
Absolute Maximum Ratings
Rating
Symbol
VCC
Value
Unit
V
Supply Voltage(1)(2)
Input Voltage(1)(2)
Storage Temperature Range
-0.3 to +6.5
-0.3 to +6.5
-55 to +150
VIN
V
TSTG
°C
Notes: 1. Permanent damage can occur if maximum ratings are exceeded. Exposure to voltages or cur-
rents in excess of recommended values affects device reliability. Device modules may not
operate normally while being exposed to electrical extremes.
2. Although sections of the device contain circuitry to protect against damage from high static
voltages or electrical fields, take normal precautions to avoid exposure to voltages higher than
maximum-rated voltages.
3. The supply voltage VCC must start and restart from 0.0V; otherwise, the 360 will not come out
of reset properly.Unless otherwise stated, all voltages are referenced to the reference terminal.
11
2113B–HIREL–06/05
This device contains protective circuitry against damage due to high static voltages or electrical
fields; however, it is advised that normal precautions be taken to avoid application of any volt-
ages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation
is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or
VDD
)
Table 5-2.
Recommended Conditions of Use
Unless otherwise stated, all voltages are referenced to the reference terminal
Symbol
VCC
Parameter
Min
+4.75
GND
+2.0
-55
Typ
Max
+5.25
+0.8
VCC
Unit
V
Supply Voltage Range
VIL
Logic Low Level Input Voltage Range
Logic High Level Input Voltage Range
Operating Temperature
V
VIH
V
Tcase
VOH
+125
°C
High Level Output Voltage
+2.4
V
(For 25 MHz version)
(For 33 MHz version)
25
33
MHz
MHz
fsys
System Frequency
Table 5-3.
Symbol
Thermal Characteristics
Parameter
Value
2
Unit
240-pin Cerquad
241-pin PGA
θJC
Thermal Resistance - Junction to Case
Thermal Resistance - Junction to Ambient
°C/W
7
240-pin Cerquad
241-pin PGA
27.4
22.8
θJA
°C/W
TJ = TA + (PD · θJA)
PD = (VDD · IDD) + PI/O
Where PI/O is the power dissipation on pins.
5.3
Power Considerations
The average chip-junction temperature, TJ, in °C can be obtained from:
TJ = TA ÷ (PD · ΘJA) (1)
where:
TA = Ambient Temperature, °C
JA = Package Thermal Resistance,
Θ
Junction-to-Ambient, C/W
PD = PINT + P I/O
PINT = ICC · VCC, Watts-chip Internal Power
P
I/O = Power Dissipation on Input and Output Pins-User Determined
For most applications, PI/O < 0.3 · PINT and can be neglected.
12
TS68EN360
2113B–HIREL–06/05
TS68EN360
An approximate relationship between PD and TJ (if PI/O is neglected) is:
PD = K ÷ (TJ + 273°C)
(2)
Solving Equations (1) and (2) for K gives:
2
K = PD · (TA + 273°C) + ΘJA · PD
(3)
where K is a constant pertaining to the particular part. K can be determined from Equation (3) by
measuring PD (at thermal equilibrium) for a know TA. Using this value of K, the values of PD and
TJ can be obtained by solving Equations (1) and (2) iteratively for any value of TA.
5.4
5.5
Mechanical and Environment
The microcircuits shall meet all mechanical environmental requirements of either MIL-STD-883
for class B devices or for Atmel standard screening.
Marking
The document where are defined the marking are identified in the related reference documents.
Each microcircuit are legible and permanently marked with the following information as
minimum:
• Atmel logo
• Manufacturer’s part number
• Class B identification
• Date-code of inspection lot
• ESD identifier if available
• Country of manufacturing
6. Quality Conformance Inspection
6.1
DESC/MIL-STD-883
Is in accordance with MIL-M-38535 and method 5005 of MIL-STD-883. Group A and B inspec-
tions are performed on each production lot. Group C and D inspections are performed on a
periodical basis.
7. Electrical Characteristics
7.1
General Requirements
All static and dynamic electrical characteristics specified for inspection purposes and the rele-
vant measurement conditions are given below:
• Static electrical characteristics for the electrical variants
• Dynamic electrical characteristics for TS68EN360 (25 MHz, 33 MHz)
For static characteristics, test methods refer to IEC 748-2 method number, where existing.
For dynamic characteristics, test methods refer to clause Table 7-1 of this specification.
13
2113B–HIREL–06/05
7.2
Static Characteristics
The electrical specifications in this document are preliminary. (See numbered notes)
Table 7-1.
Static Characteristics – GND = 0 VDC, TC = -55 to +125°C
Characteristic
Symbol
VIH
Min
2.0
Max
VCC
Unit
V
Input High Voltage (except EXTAL)
Input Low Voltage (5V Part)
VIL
GND
GND
GND
0.8*(VCC
–
0.8
V
Input Low Voltage (Part Only; PA8-15, PB1, PC5, PC7, TCK)
Input Low Voltage (Part Only; All Other Pins)
EXTAL Input High Voltage
VIL
0.5
V
VIL
0.8
V
VIHC
–
)
VCC + 0.3
-0.8
V
Undershoot
V
Input Leakage Current (All Input Only Pins except for TMS, TDI and TRST)
Vin = 0/5V
Iin
-2.5
-2.5
2.5
µA
µA
Hi-Z (Off-State) Leakage Current (All Noncrystal Outputs and I/O Pins except
TMS,TDI and TRST) Vin = 0/5V
IOZ
-2.5
Signal Low Input Current VIL = 0.8V (TMS, TDI and TRST Pins Only)
Signal High Input Current VIH = 2.0V (TMS, TDI and TRST Pins Only)
IL
-0.5
-0.5
0.5
0.5
mA
mA
IH
Output High Voltage
IOH = -0.8 mA, VCC = 4.75V
VOH
2.4
–
V
AII Noncrystal Outputs Except Open Drain Pins
Output Low Voltage
I
OL = 2.0 mA, CLKO1-2, FREEZE, IPIPE0-1, IFETCH, BKPTO
0.5
0.5
IOL = 3.2 mA, A31-A0, D31-D0, FC3-0, SIZ0-1, PA0, 2, 4, 6, 8-15, PB0-5,
PB8-17, PC0-11, TDO, PERR, PRTY0-3, IOUT0-2, AVECO, AS, CAS3-0,
BLCRO, RAS0-7
VOL
–
–
V
IOL = 5.3 mA, DSACK0-1, R/W, DS, OE, RMC, BG, BGACK, BERR
IOL = 7 mA, TXD1-4
0.5
0.5
0.5
IOL = 8.9 mA, PB6, PB7, HALT, RESET, BR (Output)
Input Capacitance
AII I/O Pins
Cin
20
pF
Load Capacitance (except CLKO1-2)
Load Capacitance (CLKO1-2)
Power
CL
–
–
100
50
pF
pF
V
CLc
VCC
4.75
5.25
7.3
Dynamic Characteristics
The AC specifications presented consist of output delays, input setup and hold times, and signal
skew times. All signals are specified relative to an appropriate edge of the clock and possibly to
one or more other signals.
The measurement of the AC specifications is defined by the waveforms shown in Figure 7-1. To
test the parameters guaranteed by Atmel inputs must be driven to the voltage levels specified in
the figure. Outputs are specified with minimum and/or maximum limits, as appropriate, and are
measured as shown. Inputs are specified with minimum setup and hold times and are measured
as shown. Finally, the measurement for signal-to-signal specifications are shown.
Note that the testing levels used to verify conformance to the AC specifications do not affect the
guaranteed DC operation of the device as specified in the DC electrical characteristics.
14
TS68EN360
2113B–HIREL–06/05
TS68EN360
Figure 7-1. Drive Levels and Test Points For AC Specifications
2.0V
2.0V
0.8V
CLKOUT
0.8V
A
B
2.0V
0.8V
2.0V
0.8V
(1)
(2)
VALID
OUTPUT
VALID
OUTPUT
OUTPUTS
OUTPUTS
A
n
n + 1
B
2.0V
0.8V
2.0V
0.8V
VALID
OUTPUT
VALID
OUTPUT
n
n+1
C
D
2.0V
0.8V
2.0V
0.8V
VALID
INPUT
(3)
INPUTS
C
D
DRIVE
2.0V
0.8V
2.0V
0.8V
TO 2.4V
VALID
INPUT
(4)
(5)
INPUTS
DRIVE
TO 0.5V
2.0V
0.8V
ALL SIGNALS
E
F
2.0V
0.8V
Notes: 1. This output timing is applicable to all parameters specified relative to the rising edge of the clock
2. This output timing is applicable to all parameters specified relative to the falling edge of the clock
3. This input timing is applicable to all parameters specified relative to the rising edge of the clock
4. This input timing is applicable to all parameters specified relative to the falling edge of the clock
5. This timing is applicable to all parameters specified relative to the assertion/negation of another signal
Legend:
a) Maximum output delay specification
b) Minimum output hold time
c) Minimum input setup time specification
d) Minimum input hold time specification
e) Signal valid to signal valid specification (maximum or minimum)
f) Signal valid to signal invalid specification (maximum or minimum)
15
2113B–HIREL–06/05
7.4
AC Power Dissipation
Table 7-2.
Typical Current Drain
System Clock
Frequency
BRGCLK Clock
Frequency
SyncCLK Clock
Frequency
Mode of Operation
Symbol
IDD
Typ
250
237
327
Unit
mA
mA
mA
Normal mode (Rev A(1) and Rev B(2))
Normal Mode (Rev C(3) and Newer)
Normal Mode
25 MHz
25 MHz
33 MHz
25 MHz
25 MHz
33 MHz
25 MHz
25 MHz
33 MHz
IDD
IDD
Divide by 2
12.5 MHz
Divide by 16
1.56 MHz
Divide by 2
12.5 MHz
Low Power Mode
Low Power Mode
Low Power Mode
Low Power Mode
IDDSB
IDDSB
IDDSB
IDDSB
150
85
mA
mA
mA
mA
Divide by 4
6.25 MHz
Divide by 16
1.56 MHz
Divide by 4
6.25 MHz
Divide by 16
1.56 MHz
Divide by 16
1.56 MHz
Divide by 4
6.25 MHz
35
Divide by 256
97.6 kHz
Divide by 16
1.56 MHz
Divide by 4
6.25 MHz
20
Divide by 256
97.6 kHz
Divide by 64
390 kHz
Divide by 64
390 kHz
Low Power Mode
IDDSB
IDDSP
13
mA
mA
Low Power Stop VCO Off(4)
0.5
PLL Supply Current
PLL Disabled
IDDPD
IDDPE
TBD
TBD
PLL Enabled
Notes: 1. Rev A mask is C63T
2. Rev B masks are C69T and F35G
3. Current Rev C masks are E63C, E68C and F15W
4. EXTAL frequency is 32 kHz
All measurements were taken with only CLKO1 enabled, VCC = 5.0V, VIL = 0V and VIH = VCC
Table 7-3.
Maximum Power Dissipation
System Frequency
VCC
Max PD
1.80
Unit
W
Mask
25 MHz
25 MHz
25 MHz
33 MHz
5.25V
5.25V
3.6V
REV A(1) and REV B(2)
REV C(3) and Newer
REV C(3) and Newer
REV C(3) and Newer
1.45
W
0.65
W
5.25V
2.00
W
Notes: 1. Rev A mask is C63T
2. Rev B masks are C69T and F35G
3. Current Rev C masks are E63C, E68C and F15W
16
TS68EN360
2113B–HIREL–06/05
TS68EN360
7.5
AC Electrical Specifications Control Timing
Table 7-4.
GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary (See Figure
7-2)
25 MHz
Min
33.34 MHz
Number Characteristic
System Frequency
Symbol
fsys
Max
25.00
6000
50
Min
Max
Unit
MHz
kHz
dc(1)
33.34
6000
67
Crystal Frequency
fXTAL
fsys
25
25
20
On-Chip VCO System Frequency
20
MHz
Start-up Time
tpll
2500
clks
With external clock (oscillator disabled) or after
changing the multiplication factor MF
CLKO1-2 stability
∆
TBD
40
40
40
19
9.5
–
TBD
–
%
ns
%
CLK
1
1A
CLKO1 Period
tcyc
tdcyc
tEXTcyc
tCW1
30
40
30
14
7
–
60
–
EXTAL Duty Cycle, MF
60
–
1C
External Clock Input Period
ns
ns
ns
ns
ns
ns
ns
ns
2, 3
2A, 3A
4, 5
4A, 5A
5B
CLKO1 Pulse Width (Measured at 1.5V)
CLKO2 Pulse Width (Measured at 1.5V)
CLKO1 Rise and Fall Times (Full drive)
CLKO2 Rise and Fall Times (Full drive)
EXTAL to CLKO1 Skew-PLL enabled (MF< 5)
EXTAL to CLKO2 Skew-PLL enabled (MF< 5)
CLKO1 to CLKO2 Skew
–
–
tCW2
–
–
tCrf1
2
–
2
tCrf2
–
2
–
1.6
a
tEXTP1
tEXTP2
AtmelKW
a
5C
a
a
5D
a
a
Note:
1. Note that the minimum VCO frequency and the PLL default values put some restrictions on the minimum system frequency.
The following calculation should be used to determine the actual value for specifications 5B, 5C and 5D.
5B: 25 MHz
33 MHz
±(0.9 ns + 0.25 x (rise time)) (1.4 ns at rise = 2 ns; 1.9 ns at rise = 4 ns)
±(0.5 ns + 0.25 x (rise time)) (1 ns at rise = 2 ns; 1.5 ns at rise = 4 ns)
±(2 ns + 0.25 x (rise time)) (2.5 ns at rise = 2 ns; 3 ns at rise = 4 ns)
±(3 ns + 0.5 x (rise time)) (4 ns at rise = 2 ns; 5 ns at rise = 4 ns)
±(2.5 ns + 0.5 x (rise time)) (3.5 ns at rise = 2 ns; 4.5 ns at rise = 4 ns)
5C: 25/33 MHz
5D: 25 MHz
33 MHz
17
2113B–HIREL–06/05
Figure 7-2. Clock Timing
1A
1C
EXTAL
(INPUT)
VOLTAGE MIDPOINT
1
5C
5B
CLKO1
(OUTPUT)
2
3
4
5
5D
CLKO2
(OUTPUT)
3A
4A
2A
5A
7.6
External Capacitor For PLL
Table 7-5.
GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary.
Characteristic
Symbol
Min
Max
Unit
PLL External Capacitor (XFC to VCCSYN)
MF< 5 (Recommended value MF x 400 pF)(1)
MF> 4 (Recommended value MF x 540 pF)(1)
cXFC
MF x 340
MF x 380
MF x 480
MF x 970
pF
pF
Note:
1. MF – multiplication factor.
7.6.1
Examples:
Notes: 1. MODCK1 pin = 0, MF = 1 ⇒ CXFC = 400 pF
2. MODCK1 pin = 1, crystal is 32.768 kHz (or 4.192 MHz), initial MF = 401, initial frequency =
13.14 MHz, later on MF is changed to 762 to support a frequency of 25 MHz. Minimum CXFC
is: 762 x 380 = 289 nF, Maximum CXFC is: 401 x 970 = 390 nF. The recommended CXFC for 25
MHz is: 762 x 540 = 414 nF. 289 nF < CXFC < 390 nF and closer to 414 nF. The proper avail-
able value for CXFC is 390 nF.
3. MODCK1 pin = 1, crystal is 32.768 kHz (or 4.192 MHz), initial MF = 401, initial frequency =
13.14 MHz, later on MF is changed to 1017 to support a frequency of 33.34 MHz. Minimum
CXFC is: 1017 x 380 = 386 nF, Maximum CXFC is: 401 x 970 = 390 nF ⇒ 386 nF < CXFC < 390
nF. The proper available value for CXFC is 390 nF.
4. In order to get higher range, higher crystal frequency can be used (i.e. 50 kHz), in this case:
Minimum CXFC is: 667 x 380 = 253 nF, Maximum CXFC is: 401 x 970 = 390 nF ⇒ 386 nF <
CXFC < 390 nF.
18
TS68EN360
2113B–HIREL–06/05
TS68EN360
7.7
Bus Operation AC Timing Specifications
Table 7-6.
GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary
(See Figure 7-3 to Figure 7-19)
25 MHz
33.34 MHz
Number
Characteristic
Symbol
tCHAV
Min
Max
15
Min
Max
12
Unit
ns
6
CLKO1 High to Address, FC, SIZ, RMC Valid
CLKO1 High to Address Valid (GAMX = 1)
0
0
0
0
6A
tCHAV
20
15
ns
CLKO1 High to Address, Data, FC, SIZ, RMC High
Impedance
7
8
9
tCHAZx
tCHAZn
tCLSA
0
-2
3
40
–
0
-2
3
30
–
ns
ns
ns
CLKO1 High to Address, Data, FC, SIZ, RMC
Invalid
CLKO1 Low to AS, DS, OE, WE, IFETCH, IPIPE,
IACKx Asserted
20
15
9(10)
CLKO1 Low to CSx/RASx Asserted
CLKO1 High to CSx/RASx Asserted
AS to DS or CSx/RASx or OE Asserted (Read)
AS to CSx/RASx Asserted
tCLSA
tCHCA
tSTSA
tSTCA
4
4
16
16
6
4
12
12
ns
ns
ns
ns
9B(11)
4
-5.625
9
9A(2)(10)
9C(2)(11)
-6
14
5.625
21
26
Address, FC, SIZ, RMC, valid to AS, CSx/RASx,
OE, WE, (and DS Read) Asserted
11(10)
11A(11)
12
tAVSA
tAVCA
tCLSN
10
30
3
–
–
8
22.5
3
–
–
ns
ns
ns
Address, FC, SIZ, RMC, Valid to CSx/RASx
Asserted
CLKO1 Low to AS, DS, OE, WE, IFETCH, IPIPE,
IACKx Negated
20
15
12(16)
12A(13)(16)
12B
CLKO1 Low to CSx/RASx Negated
CLKO1 High to CSx/RASx Negated
CS negate to WE negate (CSNTQ = 1)
tCLSN
tCHCN
4
4
16
16
–
4
4
12
12
–
ns
ns
ns
AtmelTW
15
12
AS, DS, CSx, OE, WE, IACKx Negated to Address,
FC, SIZ Invalid (Address Hold)
13(12)
tSNAI
tCNAI
10
30
–
–
7.5
–
–
ns
ns
CSx Negated to Address, FC, SIZ, Invalid (Address
Hold)
13A(13)
22.5
14(10)(12)
14C(11)(13)
14A
AS, CSx, OE, WE (and DS Read) Width Asserted
CSx Width Asserted
tSWA
tCWA
75
35
35
–
–
–
56.25
26.25
26.25
–
–
–
ns
ns
ns
DS Width Asserted (Write)
tSWAW
AS, CSx, OE, WE, IACKx, (and DS Read) Width
Asserted (Fast Termination Cycle)
14B
tSWDW
35
–
26.25
–
ns
14D(13)
CSx Width Asserted (Fast Termination Cycle)
tCWDW
tSN
15
35
–
–
–
10
26.25
–
–
–
ns
ns
ns
ns
ns
ns
15(3)(10)(12) AS, DS, CSx, OE, WE Width Negated
16
17(12)
17A(13)
18
CLKO1 High to AS, DS, R/W High Impedance
AS, DS, CSx, WE Negated to R/W High
CSx Negated to R/W High
tCHSZ
tSNRN
tCNRN
tCHRH
40
–
30
–
10
30
0
7.5
22.5
0
–
–
CLKO1 High to R/W High
20
15
19
2113B–HIREL–06/05
Table 7-6.
GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary
(See Figure 7-3 to Figure 7-19) (Continued)
25 MHz
Min
33.34 MHz
Number
20
Characteristic
Symbol
tCHRL
tRAAA
tRACA
tRASA
tCHDO
tCHPV
tPVCL
Max
20
–
Min
Max
15
–
Unit
ns
CLKO1 High to R/W Low
R/W High to AS, CSx, OE Asserted
R/W High to CSx Asserted
R/W Low to DS Asserted (Write)
CLKO1 High to Data-Out
CLKO1 High to Parity Valid
Parity Valid to CAS Low
3
10
30
47
–
3
21(10)
21A(11)
22
7.5
ns
–
–
ns
–
36
–
–
ns
23
23
25
–
18
20
–
ns
23A
–
–
ns
23B
3
3
ns
Data-Out, Parity-Out Valid to Negating Edge of AS,
CSx, WE, (Fast Termination Write)
24(12)
25(12)
tDVASN
tSNDOI
tCNDOI
10
10
35
–
–
–
7.5
7.5
25
–
–
–
ns
ns
ns
DS, CSX, WE Negated to Data-Out, Parity-Out
Invalid (Data-Out, Parity-Out Hold)
CSx Negated to Data-Out, Parity-Out Invalid (Data-
Out, Parity-Out Hold)
25A(13)
26
Data-Out, Parity-Out Valid to DS Asserted (Write)
Data-In, Parity-In to CLKO1 Low (Data-Setup)
Data-In, Parity-In Valid to CLKO1 Low (Data-Setup)
tDVSA
tDICL
tDICL
10
1
–
–
–
7.5
1
–
–
–
ns
ns
ns
27(15)
27B(14)
20
15
Late BERR, HALT, BKPT Asserted to CLKO1 Low
(Setup Time)
27A
tBELCL
tSNDN
10
0
–
7.5
0
–
ns
ns
AS, DS Negated to DSACKx, BERR, HALT
Negated
28(18)
50
37.5
DS, CSx, OE, Negated to Data-In Parity-In Invalid
(Data-In, Parity-In Hold)
29(4)
29A(4)
30(4)
tSNDI
tSHDI
tCLDI
0
–
–
40
–
0
–
–
30
–
ns
ns
ns
DS, CSx, OE Negated to Data-In High Impedance
CLKO1 Low to Data-In, Parity-In Invalid (Fast
Termination Hold)
10
7.5
30A(4)
31(5)(15)
31A
31B(5)(14)
32
CLKO1 Low to Data-In High Impedance
DSACKx Asserted to Data-in, Parity-In Valid
DSACKx Asserted to DSACKx Valid (Skew)
DSACKx Asserted to Data-in, Parity-In Valid
HALT an RESET Input Transition Time
CLKO1 High to BG Asserted
tCLDH
tDADI
tDADV
tDADI
tHRrf
–
–
60
32
10
35
140
20
20
–
–
–
45
24
7.5
26
ns
ns
–
–
ns
–
–
ns
–
–
ns
33
tCLBA
tCLBN
tBRAGA
tGAGN
tGH
–
–
15
15
–
ns
34
CLKO1 High to BG Negated
–
22.5
1
ns
35(6)
BR Asserted to BG Asserted (RMC Not Asserted)
BGACK Asserted to BG Negated
BG Width Negated
1
CLKO1
CLKO1
CLKO1
CLKO1
ns
37
1
2.5
–
1
2.5
–
39
2
2
39A
46
BG Width Asserted
tGA
1
–
1
–
R/W Width Asserted (Write or Read)
tRWA
100
–
75
–
20
TS68EN360
2113B–HIREL–06/05
TS68EN360
Table 7-6.
GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary
(See Figure 7-3 to Figure 7-19) (Continued)
25 MHz
33.34 MHz
Number
Characteristic
Symbol
Min
Max
Min
Max
Unit
R/W Width Asserted (Fast Termination Write or
Read)
46A
tRWAS
75
–
56
–
ns
47A
47B
Asynchronous Input Setup Time
tAIST
tAIHT
tDABA
tDOCH
5
10
–
–
–
4
7.5
–
–
–
ns
ns
ns
ns
Asynchronous Input Hold Time
48(5)(7)
DSACKx Asserted to BERR, HALT Asserted
Data-Out, Parity-Out Hold from CLKO1 High
30
–
22.5
–
53
0
0
CLKO1 High to Dat-Out, Parity-Out High
Impedance
54
tCHDH
–
20
–
15
ns
55
56
R/W Asserted to Data Bus Impedance Change
RESET Pulse Width (Reset Instruction)
tRADC
tHRPW
tRPWI
tBNHN
25
512
20
0
–
–
–
–
19
512
20
0
–
–
–
–
ns
CLKO1
CLKO1
ns
56A
57
RESET Pulse Width (Input from External Device)
BERR Negated to HALT Negated (Return)
CLKO1 High to BERR, RESETS, RESETH Driven
Low
58
tCHBRL
tCLRL
tCLRL
–
–
–
30
30
20
26
26
15
ns
ns
ns
CLKO1 Low RESETS Driven Low (upon Reset
Instruction execution only)
58A
58B
CLKO1 High to BERR, RESETS, RESETH
tri-stated
–
60
61
CLKO1 High to BCLRO Asserted
CLKO1 High to BCLRO Negated
BR Synchronous Setup Time
tCHBCA
tCHBCN
tBRSU
tBRH
–
–
20
20
–
–
–
15
15
–
ns
ns
62(9)
63(9)
64(9)
65(9)
66
5
3.75
7.5
3.75
7.5
5
ns
BR Synchronous Hold Time
10
5
–
–
ns
BGACK Synchronous Setup Time
BGACK Synchronous Hold Time
BR Low to CLKO1 Rising Edge (040 comp. mode)
CLKO1 Low to Data Bus Driven (Show Cycle)
Data Setup Time to CLKO1 Low (Show Cycle)
Data Hold from CLKO1 Low (Show Cycle)
BKPT Input Setup Time
tBGSU
tBGH
–
–
ns
10
5
–
–
ns
tBRCH
tSCLDD
tSCLDS
tSCLDH
tBKST
tBKHT
tMST
–
–
ns
70
0
30
–
0
22.5
–
ns
71
10
6
7.5
3.75
7.5
3.75
–
ns
72
–
–
ns
73
10
6
–
–
ns
74
BKPT Input Hold Time
–
–
ns
75
RESETH Low to Config2-0, MOD1-0, B16M Valid
Config2-0
–
500
–
500
–
CLKO1
ns
76
tMSH
0
0
77
MOD1-0 Hold Time, B16M Hold Time
DSI Input Setup Time
tMSH
10
10
6
–
10
–
CLKO1
ns
80
tDSISU
tDSIH
–
7.5
3.75
7.5
–
81
DSI Input Hold Time
–
–
ns
82
DSCLC Setup Time
tDSCSU
10
–
–
ns
21
2113B–HIREL–06/05
Table 7-6.
GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary
(See Figure 7-3 to Figure 7-19) (Continued)
25 MHz
33.34 MHz
Number
Characteristic
Symbol
Min
Max
Min
Max
Unit
83
DSCLC Hold Time
tDSCH
6
–
–
3.75
–
–
ns
tcyc+2
0
tcyc+2
0
84
DSO Delay Time
tDSOD
ns
85
86
87
88
89
90
91
92
DSCLK Cycle
tDSCCYC
tFRZA
tFRZN
tIFZ
2
0
0
0
0
0
0
5
–
2
0
0
0
0
0
0
5
–
CLKO1
ns
CLKO1 High to Freeze Asserted
CLKO1 High to Freeze Negated
CLKO1 High to IFETCH High Impedance
CLKO1 High to IFETCH Valid
CLKO1 High to PERR Asserted
CLKO1 High to PERR Negated
VCC Ramp-Up Time At Power-On Reset
35
35
35
35
20
20
–
26.25
26.25
26.25
26.25
15
ns
ns
tIF
ns
tCHPA
tCHPN
tRMIN
ns
15
ns
–
ns
Notes: 1. All AC timing is shown with respect to 0.8V and 2.0V levels unless otherwise noted.
2. This number can be reduced to 5 ns if strobes have equal loads.
3. If multiple chip selects are used, the CSx width negated (#15) applies to the time from the negation of a heavily loaded chip
select to the assertion of a lightly loaded chip select.
4. Hold times are specified with respect to DS or CSx on asynchronous reads and with respect to CLKO1 on fast termination
reads. The user is free to use either hold time for fast termination reads.
5. If the asynchronous setup (#17) requirements are satisfied, the DSACKx low to data setup time (#31) and DSACKx low to
BERR low setup time (#48) can be ignored. The data must only satisfy the data-in to CLKO1 low setup time (#27) for the fol-
lowing clock cycle: BERR must only satisfy the late BERR low to CLKO1 low setup time (#27A) for the following clock cycle.
6. To ensure coherency during every operand transfer, BG will not be asserted in response to BR until after cycles of the cur-
rent operand transfer are complete and RMC is negated.
7. In the absence of DSACKx, BERR is an asynchronous input using the asynchronous setup time (#47).
8. During interrupt acknowledge cycles, the processor may insert up to two wait states between states S0 and S1.
9. Specs are for Synchronous Arbitration only. ASTM = 1.
10. CSx specs are for TRLX = 0.
11. CSx specs are for TRLX = 1.
12. CSx specs are for CSNTQ = 0.
13. CSx specs are for CSNTQ = 1; or RASx specs for DRAM accesses.
14. Specs are read cycles with parity check and PBEE = 1.
15. Specs are read cycles with parity check and PBEE = 0, PAREN = 1.
16. RASx specs are for page miss case.
17. Specifications only apply to CSx/RASx pins.
18. Specification applies to non fast termination cycles. In fast termination cycles, the BERR signal must be negated by 20 ns
after negation of AS, DS.
22
TS68EN360
2113B–HIREL–06/05
TS68EN360
Figure 7-3. Read Cycle
S0
S1
S2
S3
S4
S5
CLKO1
(OUTPUT)
6
8
A31-A0
(OUTPUT)
FC3-FC0
(OUTPUT)
SIZ1-SIZ0
(OUTPUT)
RMC
(OUTPUT)
11
16
14
AS
(OUTPUT)
12
9
13
DS
(OUTPUT)
15
9A
CSx
(OUTPUT)
OE
(OUTPUT)
20
21
18
R/W
(OUTPUT)
46
DSACK0
(I/O)
28
47A
DSACK1
(I/O)
31A
29
31
D31-D0
(INPUT)
27
29A
48
27A
BERR,
HALT
(INPUT)
9
12
12
IFETCH
IPIPE1,0
(OUTPUT)
47A
47B
ASYNCHRONOUS
INPUTS
73
74
BKPT
(INPUT)
Note:
All timing is shown with respect to 0.8V and 2.0V levels.
23
2113B–HIREL–06/05
Figure 7-4. Fast Termination Read Cycle (Parity Check PAREN = 1, PBEE = 0)
CPU CLEARS PERn BIT
S0
S1
S4
S5
S0
S0
CLKO1
(OUTPUT)
8
6
A31-A0
(OUTPUT)
FC3-FC0
(OUTPUT)
SIZ1-SIZ0
(OUTPUT)
9
14B
AS
(OUTPUT)
12
DS
(OUTPUT)
CSx
(OUTPUT)
OE
(OUTPUT)
18
46A
R/W
(OUTPUT)
27
30
D31-D0
(INPUT)
30A
73
74
BKPT
(INPUT)
90
91
PERR
(OUTPUT)
24
TS68EN360
2113B–HIREL–06/05
TS68EN360
Figure 7-5. Read Cycle (With Parity Check, PBEE = 1)
S0
S1
S2
S3
S4
S5
CLKO1
(OUTPUT)
6
8
A31-A0, FC3-FC0,
SIZ1-SIZ0 (OUTPUT)
RMC
(OUTPUT)
11
16
14
AS
(OUTPUT)
12
9
13
DS
(OUTPUT)
15
9A
CSx
(OUTPUIT)
OE
(OUTPUT)
21
20
18
R/W
(OUTPUT)
46
31A
DSACK0
(I/O)
47A
28
DSACK1
(I/O)
PRTY0-PRTY3
(INPUT)
29
31B
D31-D0
(INPUT)
29A
27B
BERR
(INPUT)
48
27A
HALT
(INPUT)
9
12
12
IFETCH
(OUTPUT)
47A
47B
IPIPE1,0
(OUTPUT)
ASYNCHRONOUS
INPUTS
73
74
BKPT
(INPUT)
Note:
All timing is shown with respect to 0.8V and 2.0V levels.
25
2113B–HIREL–06/05
Figure 7-6. SRAM: Read Cycle (TRLX = 1)
S0
S1
S2
S3
S4
S5
CLKO1
(OUTPUT)
6
8
A31-A0
(OUTPUT)
FC3-FC0
(OUTPUT)
SIZ1-SIZ0
(OUTPUT)
RMC
(OUTPUT)
16
9C
AS
(OUTPUT)
13
11A
12
DS
(OUTPUT)
15
9B
CSx
(OUTPUT)
20
21A
OE
(OUTPUT)
18
R/W
(OUTPUT)
46
28
DSACK0
(I/O)
47A
DSACK1
(I/O)
31A
29
31
D31-D0
(INPUT)
29A
27
26
TS68EN360
2113B–HIREL–06/05
TS68EN360
Figure 7-7. CPU32+ IACK Cycle
*
0-2 CLOCKS
A2 A3
S0
A1
A4
S1
S2
S3
S4
S5
CLKO1
(OUTPUT)
8
6
A31-A0
(OUTPUT)
FC3-FC0
(OUTPUT)
SIZ1-SIZ0
(OUTPUT)
16
11
14
AS
(OUTPUT)
13
9
12
DS
(OUTPUT)
15
9A
IACKx
(OUTPUT)
OE
(OUTPUT)
20
18
21
R/W
(OUTPUT)
46
31A
28
DSACK0
(I/O)
47A
31
DSACK1
(I/O)
29
D31-D0
(INPUT)
29A
27
Note:
Up to two wait states may be inserted by the processor between states S0 and S1.
27
2113B–HIREL–06/05
Figure 7-8. Write Cycle
S0
S1
S2
S3
S4
S5
CLKO1
(OUTPUT)
6
8
A31-A0
(OUTPUT)
FC3-FC0
(OUTPUT)
SIZ1-SIZ0
(OUTPUT)
11
15
14
AS
(OUTPUT)
12
9
9
13
DS
(OUTPUT)
14A
CSn
(OUTPUT)
22
17
WEn
(OUTPUT)
18
20
R/W
(OUTPUT)
46
DSACK0
(I/O)
31A
28
47A
DSACK1
(I/O)
25
55
53
D31-D0
(OUTPUT)
23
54
26
PRTY3-PRTY0
(OUTPUT)
BERR
(INPUT)
48
73
74
HALT
(INPUT)
BKPT
(INPUT)
Note:
All timing is shown with respect to 0.8V and 2.0V levels.
28
TS68EN360
2113B–HIREL–06/05
TS68EN360
Figure 7-9. Fast Termination Write Cycle
S0
S1
S4
S5
S0
CLKO1
(OUTPUT)
6
8
A31-A0
(OUTPUT)
FC3-FC0
(OUTPUT)
SIZ1-SIZ0
(OUTPUT)
12
AS
(OUTPUT)
9
14B
CSx
(OUTPUT)
DS
(OUTPUT)
WEx
(OUTPUT)
20
46A
R/W
(OUTPUT)
23
18
24
D31-D0
(OUTPUT)
25
PRTY3-PRTY0
(OUTPUT)
73
74
BKPT
(INPUT)
Figure 7-10. SRAM: Fast Termination Write Cycle (CSNTQ = 1)
S0
S1
S4
S5
S0
CLKO1
(OUTPUT)
8
6
A31-A0
(OUTPUT)
FC3-FC0
(OUTPUT)
SIZ1-SIZ0
(OUTPUT)
12A
AS
(OUTPUT)
9
14D
CSx
(OUTPUT)
DS
(OUTPUT)
WEx
(OUTPUT)
20
46A
R/W
(OUTPUT)
18
23
D31-D0
(OUTPUT)
25A
PRTY3-PRTY0
(OUTPUT)
29
2113B–HIREL–06/05
Figure 7-11. SRAM: Write Cycle (TRLX = 1, CSNTQ = 1, TCYC = 0)
S0
S1
S2
S3
S4
S5
CLKO1
(OUTPUT)
A31-A0
(OUTPUT)
AS
(OUTPUT)
9C
DS
(OUTPUT)
11A
9B
12A
CSx
(OUTPUT)
14C
13A
WEx
(OUTPUT)
20
17A
22
R/W
(OUTPUT)
46
47A
DSACK0
(I/O)
31A
DSACK1
(I/O)
55
25A
26
D31-D0
(OUTPUT)
23
PRTY0-PRTY3
(OUTPUT)
Note:
All timing is shown with respect to 0.8V and 2.0V levels.
Figure 7-12. ASYNC Bus Arbitration – IDLE Bus Case
CLKO1
(OUTPUT)
A31-A0
(OUTPUT)
D31-D0
(OUTPUT)
AS
(OUTPUT)
47A
47A
BR
(INPUT)
35
37
BG
(OUTPUT)
47A
33
34
BGACK
(INPUT)
47A
BCLRO
(OUTPUT)
60
61
30
TS68EN360
2113B–HIREL–06/05
TS68EN360
Figure 7-13. ASYNC Bus Arbitration – Active Bus Case
S0
S1
S2
S3
S4
S5
CLKO1
(OUTPUT)
A31-A0
(OUTPUT)
7
D31-D0
(OUTPUT)
AS
(OUTPUT)
16
DS
(OUTPUT)
R/W
(OUTPUT)
DSACK0
(I/O)
DSACK1
(I/O)
47A
47A
BR
(INPUT)
39A
35
BG
(OUTPUT)
33
34
BGACK
(INPUT)
47A
37
BCLRO
(OUTPUT)
60
Figure 7-14. SYNC Bus Arbitration – IDLE Bus Case
CLKO1
(OUTPUT)
A31-A0
(OUTPUT)
D31-D0
(OUTPUT)
AS
(OUTPUT)
63
62
BR
(INPUT)
37
35
BG
(OUTPUT)
65
33
34
BGACK
(INPUT)
64
BCLRO
(OUTPUT)
61
60
31
2113B–HIREL–06/05
Figure 7-15. SYNC Bus Arbitration – Active Bus Case
S98
S0
S1
S2
S3
S4
S5
CLKO1
(OUTPUT)
A31-A0
(OUTPUT)
7
D31-D0
(OUTPUT)
AS
(OUTPUT)
16
DS
(OUTPUT)
R/W
(OUTPUT)
DSACK0
(I/O)
DSACK1
(I/O)
62
BR
(INPUT)
35
39A
BG
(OUTPUT)
33
34
BGACK
(INPUT)
64
37
60
BCLRO
(OUTPUT)
Figure 7-16. Configuration and Clock Mode Select Timing
RWSWTH
CONFIGꢀ-CONFIGE6
7ꢁ
77
MODCK1-MODCKE6
1ꢁBM
75
32
TS68EN360
2113B–HIREL–06/05
TS68EN360
Figure 7-17. Show Cycle
S0
S2
S41
S42
S43
S0
S1
CLKO1
(OUTPUT)
8
6
A31-A0
(OUTPUT)
18
20
R/W
(OUTPUT)
AS
(OUTPUT)
12
15
9
DS
(OUTPUT)
72
71
70
D31-D0
27A
BKPT
(INPUT)
SHOW CYCLE
START OF EXTERNAL CYCLE
Figure 7-18. Background Debug Mode FREEZE Timing
CLKO1
86
FREEZE
87
IFETCH/DSI
89
88
Figure 7-19. Background Debug Mode Serial Port Timing
CLKO1
FREEZE
83
82
BKPT/DSCLK
IFETCH
80
81
84
IPIPE0/DSO
DSI
85
80
33
2113B–HIREL–06/05
Figure 7-20. DRAM: Normal Read Cycle (Internal Mux, TRLX = 0)
S0
S1
S2
S3
S4
S5
S0
S1
S2
S3
SW
SW
CLKO1
(OUTPUT)
6A
6
8
A31-A0
(OUTPUT)
108
11
107
AS
(OUTPUT)
9
12
9
100
101
RASx
(OUTPUT)
103
102
106
109
104
CAS3-CAS0
(OUTPUT)
110
111
105
OE
(OUTPUT)
21
18
R/W
(OUTPUT)
DSACK1,0
(I/O)
27
D31ÐD0
(INPUT)
29
PBEE = 0
27B
PARITY3-PARITY0
(INPUT)
PBEE = 1
D31-D0
(INPUT)
Note:
All timing is shown with respect to 0.8V and 2.0V levels.
34
TS68EN360
2113B–HIREL–06/05
TS68EN360
7.8
Bus Operation – DRAM Accesses AC Timing Specification
Table 7-7.
GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary (See Figure
7-20 to Figure 7-24)
25.0 MHz
33.34 MHz
Unit
Number Characteristic
Min
Max
Min
Max
100
101
102
RASx Asserted to Row Address Invalid
15
20
75
11.25
15
ns
ns
ns
RASx Asserted to column Address Valid
RASx Width Asserted
56.25
RASx width Negated (Back to back Cycle) Non page mode at
WBTQ = 0
103A
103B
103C
75
55
56.25
41.25
86.25
ns
ns
ns
RASx width Negated (Back to back Cycle) Page mode at WBTQ = 0
RASx width Negated (Back to back Cycle) Non page mode at
WBTQ = 1
115
103D
104
105
105A
106
107
108
109
110
1111
111A
113
114
115
116
117
119
120
121
122
123
124
125
RASx width Negated (Back to back Cycle) Page mode at WBTQ = 1
RASx Asserted to CASx Asserted
CLKO1 Low to CASx Asserted
95
35
3
69.23
26.25
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
13
13
13
10
10
10
CLKO1 High to CASx Asserted (Refresh Cycle)
CLKO1 High to CASx Negated
3
2
3
2
Column Address Valid to CASx Asserted
CASx Asserted to Column Address Negated
CASx Asserted to RASx Negated
CASx Width Asserted
15
40
35
50
95
20
35
35
52.5
55
10
3
11.25
30
27
37.5
71.25
15
CASx Width Negated (Back to Back Cycles)
CASx Width Negated (Page Mode)
WE Low to CASx Asserted
27
CASx Asserted to WE Negated
27
R/W Low to CASx Asserted (Write)
CASx Asserted to R/W High (Write)
Data-Out, Parity-Out Valid to CASx Asserted
CLKO1 High to AMUX Negated
40
41.25
7.5
16
16
2
12
12
CLKO1 High to AMUX Asserted
3
2
AMUX High to RASx Asserted
15
15
15
55
0
11.25
11.25
11.25
41.25
0
RASx Asserted to AMUX Low
AMUX Low to CASx Asserted
CASx Asserted to AMUX High
RAS/CASx Negated to R/W change
35
2113B–HIREL–06/05
Figure 7-21. DRAM: Normal Write Cycle
S0
S1
S2
S3
S4
S5
S0
CLKO1
(OUTPUT)
6A
6
8
A31-A0
(OUTPUT)
108
11
107
AS
(OUTPUT)
9
12
100
101
RASx
(OUTPUT)
102
106
CAS3-CAS0
(OUTPUT)
105
110
113
114
WEx
(OUTPUT)
20
116
115
R/W
(OUTPUT)
17
DSACK1,0
(I/O)
117
D31-D0
(OUTPUT)
23
53
PARITY0-PARITY3
(OUTPUT)
Note:
All timing is shown with respect to 0.8V and 2.0V levels.
36
TS68EN360
2113B–HIREL–06/05
TS68EN360
Figure 7-22. DRAM: Refresh Cycle
S4
S5
S0
S1
CLKO1
(OUTPUT)
A31-A0
(OUTPUT)
106
CAS3-CAS0
(OUTPUT)
105A
12
12
9
RASx
(OUTPUT)
12A
RASx
(OUTPUT)
PAGE MODE
NOT IN PAGE MODE
Note:
All timing is shown with respect to 0.8V and 2.0V levels.
Figure 7-23. DRAM: Page Mode – Page-Hit
S0
S1
S2
S3
S4
S5
S0
S1
S4
8
S5
S0
S1
CLKO1
(OUTPUT)
6A
6A
A31-A0
(OUTPUT)
108
11
INTERNAL MUX
X
107
107
AS
(OUTPUT)
9
100
101
RASx
(OUTPUT)
105
106
CAS3-CAS0
(OUTPUT)
105
121
111A
122
123
AMUX
(OUTPUT)
120
119
124
EXTERNAL MUX
Note:
All timing is shown with respect to 0.8V and 2.0V levels.
37
2113B–HIREL–06/05
Figure 7-24. DRAM: Page Mode – Page-Miss
S0
S1
S3
S4
S5
S1
S2
S3
SW
S2
SW
S0
CLKO1
(OUTPUT)
6A
6A
8
A31-A0
(OUTPUT)
INTERNAL MUX
11
AS
(OUTPUT)
9
12A
106
RASn
(OUTPUT)
CAS3-CAS0
(OUTPUT)
105
123
122
AMUX
(OUTPUT)
120
120
119
EXTERNAL MUX
Note:
All timing is shown with respect to 0.8V and 2.0V levels.
38
TS68EN360
2113B–HIREL–06/05
TS68EN360
7.9
040 Bus Type Slave Mode Bus Arbitration AC Electrical Specifications
Table 7-8.
GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary (See Figure
7-25)
25.0 MHz
33.34 MHz
Number Characteristic
Min
Max
–
Min
Max
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
231
232(1)
233
234
235
236
237
238
Address, Transfer Attributes High Impedance to Clock High
7
–
4
7
0
–
–
–
6
–
4
6
0
–
–
–
Clock High to BG Low
20
20
–
15
15
–
Clock High to BG High
BB High to Clock High (040 output)
BB High Impedance to Clock High (040 output)
Clock High to BB Low (360 Output)
Clock High to BB High (360 Output)
Clock Low to BB High Impedance (360 output)
–
–
20
20
20
15
15
15
Note:
1. BG remains low until either the SDMA or the IDMA requests the external bus.
Figure 7-25. TS68040 Companion Mode Arbitration
040 BUS MASTER
360 BUS MASTER
C2
C1
S0
S1
S2
S3
S5
S4
CLKO1
(OUTPUT)
A31-A0
(I/O)
231
TRANSFER
ATTRIBUTES
(INPUT)
232
233
BG
(OUTPUT)
234
237
BB
(I/O)
235
238
236
61
60
BCLRO
(OUTPUT)
141
140
BCLRI
(INPUT)
Notes: 1. TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W, LOCK.
2. BG always remains asserted until either the SDMA or the IDMA requests the external bus
39
2113B–HIREL–06/05
7.10 040 Bus Type Slave Mode Internal Read/Write/Lack Cycles AC Electrical Specifications
Table 7-9.
GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary
(See Figure 7-26 to Figure 7-29)
25.0 MHz
33.34 MHz
Number Characteristic
Min
Max
–
Min
Max
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
251(1)
252
253
254
255
256
257
257
258(2)(3)
259
Address, Transfer Attributes Valid to Clock Low
15
7
5
0
0
0
4
4
4
–
–
–
–
–
–
–
–
–
11.25
TS Low to Clock High
–
6
3
0
0
0
4
4
4
–
–
–
–
–
–
–
–
–
–
Clock High to TS High
–
–
Clock high to Address, Transfer Attributes Invalid
Data-In, MBARE Valid to Clock High (040 Write)
Clock High to Data-In, MBARE Hold Time
Clock High to TA, TBI Low (External to External)
Clock High to TA, TBI Low (External to Internal)
Clock High to TA, TBI High
–
–
–
–
–
–
20
23
20
15
20
20
15
20
30
30
30
30
15
18
15
11.25
15
15
TA, TBI High to TA, TBI High Impedance
Clock Low to Data-Out Valid (040 Read)
Clock Low to Data-Out Invalid
260
262
263
Clock Low to Data-Out High Impedance
Clock High to AVECO Low
264
265
15
23
23
23
23
Clock Low to AVECO High Impedance
Clock Low to IACK Low
266
267
268
Clock High to IACK High
Clock Low to AVEC Low
Notes: 1. Transfer attributes signals = SIZx, TTx, TMx, R/W and LOCK.
2. When TS68040 is accessing the internal registers, specification 258 is from clock low not clock high.
3. The clock reference is EXTAL, not CLK01.TS68040 Internal Registers Read Cycles
40
TS68EN360
2113B–HIREL–06/05
TS68EN360
Figure 7-26. TS68040 Internal Registers Read Cycles
C1
C2
CW
CW
CW
CW
C1
CLKO1
(OUTPUT)
251
A31-A0
(INPUT)
254
TRANSFER
ATTRIBUTES
(INPUT)
253
252
TS
(INPUT)
260
263
D31-D0
(040 WRITE)
(INPUT)
TA
(OUTPUT)
258
257
259
TBI
(OUTPUT)
3Ð4 CLOCKS
Notes: 1. Three wait states are inserted when reading the SIM, dual-port RAM, and CPM. Four wait states are inserted when reading
the SI RAM. Additional wait states may be inserted when the SHEN1-SHEN0 = 10 and one of the internal masters is
accessing an internal peripheral.
2. TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W, LOCK.
Figure 7-27. TS68040 Internal Registers Write Cycles
C1
C2
CW
CW
CW
C1
CLKO1
(OUTPUT)
251
A31-A0
(INPUT)
254
TRANSFER
ATTRIBUTES
(INPUT)
253
252
TS
(INPUT)
256
255
D31-D0
(040 WRITE)
(INPUT)
256
255
MBARE
(INPUT)
258
TA
(OUTPUT)
257
259
TBI
(OUTPUT)
2Ñ4 CLOCKS
Notes: 1. Two wait states are inserted when writing. Three wait states are inserted when writing to the dual-port RAM and CPM. Four
wait states are inserted when writing to the SI RAM. Additional wait states may be inserted when the SHEN1-SHEN0 = 10
and one of the internal masters is accessing an internal peripheral.
2. TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W, LOCK.
41
2113B–HIREL–06/05
Figure 7-28. TS68040 IACK Cycles (Vector Driven)
C1
C2
CW
CW
CW
CW
CW
CLKO1
(OUTPUT)
251
254
A31-A0
(INPUT)
TRANSFER
ATTRIBUTES
(INPUT)
253
252
TS
263
258
(INPUT)
262
259
D31-D0
(OUTPUT)
260
TA
(OUTPUT)
257
TBI
(OUTPUT)
IACK7-1
(OUTPUT)
266
267
0Ð2 CLOCKS
Notes: 1. TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W, LOCK.
2. Up to two wait states may be inserted for internal peripheral.
Figure 7-29. TS68040 IACK Cycles (No Vector Driven)
C1
C2
CW
CW
254
CLKO1
(OUTPUT)
251
A31-A0
(INPUT)
TRANSFER
ATTRIBUTES
(INPUT)
253
252
TS
(INPUT)
290
TA
(INPUT)
289
TBI
(OUTPUT)
257
250
265
AVECO
(OUTPUT)
264
IACK7-1
(OUTPUT)
266
267
Note:
TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W, LOCK.
42
TS68EN360
2113B–HIREL–06/05
TS68EN360
7.11 040 Bus Type SRAM/DRAM Cycles AC Electrical Specifications
Table 7-10. GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary
(See Figure 7-30 to Figure 7-34)
25.0 MHz
33.34 MHz
Number Characteristic
Min
Max
20
–
Min
Max
15
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
280
280A
281
Address Valid to BADD2-3 Valid
–
15
0
–
10
0
BADD2-3 Valid to CAS Assertion
Address Invalid to BADD2-3 Invalid
Clock High to CSx/RASx Low (TSS40 = 0)
Clock High to CSx/RASx High (CSNT40 = 0)
Clock High to BRK Low
–
–
282
4
16
16
20
20
20
16
16
–
4
12
12
15
15
15
12
12
–
283
4
4
284
–
–
284A
285
Clock Low to BRK Low
–
–
Clock high to BRK High
–
–
286
Clock Low to CSx/RASx Low (TSS40 = 1)
Clock Low to CSx/RASx High (CSNT40 = 1)
Address Transfer Attributes Valid to Clock High (TSS40 = 0)
TA Low to Clock High (External Termination)
Clock High to TA High (External Termination)
Clock High to OE Low (Read Cycles)
Clock High to OE High (Read Cycles)
Clock High to WE Low (Write Cycles)
Clock High to WE High (Write Cycles)
Clock High to CASx Low
4
4
287
4
4
288(1)
289(2)
290(2)
291
10
11
–
10
9
–
–
20
20
20
20
20
13
13
13
16
16
20
–
–
15
15
15
15
15
10
10
10
12
12
15
–
–
–
292
–
–
293
–
–
294
–
–
295
4
4
295A
296(3)
297
Clock Low to CASx Low (040 Burst Read only)
Clock High to CASx High
4
4
4
4
Clock Low to AMUX Low
3
3
298
Clock High to AMUX High
3
3
299
Clock High to BADD2-3 Valid (040 Burst Cycles)
TEA Low to Clock High
4
4
300(2)
301(2)
302
11
2
Clock High to TEA High
20
–
2
6
5
–
15
–
Data, Parity Valid to Clock High (Data, Parity Setup)
Clock High to Data, Parity Invalid (Data, Parity Hold)
CLKO1 High (After TS Low) to Parity Valid
CLKO1 High (After TA Low) to Parity Hi-Z
7
303
7
–
–
305
–
20
20
15
15
306
4
Notes: 1. Transfer attributes signals = SIZx, TTx, TMx, R/W and LOCK.
2. TEA/TA should not be asserted on a DRAM burst access, or on the same clock or before RASx/CSx is asserted.
3. The clock reference is EXTAL, not CLK01.
43
2113B–HIREL–06/05
Figure 7-30. TS68040 SRAM Read/Write Cycles (TSS40 = 0, CSNT40 = 0)
C1
C2
CLKO1
(OUTPUT)
288
TRANSFER
ATTRIBUTES
(INPUT)
254
A31-A0
(INPUT)
280
281
BADD3-
BADD2
(OUTPUT)
253
252
282
TS
(INPUT)
283
CSx
(OUTPUT)
258
TA
(OUTPUT)
259
257
TBI
(OUTPUT)
284
291
285
BKPTO
(OUTPUT)
OE
(OUTPUT)
(READ
292
CYCLES)
293
WE
(OUTPUT)
(WRITE
294
300
CYCLES)
301
TEA
(INPUT)
Note:
TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W, LOCK.
44
TS68EN360
2113B–HIREL–06/05
TS68EN360
Figure 7-31. TS68040 SRAM Read/Write Cycles (TSS40 = 1, CSNT40 = 1)
C1
C2
C3
CLKO1
(OUTPUT)
251
TRANSFER
ATTRIBUTES
(INPUT)
254
A31-A0
(INPUT)
281
280
BADD3-
BADD2
(OUTPUT)
253
252
TS
(INPUT)
287
CSn
(OUTPUT)
286
258
TA
(OUTPUT)
259
257
TBI
(OUTPUT)
284A
285
BKPTO
(OUTPUT)
300
301
TEA
(INPUT)
290
289
TA
(INPUT)
45
2113B–HIREL–06/05
Figure 7-32. External TS68040 DRAM Cycles Timing Diagram
C1
Cw
C2
C1
CLKO1
(OUTPUT)
288
TRANSFER
ATTRIBUTES
(INPUT)
254
A31-A0
(INPUT)
281
280
BADD3-
BADD2
(OUTPUT)
253
252
TS
(INPUT)
282
283
RASx
(OUTPUT)
296
295
CAS3-
CAS0
(OUTPUT)
122
121
123
298
298
294
AMUX
(OUTPUT)
297
293
WE
(WRITE CYCLE
OUTPUT)
258
TA
(OUTPUT)
257
259
TBI
(OUTPUT)
300
301
TEA
(INPUT)
46
TS68EN360
2113B–HIREL–06/05
TS68EN360
Figure 7-33. External TS68040 DRAM Burst Cycles Timing Diagram
C1
Cw
C2
C1
C2
CLKO1
(OUTPUT)
288
TRANSFER
ATTRIBUTES
(INPUT)
A31-A0
(INPUT)
299
299
280
BADD3-
BADD2
(OUTPUT)
253
252
TS
(INPUT)
282
RASx
(OUTPUT)
295A
296
296
CAS3-
CAS0
(OUTPUT)
295
295
AMUX
(OUTPUT)
297
WE
(WRITE
CYCLE
OUTPUT)
293
258
258
TA
(OUTPUT)
257
257
TBI
(OUTPUT)
47
2113B–HIREL–06/05
Figure 7-34. External TS68040 Parity Bit Checking Timing Diagram
D31-D0
(INPUT)
PRTY3-
PRTY0
(OUTPUT)
212
213
(a) Generation Timing Diagram
CPU Clears PERn Bit
C1
C2
C1
CLKO1
(OUTPUT)
TRANSFER
ATTRIBUTES
(INPUT)
A31-A0
(INPUT)
BADD3-
BADD2
(OUTPUT)
TS
(INPUT)
TA
(OUTPUT)
302
303
D31-D0,
(INPUT)
305
306
PRTY3-
PRTY0
(INPUT)
90
91
PERR
(OUTPUT)
(b) Checking Timing Diagram
48
TS68EN360
2113B–HIREL–06/05
TS68EN360
7.12 IDMA AC Electrical Specifications
Table 7-11. GND = 0 VDC, TC = -55 to +125°C.The electrical specifications in this document are preliminary
(See Figure 7-35 and Figure 7-36)
25.0 MHz
33.34 MHz
Number Characteristic
Min
Max
24
Min
Max
18
Unit
ns
1
CLKO1 Low to DACK, DONE Asserted
3
3
3
3
2
CLKO1 Low to DACK, DONE Negated
24
18
ns
3(1)
4(1)
5(1)
6
DREQx Asserted to AS Asserted (for DMA Bus Cycle)
Asynchronous Input Setup Time to CLKO1 Low
Asynchronous Input Hold Time from CLKO1 Low
AS to DACK Assertion Skew
3tcyc + tAIST + tCLSA
12
0
–
–
9
0
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
clk
0
20
8
0
15
6
7
DACK to DONE Assertion Skew
-8
70
28
5
-6
8
AS, DACK, DONE Width Asserted
–
52.5
20.5
4
–
8A
AS, DACK, DONE Width Asserted (Fast Termination Cycle)
Asynchronous Input Setup Time to CLKO1 Low
Asynchronous Input Hold Time from CLKO1 Low
DREQ Input Setup Time to CLKO1 Low
DREQ Input Hold Time from CLKO1 Low
DONE Input Setup Time to CLKO1 Low
DONE Input Hold Time From CLKO1 Low
DREQ Asserted to AS Asserted
–
–
10(1)
11(1)
12(2)
13(2)
14(2)
15(2)
16(2)
–
–
10
20
5
–
7.5
15
3.75
15
3.75
2
–
–
–
–
–
20
5
–
–
–
–
2
–
–
Notes: 1. These specifications are for asynchronous mode.
2. These specifications are for synchronous mode.
49
2113B–HIREL–06/05
Figure 7-35. IDMA Signal Asynchronous Timing Diagram
CPU_CYCLW
(IDMA RWQUWST)
IDMA_CYCLW
SE
S1
Sꢀ
S3
S4
S5
S5
SE
S1
Sꢀ
S3
S4
CLKO1
(OUTPUT)
4
1
5
DREQ
(INPUT)
6
8
3
AS
(OUTPUT)
1
2
DACK
(OUTPUT)
7
DONE
(OUTPUT)
1
DONE
(INPUT)
11
10
Figure 7-36. IDMA Signal Synchronous Timing Diagram
CPU_CYCLE
(IDMA REQUEST)
IDMA_CYCLE
S2
S5
S0
S1
S3
S4
S5
S0
S1
S2
S3
S4
CLKO1
(OUTPUT)
12
1
13
DREQ
(INPUT)
6
8
16
AS
(OUTPUT)
1
2
DACK
(OUTPUT)
7
DONE
(OUTPUT)
1
DONE
(INPUT)
15
14
50
TS68EN360
2113B–HIREL–06/05
TS68EN360
7.13 PIP/PIO Electrical Specifications
Table 7-12. GND = 0 VDC, TC = -55 to +125°C.The electrical specifications in this document are preliminary
(See Figure 7-37 to Figure 7-41)
25.0 MHz
33.34 MHz
Number Characteristic
Min
Max
Min
Max
Unit
ns
21
22
23
Data-In Setup Time to STBI Low
0
–
–
–
0
–
–
–
Data-In Hold Time to STBI High
STBI Pulse Width
2.5 – t3
1.5
2.5 – t3
1.5
clk
clk
1 CLKO1 –
5 ns
1 CLKO1 –
5 ns
24
STBO Pulse Width
–
–
–v
25
26
27
28
29
30
Data-Out Setup Time to STBO Low
Data-Out Hold Time from STBO High
STBI Low to STBO Low (Rx Interlock)
STBI Low to STBO High (Tx Interlock)
Data-In Setup Time to Clock Low
Data-In Hold Time from Clock Low
2
5
–
–
2
–
–
–
2
5
–
–
2
–
–
–
clk
clk
clk
clk
ns
–
–
2
2
20
10
15
7.5
ns
Clock High to Data-Out Valid (CPU Writes Data,
Control, or Direction)
–
25
–
25
ns
Note:
1. t3 = spec. 3 on Table 7-4.
Figure 7-37. PIP Rx (Interlock Mode)
26
25
DATA OUT
STRBO
(OUTPUT)
28
23
STRBI
(INPUT)
51
2113B–HIREL–06/05
Figure 7-38. PIP Tx (Interlock Mode)
22
21
DATA IN
23
STRBI
(INPUT)
24
STRBO
(OUTPUT)
Figure 7-39. PIP Tx (Pulse Mode)
22
21
DATA IN
23
STBI
(INPUT)
24
STBO
(OUTPUT)
52
TS68EN360
2113B–HIREL–06/05
TS68EN360
Figure 7-40. PIP Tx (Pulse Mode)
26
25
DATA OUT
24
STBO
(OUTPUT)
23
STBI
(INPUT)
Figure 7-41. Parallel I/O Data-in/Data-out Timing Diagram
CLKO1
(OUTPUT)
DATA IN
29
30
DATA OUT
31
CPU WRITE S4
7.14 Interrupt Controller AC Electrical Specifications
Table 7-13. GND = 0 VDC, TC = -55 to +125°C.The electrical specifications in this document are preliminary.
(See Figure 7-42 and Figure 7-43)
25.0 MHz
33.34 MHz
Number Characteristic
Min
Max
–
Min
Max
–
Unit
ns
35
36
37
38
Port C Interrupt Pulse Width Low (Edge Triggered Mode)
70
70
–
55
55
–
Minimum Time Between Active Edges Port C
Clock High to IOUT Valid (Slave Mode)
Clock High to RQOUT Valid (Slave Mode)
–
–
clk
ns
20
20
17
17
–
–
ns
53
2113B–HIREL–06/05
Figure 7-42. Interrupts Timing Diagram
Port C
(INPUT)
35
36
Figure 7-43. Slave Mode: Interrupts Timing Diagram
CLKO1
(OUTPUT)
IOUT2-
IOUT0
(OUTPUT)
37
RQOUT
(OUTPUT)
38
7.15 BAUD Rate Generator AC Electrical Specifications
Table 7-14. GND = 0 VDC, TC = -55 to +125°C.The electrical specifications in this document are preliminary (See Figure
7-44)
25.0 MHz
33.34 MHz
Number Characteristic
Min
Max
10
Min
Max
7.5
60
Unit
ns
50
51
52
BRGO Rise and Fall Time
–
–
BRGO Duty Cycle
BRGO Cycle
40
40
60
40
30
%
ns
Figure 7-44. Baud Rate Generator Output Signals
50
50
BRGOx
51
51
52
54
TS68EN360
2113B–HIREL–06/05
TS68EN360
7.16 Timer Electrical Specifications
Table 7-15. GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary (See Figure
7-45)
25.0 MHz
33.34 MHz
Number Characteristic
Symbol
Min
Max
–
Min
Max
–
Unit
ns
61
62
63
64
65
TIN/TGATE Rise and Fall Time
trf
–
10
1
10
1
TIN/TGATE Low Time
TIN/TGATE High Time
TIN/TGATE Cycle Time
CLKO1 High to TOUT Valid
–
–
clk
clk
clk
ns
–
2
–
2
–
–
3
–
3
–
tTO
3
25
3
22
Figure 7-45. CPM General-purpose Timers
60
CLKO1
(OUTPUT)
61
62
63
TIN/TGATE
(INPUT)
64
61
65
TOUT
(OUTPUT)
55
2113B–HIREL–06/05
7.17 SI Electrical Specifications
Table 7-16. GND = 0 VDC, TC = -55 to +125°C.The electrical specifications in this document are preliminary
(See Figure 7-46 to Figure 7-50)
25.0 MHz
33.34 MHz
Number Characteristic
Min
Max
10
–
Min
Max
10
–
Unit
MHz
ns
70(1)(3)
71(1)
71A(2)
72
L1RCLK, L1TCLK Frequency (DCS = 0)
–
P+10
P+10
–
–
P+10
P+10
–
L1RCLK, L1TCLK Width Low (DCS = 0)
L1RCLK, L1TCLK Width High (DCS = 0)
L1TXD, L1ST(1-4), L1RQ, L1CLKO Rise/Fall Time
L1RSYNC, L1TSYNC Valid to L1CLK Edge (SYNC Setup Time)
L1CLK Edge to L1RSYNC, L1TSYNC Invalid (SYNC Hold Time)
L1RSYNC, L1TSYNC Rise/Fall Time
L1RXD Valid to L1CLK Edge (L1RXD Setup Time)
L1CLK Edge to L1RXD Invalid (L1RXD Hold Time)
L1CLK Edge to L1ST(1-4) Valid
–
–
ns
15
–
15
–
ns
73
20
35
–
20
35
–
ns
74
–
–
ns
75
15
–
15
–
ns
76
42
35
10
10
10
10
10
0
42
35
10
10
10
10
10
0
ns
77
–
–
ns
78
45
45
45
65
65
42
12.5
–
45
45
45
65
65
42
16
–
ns
78A(4)
L1SYNC Valid to L1ST(1-4) Valid
ns
79
L1CLK Edge to L1ST(1-4) Invalid
ns
80
L1CLK Edge to L1TXD Valid
ns
80A(4)
L1TSYNC Valid to L1TXD Valid
ns
81
L1CLK Edge to L1TXD High Impedance
L1RCLK, L1TCLK Frequency (DSC = 1)
L1RCLK, L1TCLK Width Low (DSC = 1)
L1RCLK, L1TCLK Width High (DSC = 1)
L1CLK Edge to L1CLKO Valid (DSC = 1)
L1RQ Valid Before Falling Edge of L1TSYNC
L1GR Setup Time
ns
82
–
–
MHz
ns
83
P+10
P+10
–
P+10
P+10
–
83A(2)
–
–
ns
84
30
–
30
–
ns
85(3)
86(3)
87(3)
1
1
L1TCLK
ns
42
42
–
42
42
–
L1RG Hold Time
–
–
ns
L1CLK Edge to L1SYNC Valid (FSD = 00, CNT = 0000, BYT = 0,
DSC = 0)
88
–
0
–
0
ns
Notes: 1. The ratio SyncCLK/L1RC LK must be greater than 2.5/1.
2. Where P = 1/CLKO1. Thus for a 25 MHz CLKO1 rate, P = 40 ns.
3. These specs are valid for IDL mode only.
4. The strobes and Txd on the first bit of the frame become valid after L1CLK edge or L1SYNC, whichever is later.
56
TS68EN360
2113B–HIREL–06/05
TS68EN360
Figure 7-46. SI Receive Timing with Normal Clocking (DSC = 0)
L1RCLK
(FE = 0,CE = 0)
(INPUT)
72
70
L1RCLK
(FE =1,CE = 1)
(INPUT)
71
75
RFCD = 1
L1RSYNC
(INPUT)
73
74
77
76
L1RXD
(INPUT)
BIT0
79
78
L1ST (4-1)
(OUTPUT)
57
2113B–HIREL–06/05
Figure 7-47. SI Receive Timing with Double Speed Clocking (DSC = 1)
72
83A
L1RCLK
(FE = 0,
CE = 0)
(INPUT)
82
L1RCLK
(FE = 1,
CE = 1)
(INPUT)
75
RFCD = 1
L1RSYNC
(INPUT)
73
74
77
76
L1RXD
(INPUT)
BIT0
78
79
L1ST (4-1)
(OUTPUT)
L1CLKO
(OUTPUT)
84
58
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2113B–HIREL–06/05
TS68EN360
Figure 7-48. SI Transmit Timing with Normal Clocking (DSC = 0)
L1TCLK
(FE = 0,
CE = 0)
(INPUT)
72
70
L1TCLK
(FE = 1,
CE = 1)
(INPUT)
71
75
L1TSYNC
(OUTPUT)
73
74
TFCD = 0
81
80A
L1TXD
BIT0
(INPUT)
80
78A
79
L1ST (4-1)
(OUTPUT)
78
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2113B–HIREL–06/05
Figure 7-49. SI Transmit Timing with Double Speed Clocking (DSC = 1)
72
83A
L1RCLK
(FE = 0,
CE = 0)
(INPUT)
82
L1RCLK
(FE = 1,
CE = 1)
(INPUT)
75
L1TSYNC
(INPUT)
73
74
TFCD = 0
81
80A
L1TXD
(OUTPUT)
BIT0
80
78A
79
L1ST (1-4)
(OUTPUT)
78
L1CLKO
(OUTPUT)
84
Figure 7-50. IDL Timing SI Transmit Timing with Double Speed Clocking (DSC = 1)
74
L1RSYNC
(INPUT)
73
71
L1RCLK
(INPUT)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
M
71
80
L1TXD
(OUTPUT)
B17
B16
B15 B14 B13 B12 B11 B10 D1
72
A
A
B27 B26 B25 B24 B23 B22 B21 B20 D2
81
77
76
L1RXD
(INPUT)
B17
B16
B15 B14 B13 B12 B11 B10 D1
78
B27 B26 B25 B24 B23 B22 B21 B20 D2
M
L1ST (4-1)
(OUTPUT)
85
L1RQ
(OUTPUT)
86
87
L1GR
(INPUT)
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TS68EN360
7.18 SCC in NMSI Mode-external Clock Electrical Specifications
Table 7-17. GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary
(See Figure 7-51 to Figure 7-53)
25.0 MHz
Min
33.34 MHz
Min
Number Characteristic
Max
–
Max
–
Unit
100(1)
RCLK1 and TCLK1 Width High
CLKO1
CLKO1
101
RCLK1 and TCLK1 Width Low
CLKO1 + 5 ns
–
CLKO1 + 5 ns
–
102
RCLK1 and TCLK1 Rise/Fall Time
–
0
15
50
50
–
–
0
15
50
50
–
ns
ns
ns
ns
ns
ns
ns
103
TXD1 Active Delay (From TCLK1 Falling Edge)
RTS1 Active/Inactive Delay (From TCLK1 Falling Edge)
CTS1 Setup Time to TCLK1 Rising Edge
RXD1 Setup Time to RCLK1 Rising Edge
RXD1 Hold Time from RCLK1 Rising Edge
CD1 Setup Time to RCLK1 Rising Edge
104
0
0
105
40
40
0
40
40
0
106
–
–
107(2)
–
–
108
40
–
40
–
Notes: 1. The ratio SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 2.25/1.
2. Also applies to CD and CTS hold time when they are used as external sync signals.
7.19 SCC in NMSI Mode-internal Clock Electrical Specifications
Table 7-18. GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary
(See Figure 7-51 to Figure 7-53)
25.0 MHz
Min
33.34 MHz
Number Characteristic
Max
8.3
–
Min
Max
11
–
Unit
100(1)
RCLK1 and TCLK1 Frequency
0
–
0
–
MHz
ns
102
RCLK1 and TCLK1 Rise/Fall Time
103
TXD1 Active Delay (From TCLK1 Falling Edge)
RTS1 Active/Inactive Delay (From TCLK1 Falling Edge)
CTS1 Setup Time to TCLK1 Rising Edge
RXD1 Setup Time to RCLK1 Rising Edge
RXD1 Hold Time from RCLK1 Rising Edge
CD1 Setup Time to RCLK1 Rising Edge
0
30
30
–
0
30
–
ns
104
0
40
40
0
ns
105
40
40
0
–
ns
106
–
–
ns
107(2)
–
40
0
–
ns
108
40
–
30
ns
Notes: 1. The ratio SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 3/1.
2. Also applies to CD and CTS hold time when they are used as external sync signals.
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2113B–HIREL–06/05
Figure 7-51. SCC NMSI Receive
102
102
101
RCLK1
100
106
RXD1
(INPUT)
107
108
CD1
(INPUT)
107
CD1
(SYNC-
INPUT)
Figure 7-52. SCC NMSI Transmit
102
102
101
TCLK1
100
103
TXD1
(OUTPUT)
RTS1
(OUTPUT)
104
104
105
CTS1
(INPUT)
107
CTS1
(SYNC-
INPUT)
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TS68EN360
Figure 7-53. HDLC BUS Timing
102
103
102
101
TCLK1
100
TXD1
(OUTPUT)
RTS1
(OUTPUT)
104
104
107
105
CTS1
(ECHO
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2113B–HIREL–06/05
7.20 Ethernet Electrical Specifications
Table 7-19. GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary
(See Figure 7-54 to Figure 7-59)
25.0 MHz
33.34 MHz
Number Characteristic
Min
Max
–
Min
Max
–
Unit
ns
120
121
CLSN Width High
40
–
40
–
RCLK1 Rise/Fall Time
15
15
ns
CLKO1 +
5 ns
CLKO1 +
5 ns
122
RCLK1 Width Low
–
–
123(1)
124
RCLK1 Width High
RXD1 Setup Time
RXD1 Hold Time
CLKO1
–
–
–
CLKO1
–
–
–
20
5
20
5
ns
ns
125
RENA Active Delay (from RCLK1 rising edge of the last
data bit)
126
10
–
10
–
ns
127
128
RENA Width Low
100
–
–
100
–
–
ns
ns
TCLK1 Rise/Fall Time
15
15
CLKO1 +
5 ns
CLKO1 +
5 ns
129
TCLK1 Width Low
–
–
130(1)
131
TCLK1 Width High
CLKO1
10
10
10
10
10
10
1
–
CLKO1
10
10
10
10
10
10
1
–
TXD1 Active Delay (from TCLK1 rising edge)
TXD1 Inactive Delay (from TCLK1 rising edge)
TENA Active Delay (from TCLK1 rising edge)
TENA Inactive Delay (from TCLK1 rising edge)
RSTRT Active Delay (from TCLK1 falling edge)
RSTRT Inactive Delay (from TCLK1 falling edge)
RRJCT Width Low
50
50
50
50
50
50
–
50
50
50
50
50
50
–
ns
ns
132
133
ns
134
ns
135
ns
136
ns
137
CLKO1
ns
138(2)
139(2)
CLKO1 Low to SDACK Asserted
–
20
20
–
20
20
CLKO1 Low to SDACK Negated
–
–
ns
Notes: 1. SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 2.25/1
2. SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.
Figure 7-54. Ethernet Collision Timing
CLSN (CTS1)
(INPUT)
120
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2113B–HIREL–06/05
TS68EN360
Figure 7-55. Ethernet Receive Timing
121
122
121
RCLK1
123
124
RXD1
(INPUT)
LAST BIT
125
127
RENA (CD1)
(INPUT)
126
Figure 7-56. Ethernet Transmit Timing
128
128
129
TCLK1
(NOTE 1)
130
131
132
TXD1
(OUTPUT)
133
TENA (RTS1)
(OUTPUT)
134
RENA (CD1)
(INPUT)
(NOTE 2)
Notes: 1. Transmit clock invert (TCI) bit in GSMR is set.
2. If RENA is deasserted before TENA, or RENA is not asserted at all during transit, then CSL bit is set in the buffer descriptor
at the end of frame transmission.
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2113B–HIREL–06/05
Figure 7-57. CAM Interface Receive Start Timing
RCLK1
RXD1
(INPUT)
1
1
0
Bit # 1
Bit # 2
START FRAME DELIMITER
135
136
RSTRT
(OUTPUT)
Note:
Valid for the ethernet protocol only.
Figure 7-58. CAM Interface Reject Timing
137
RRJCT
(INPUT)
Note:
Valid for the ethernet protocol only.
Figure 7-59. SDACK Timing Diagram
SDMA CYCLE
SE
S1
Sꢀ
S3
S4
S5
CLKO1
(OUTPUT)
AS
(OUTPUT)
138
139
SDACKx
(OUTPUT)
Note:
SDACKx is asserted when the SDMA writes the received Ethernet frame into memory.
66
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7.21 SMC Transparent Mode Electrical Specifications
Table 7-20. GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary (See Figure
7-60)
25.0 MHz
33.34 MHz
Number Characteristic
Min
Max
–
Min
Max
–
Unit
ns
150(1)
SMCLK Clock Period
100
50
50
–
100
50
50
–
151
SMCLK Width Low
–
–
ns
151A
152
SMCLK Width High
–
–
ns
SMCLK Rise/Fall Time
15
50
–
15
50
–
ns
153
SMTXD Active Delay (from SMCLK falling edge)
SMRXD/SYNC1 Setup Time
SMRXD/SYNC1 Hold Time
10
20
5
10
20
5
ns
154
ns
155
–
–
ns
Note:
1. The ratio SyncCLK/SMCLK must be greater or equal to 2/1. SMC Transparent.
Figure 7-60. SMC Transparent
152
152
151A
151
SMCLK
150
TXD1
(OUTPUT)
Note 1
153
154
155
SYNC1
154
RXD1
(INPUT)
155
This delay is equal to an integer number of “Character length” clocks
Note:
67
2113B–HIREL–06/05
7.22 SPI Master Electrical Specifications
Table 7-21. GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary
(See Figure 7-61 and Figure 7-62)
25.0 MHz
33.34 MHz
Number Characteristic
Min
Max
1024
512
–
Min
Max
1024
512
–
Unit
tcyc
tcyc
ns
160
161
162
163
164
165
166
167
Master Cycle Time
4
2
4
2
Master Clock (SPICLK) High or Low Time
Master Data Setup Time (Inputs)
Master Data Hold Time (Inputs)
Master Data Valid (after SPICLK Edge)
Master Data Hold Time (Outputs)
Rise Time: Output
50
0
50
0
–
–
ns
–
20
–
–
20
–
ns
0
0
ns
15
15
15
15
ns
Fall Time: Output
ns
Figure 7-61. SPI Master (CP = 0)
167
166
SPICLK
CI=0
OUTPUT
167
161
160
SPICLK
CI=1
OUTPUT
166
161
162
163
SPIMISO
INPUT
LSB IN
MSB IN
MSB IN
DATA
165
164
SPIMOSI
OUTPUT
"1"
166
LSB OUT
DATA
MSB OUT
"1"
MSB OUT
167
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TS68EN360
Figure 7-62. SPI Master (CP = 1)
167
160
166
SPICLK
CI=0
OUTPUT
161
160
163
SPICLK
CI=1
OUTPUT
166
161
162
LSB IN
SPIMISO
DATA
DATA
MSB
MSB IN
INPUT
165
164
SPIMOSI
OUTPUT
MSB OUT
167
LSB OUT
"1"
166
MSB
"1"
7.23 SPI Slave Electrical Specifications
Table 7-22. GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary
(See Figure 7-63 and Figure 7-64)
25.0 MHz
33.34 MHz
Number Characteristic
Min
Max
Min
Max
Unit
tcyc
ns
170
171
172
173
174
175
176
177
178
179
180
181
182
Slave Cycle Time
2
15
15
1
–
2
15
15
1
–
Slave Enable Lead Time
Slave Enable Lag Time
ns
Slave Clock (SPICLK) High or Low Time
Slave Sequential Transfer Delay (Does Not Require Deselect)
Slave Data Setup Time (Inputs)
Slave Data Hold Time (Inputs)
Slave Access Time
–
–
tcyc
tcyc
ns
1
1
20
20
–
20
20
–
–
–
ns
50
50
50
–
50
50
50
–
ns
Slave SPIMISO Disable Time
Slave Data Valid (after SPICLK Edge)
Slave Data Hold Time (Outputs)
Rise Time: Input
ns
–
0
–
0
ns
ns
15
15
15
15
ns
Fall Time: Input
ns
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2113B–HIREL–06/05
Figure 7-63. SPI Slave (CP = 0)
171
172
SPISEL
INPUT
174
182
181
SPICLK
CI=0
INPUT
173
170
SPICLK
CI=1
INPUT
181
179
173
182
180
180
177
178
SPIMISO
MSB OUT
OUTPUT
DATA
LSB OUT
181
UNDEF.
182
MSB OUT
176
175
SPIMOSI
MSB IN
DATA
LSB IN
MSB IN
INPUT
Figure 7-64. SPI Slave (CP = 1)
SPISEL
INPUT
174
182
170
181
173
SPICLK
CI=0
INPUT
172
173
171
SPICLK
CI=1
INPUT
181
182
180
SLAVE
179
179
177
178
SPIMISO
UNDEF.
OUTPUT
MSB OUT
DATA
UNDEF.
LSB OUT
181
176
175
SPIMOSI
INPUT
MSB IN
DATA
LSB IN
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TS68EN360
7.24 JTAG Electrical Specifications
Table 7-23. GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary
(See Figure 7-65 and Figure 7-68)
25.0 MHz
33.34 MHz
Number Characteristic
TCK Frequency of Operation
Min
Max
25
–
Min
Max
25
–
Unit
MHz
ns
0
40
18
0
0
40
18
0
1
2
TCK Cycle Time in Crystal Mode
TCK Clock Pulse Width Measured at 1.5V
TCK rise and Fall Times
–
–
ns
3
3
3
ns
6
Boundary Scan Input Data Setup Time
Boundary Scan Input Data Hold Time
TCK Low to Output Data Valid
TCK Low to Output High Impedance
TMS, TDI Data Setup Time
10
18
0
–
10
18
0
–
ns
7
–
–
ns
8
30
40
–
30
40
–
ns
9
0
0
ns
10
11
12
13
14
15
10
10
0
10
10
0
ns
TMS, TDI Data Hold Time
–
–
ns
TCK Low to TDO Data Valid
20
20
–
20
20
–
ns
TCK Low to TDO High Impedance
TRST Assert Time
0
0
ns
100
40
100
40
ns
TRST Setup Time to TCK Low
–
–
ns
Figure 7-65. Test Clock Input Timing Diagram
1
2
2
V
IH
TCK
(INPUT)
VM
VM
V
IL
3
3
Figure 7-66. TRST Timing Diagram
TCK
(INPUT)
15
TRST
(INPUT)
14
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2113B–HIREL–06/05
Figure 7-67. Boundary Scan (JTAG) Timing Diagram
V
IH
TCK
(INPUT)
V
IL
6
7
DATA
INPUTS
INPUT DATA VALID
8
DATA
OUTPUTS
OUTPUT DATA VALID
9
8
DATA
OUTPUTS
DATA
OUTPUTS
OUTPUT DATA VALID
Figure 7-68. Test Access Port Timing Diagram
V
IH
TCK
(INPUT)
V
IL
10
11
TDI
TMS
INPUT DATA VALID
(INPUT)
12
TDO
(OUTPUT)
OUTPUT DATA VALID
13
12
TDO
(OUTPUT)
TDO
(OUTPUT)
OUTPUT DATA VALID
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TS68EN360
8. Functional Description
8.1
CPU32+ Core
The CPU32+ core is a CPU32 that has been modified to connect directly to the 32-bit IMB and
apply the larger bus width. Although the original CPU32 core had a 32-bit internal data path and
32-bit arithmetic hardware, its interface to the IMB was 16 bits. The CPU32+ core can operate
on 32-bit external operands with one bus cycle. This allows the CPU32+ core to fetch a long-
word instruction in one bus cycle an to fetch two word-length instructions in one bus cycle, filling
the internal instruction queue more quickly. The CPU32+ core can also read and write 32-bit of
data in one bus cycle.
Although the CPU32+ instruction timings are improved, its instruction set is identical to that of
the CPU32. It will also execute the entire 68000 instruction set. It contains the same background
debug mode (BDM) features as the CPU32. No new compilers, assemblers or other software
support tools need be implemented for the CPU32+; standard CPU32 tools can be used.
The CPU32+ delivers approximately 4.5 MIPS at 25 MHz, based on the standard (accepted)
assumption that a 10-MHz 68000 delivers 1 VAX MIPS. If an application requires more perfor-
mance, the CPU32+ can be disabled, allowing the rest of the QUICC to operate as an intelligent
peripheral to a faster processor. The QUICC provides a special mode called TS68040 compan-
ion mode to allow it to conveniently interface to members of the TS68040 family. This two-chip
solution provides a 22-MIPS performance at 25 MHz.
The CPU32+ also offers automatic byte alignment features that are not offered on the CPU32.
These features allow 16- or 32-bit data to be read or written at an odd address. The CPU32+
automatically performs the number of bus cycles required.
8.2
System Integration Module (SIM60)
The SIM60 integrates general-purpose features that would be useful in almost any 32-bit pro-
cessor system. The term “SIM60” is derived from the QUICC part number, TS68EN360. The
SIM60 is an enhanced version of the SIM40 that exists on the TS68332 device.
First, new features, such as a DRAM controller and breakpoint logic, have been added. Second,
the SIM40 was modified to support a 32-bit IMB as well as a 32-bit external system bus. Third,
new configurations, such as slave mode and internal accesses by an external master, are
supported.
Although the QUICC is always a 32-bit device internally, it may be configured to operate with a
16-bit data bus. Regardless of the choice of the system bus size, dynamic bus sizing is sup-
ported. Bus sizing allows 8-16-, and 32-bit peripherals and memory to exist in the 32-bit system
bus mode and 8- and 16-bit peripherals and memory to exist in the 16-bit system bus mode.
8.3
Communications Processor Module (CPM)
The CPM contains features that allow the QUICC to excel in communications and control appli-
cations. These features may be divided into three sub-groups:
• Communications Processor (CP)
• Two IDMA Controllers
• Four General-purpose Timers
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2113B–HIREL–06/05
The CP provides the communication features of the QUICC. Included are a RISC processor,
four SCCs, two SMCs, one SPI, 2.5K bytes of dual-port RAM, an interrupt controller, a time slot
assigner, three parallel ports, a parallel interface port, four independent baud rate generators,
and fourteen serial DMA channels to support the SCCs, SMCs, and SPI.
The IDMAs provide two channels of general-purpose DMA capability. They offer high-speed
transfers, 32-bit data movement, buffer chaining, and independent request and acknowledge
logic. The RISC controller may access the IDMA registers directly in the buffer chaining modes.
The QUICC IDMAs are similar to, yet enhancements of, the one IDMA channel found on the
TS68302.
The four general-purpose timers on the QUICC are functionally similar to the two general-pur-
pose timers found on the TS68302. However, they offer some minor enhancements, such as the
internal cascading of two timers to form a 32-bit timer. The QUICC also contains a periodic inter-
val timer in the SIM60, bringing the total to five on-chip timers.
8.4
Ethernet on QUICC
The Ethernet protocol is available only on the Ethernet version of the QUICC called the
TS68EN360. The non-Ethernet version of the QUICC is the MC68360. The term “QUICC” is the
overall device name that denotes all versions of the device.
The TS68EN360 is a superset of the MC68360, having the additional option allowing Ethernet
operation on any of the four SCCs. Due to performance reason not ass SCCs can be configured
as Ethernet controller at the same time. The TS68EN360 is not restricted only to Ethernet oper-
ation. HDLC, UART, and other protocols may be used to allow dynamic switching between
protocols. See Appendix A Serial Performance for available SCC performance.
When the MODE bits of the SCC GSMR select the Ethernet protocol, then that SCC performs
the full set of IEEE 802.3/Ethernet CSMA/CD media access control and channel interface func-
tions (see Figure 8-1)
Figure 8-1. Ethernet Block Diagram
IMB
SLOT TIME
AND DEFER
COUNTER
CONTROL
REGISTERS
RX CLOCK
TX CLOCK
PERIPHERAL BUS
CLOCK
GENERATOR
INTERNAL CLOCKS
RTS = TENA
RRJCT
RECEIVER
RSTRT
RECEIVE
DATA
FIFO
TRANSMIT
DATA
FIFO
TRANSMITTER
CD = RENA
CTS = CLSN
CONTROL
CONTROL
UNIT
CD = RENA
CTS = CLSN
UNIT
TXD
RXD
SHIFTER
SHIFTER
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8.5
Upgrading Designs from the TS68302
Since the QUICC is a next-generation TS68302, many designers currently using the TS68302
may wish to use the QUICC in a follow-on design. The following paragraphs briefly discuss this
endeavor in terms of architectural approach, hardware issues, and software issues.
8.5.1
Architectural Approach
The QUICC is the logical extension of the TS86302, but the overall architecture and philosophy
of the TS86302 design remains intact in the QUICC. The QUICC keeps the best features of the
TS86302, while making the changes required to provide for the increased flexibility, integration,
and performance requested by customers. Because the CPM is probably the most difficult mod-
ule to learn, anyone who has used the TS86302 can easily become familiar with the QUICC
since the CPM architectural approach remains intact.
The most significant architectural change made on the QUICC was the translation of the design
into the standard 68300 family IMB architecture, resulting in a faster CPU and different system
integration features.
Although the features of the SIM60 do not exactly correspond to those of the TS86302 SIM, they
are very similar.
Because of the similarity of the QUICC SIM60 and CPU to other members of the 68300 family,
such as the TS68332, previous users of these devices will be comfortable with these same fea-
tures on the QUICC.
8.5.2
Hardware Compatibility Issues
The following list summarizes the hardware differences between the TS86302 and the QUICC:
• Pinout – The pinout is not the same. The QUICC has 240 pins; the TS86302 has 132 pins
• Package – Both devices offer PGA and PQFP packages. However, the QUICC QFP package
has a 20-mil pitch; whereas, the TS86302 QFP package has a 25-mil pitch
• System Bus – The system bus signals now look like those of the TS68020 as opposed to
those of the 68000. It is still possible to interface 68000 peripherals to the QUICC, utilizing the
same techniques used to interface them to a TS68020
• System Bus in Slave Mode – A number of QUICC pins take on new functionality in slave
mode to support an external TS68EC040. On the TS68302, the pin names generally
remained the same in slave mode
• Peripheral Timing – The external timings of the peripherals (SCCs, timers, etc.) are very
similar (if not identical) to corresponding peripherals on the TS68302
• Pin Assignments – The assignment of peripheral functions to I/O pins is different in several
ways. First, the QUICC contains more general-purpose parallel I/O pins than the TS68302.
However, the QUICC offers many more functions than even a 240-pin package would
normally allow, resulting in more multifunctional pins than the TS68302
8.5.3
Software Compatibility Issues
The following list summarizes the major software differences between the TS68302 and the
QUICC:
• Since the CPU32+ is a superset of the 68000 instruction set, all previously written code will
run. However, if such code is accessing the TS68302 peripherals, it will require some
modification
75
2113B–HIREL–06/05
• The QUICC contains an 8-Kbyte block of memory as opposed to a 4-Kbyte block on the
TS68302. The register addresses within that memory map are different
• The code used to initialize the system integration features of the TS68302 has to be modified
to write the corresponding features on the QUICC SIM60
• As much as possible, QUICC CPM features were made identical to those of the TS68302 CP.
The most important benefit is that the code flow (if not the code itself) will port easily from the
TS68302 to the QUICC. The nuances learned from the TS68302 will still be useful in the
QUICC
• Although the registers used to initialize the QUICC CPM are new (for example, the SCM on
the TS68302 is replaced with the GSMR and PSMR on the QUICC), most registers retain
their original purpose such as the SCC event, SCC mask, SCC status, and command
registers. The parameter RAM of the SCCs is very similar, and most parameter RAM register
names and usage are retained. More importantly, the basic structure of a buffer descriptor
(BD) on the QUICC is identical to that of the TS68302, except for a few new bit functions that
were added. (In a few cases, a bit in a BD status word had to be shifted)
• When porting code from the TS68302 CP to the QUICC CPM, the software writer may find
that the QUICC has new options to simplify what used to be a more code-intensive process.
For specific examples, see the INIT TX AND RX PARAMETERS, GRACEFUL STOP
TRANSMIT, and CLOSE BD commands
9. Preparation for Delivery
9.1
Packaging
Microcircuits are prepared for delivery in accordance with MIL-PRF-38535 or Atmel standards.
9.2
Certificate of Compliance
Atmel offers a certificate of compliances with each shipment of parts, affirming the products are
in compliance either with MIL-STD-883 or Atmel standard and guarantying the parameters not
tested at temperature extremes for the entire temperature range.
10. Handling
MOS devices must be handled with certain precautions to avoid damage due to accumulation of
static charge. Input protection devices have been designed in the chip to minimize the effect of
this static buildup. However, the following handling practices are recommended:
a) Devices should be handled on benches with conductive and grounded surfaces
b) Ground test equipment, tools and operator
c) Do not handle devices by the leads
d) Store devices in conductive foam or carriers
e) Avoid use of plastic, rubber, or silk in MOS areas
f) Maintain relative humidity above 50% if practical
76
TS68EN360
2113B–HIREL–06/05
TS68EN360
11. Package Mechanical Data
11.1 241-pin – PGA
Inches
Millimeters
Dim
A
Min
Max
Min
46.74
2.79
Max
47.75
3.56
0.51
1.4
1.840
0.110
0.016
0.045
0.045
1.880
0.140
0.020
0.055
0.055
C
(top view)
D
0.41
E
1.143
1.143
F
1.4
G
K
0.100 BASIC
0.150 0.170
2.54 BASIC
3.81
4.32
C
G
W
T
(BOTTOM VIW/)
A
1
12
A
K
77
2113B–HIREL–06/05
11.2 240-pin – CERQUAD
VIEW AC
S
VIEW AC
4 PLACES
U
AD
AD
180
121
181
120
X = L, M or N
–X–
SECTION AD
240 PLACES
F
D
M
S
S
M
0.08(0.003)
T L–N
240
61
1
60
MILLIMETERS
INCHES
–M–
A
DIM
A
MIN
30.86
30.86
3.67
0.20
3.10
0.19
MAX
31.75
31.75
4.15
MIN
1.215
1.215
0.144
0.0079
0.122
0.0075
MAX
1.250
1.250
0.163
0.012
0.154
0.010
4 x 60 TIPS
S
S
M
M
0.25(0.010) T L–N M
0.20(0.008)
H L–N
B
C
DATUM
PLANE
–H–
–T–
D
0.30
0.10(0.004)
E
3.90
SEATING
PLANE
AB
F
0.25
VIEW AE
G
J
0.50 BSC
0.019 BSC
VIEW AE
0.13
0.45
0.175
0.55
0.005
0.018
0.007
0.021
θ2
K
DATUM
–H–
PLANE
P
0.25 BSC
0.15 BSC
34.41 34.75
17.30 BSC
0.010 BSC
0.006 BSC
1.355 1.37
0.681 BSC
R
S
K
AA
U
V
34.41
34.75
0.75
1.355
1.37
Notes: 1. Dimensioning and tolerancing per ASME Y 14.5, 1994.
2. Controlling dimension: millimeter.
W
Y
0.25
0.0035
0.0232
3. Datum plane -H- is located at bottom of lead and is coincident with the
lead where the lead exits the ceramic body at the bottom of the parting
line.
4. Datums -L-, -M- and -N- to be determined at datum plane -H-.
5. Dimensions S and V to be determined at seating plane -T-.
6. Dimensions A and B define maximum ceramic body dimensions
including glass protrusion and top and bottom mismatch.
17.30 BSC
0.681 BSC
Z
0.12
0.13
0.005
0.005
AA
AB
θ2
1.80 REF
0.95 REF
1° 7°
0.071 REF
0.037 REF
1° 7°
78
TS68EN360
2113B–HIREL–06/05
TS68EN360
12. Ordering Information
12.1 Hi-REL Product
Commercial Atmel
Part-Number
Temperature
Range Tc (°C)
Frequency
(MHz)
Norms
Package
DSCC
TS68EN360MRB/Q25L
TS68EN360MRB/Q33L
TS68EN360MR1B/Q25L
TS68EN360MR1B/Q33L
TS68EN360MAB/Q25L
TS68EN360MAB/Q33L
MIL-PRF-38535
MIL-PRF-38535
MIL-PRF-38535
MIL-PRF-38535
MIL-PRF-38535
MIL-PRF-38535
PGA 241 Gold
PGA 241 Gold
PGA 241 Tinned
PGA 241 Tinned
CERQUAD 240
CERQUAD 240
-55/+125
-55/+125
-55/+125
-55/+125
-55/+125
-55/+125
25
33
25
33
25
33
5962-9760701MXC
5962-9760702MXC
5962-9760701MXA
5962-9760702MXA
5962-9760701MYA
5962-9760702MYA
12.2 Standard Product
Commercial Atmel
Part-Number
Temperature
Range Tc (°C)
Frequency
(MHz)
Norms
Package
PGA 241
Drawing Number
Internal
TS68EN360VR25L
TS68EN360MR25L
TS68EN360VA25L
TS68EN360MA25L
TS68EN360VR33L
TS68EN360MR33L
TS68EN360VA33L
TS68EN360MA33L
Atmel Standard
Atmel Standard
Atmel Standard
Atmel Standard
Atmel Standard
Atmel Standard
Atmel Standard
Atmel Standard
-40/+85
-55/+125
-40/+85
-55/+125
-40/+85
-55/+125
-40/+85
-55/+125
25
25
25
25
33
33
33
33
PGA 241
Internal
CERQUAD 240
CERQUAD 240
PGA 241
Internal
Internal
Internal
PGA 241
Internal
CERQUAD 240
CERQUAD 240
Internal
Internal
(TSX) TS68EN360
M
R
1
B/Q 25
L
Prototype version
Generic
Revision level
Temperature range : (TC
M : -55˚C, +125˚C
V : -40˚C, +110˚C
)
Operating frequency :
25 : 25 MHz
33 : 33 MHz
Screening :
Package :
R = Pin grid array 241 (gold)
A = CERQUAD 240 (tin)
___ = Standard
B/Q = MIL-PRF-38535
Hirel lead finish :
_ = Gold (for PGA)
_ = Hot solder dip (for CERQUAD)
1 =
Hot solder dip (for PGA - On request)
79
2113B–HIREL–06/05
13. Document Revision History
Table 13-1 provides a revision history for this hardware specification.
Table 13-1. Revision History
Revision Number
2113B
Date
Substantive Change(s)
Cerquad Package Change. See page 77
Initial Revision
04/2005
03/2002
2113A
80
TS68EN360
2113B–HIREL–06/05
TS68EN360
Table of Contents
Features .................................................................................................... 1
Description ............................................................................................... 1
Screening/Quality
1
1
Introduction .............................................................................................. 2
1.1 QUICC Architecture Overview ..................................................................................2
2
3
Pin Assignments ...................................................................................... 3
Signal Description ................................................................................... 5
3.1 Functional Signal Group ...........................................................................................5
3.2 Signal Index ..............................................................................................................6
4
5
Detailed Specification ............................................................................ 11
Applicable Documents .......................................................................... 11
5.1 Design and Construction ........................................................................................11
5.2 Absolute Maximum Ratings ....................................................................................11
5.3 Power Considerations ............................................................................................12
5.4 Mechanical and Environment .................................................................................13
5.5 Marking ...................................................................................................................13
6
7
Quality Conformance Inspection .......................................................... 13
6.1 DESC/MIL-STD-883 ...............................................................................................13
Electrical Characteristics ...................................................................... 13
7.1 General Requirements ...........................................................................................13
7.2 Static Characteristics ..............................................................................................14
7.3 Dynamic Characteristics .........................................................................................14
7.4 AC Power Dissipation .............................................................................................16
7.5 AC Electrical Specifications Control Timing ...........................................................17
7.6 External Capacitor For PLL ....................................................................................18
7.7 Bus Operation AC Timing Specifications ................................................................19
7.8 Bus Operation – DRAM Accesses AC Timing Specification ..................................35
7.9 040 Bus Type Slave Mode Bus Arbitration AC Electrical Specifications ................39
7.10 040 Bus Type Slave Mode Internal Read/Write/Lack Cycles AC Electrical
Specifications ................................................................................................40
7.11 040 Bus Type SRAM/DRAM Cycles AC Electrical Specifications ........................43
7.12 IDMA AC Electrical Specifications ........................................................................49
i
2113B–HIREL–06/05
7.13 PIP/PIO Electrical Specifications ..........................................................................51
7.14 Interrupt Controller AC Electrical Specifications ...................................................53
7.15 BAUD Rate Generator AC Electrical Specifications .............................................54
7.16 Timer Electrical Specifications ..............................................................................55
7.17 SI Electrical Specifications ...................................................................................56
7.18 SCC in NMSI Mode-external Clock Electrical Specifications ...............................61
7.19 SCC in NMSI Mode-internal Clock Electrical Specifications ................................61
7.20 Ethernet Electrical Specifications .........................................................................64
7.21 SMC Transparent Mode Electrical Specifications ................................................67
7.22 SPI Master Electrical Specifications .....................................................................68
7.23 SPI Slave Electrical Specifications .......................................................................69
7.24 JTAG Electrical Specifications ............................................................................71
8
9
Functional Description .......................................................................... 73
8.1 CPU32+ Core .........................................................................................................73
8.2 System Integration Module (SIM60) .......................................................................73
8.3 Communications Processor Module (CPM) ...........................................................73
8.4 Ethernet on QUICC ................................................................................................74
8.5 Upgrading Designs from the TS68302 ...................................................................75
Preparation for Delivery ........................................................................ 76
9.1 Packaging ...............................................................................................................76
9.2 Certificate of Compliance .......................................................................................76
10 Handling .................................................................................................. 76
11 Package Mechanical Data ..................................................................... 77
11.1 241-pin – PGA .....................................................................................................77
11.2 240-pin – CERQUAD ...........................................................................................78
12 Ordering Information ............................................................................. 79
12.1 Hi-REL Product ....................................................................................................79
12.2 Standard Product .................................................................................................79
13 Document Revision History .................................................................. 80
ii
TS68EN360
2113B–HIREL–06/05
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