AT22LV10L-25JI [ATMEL]

Low-Voltage UV Erasable Programmable Logic Device; 低压紫外线擦除可编程逻辑器件
AT22LV10L-25JI
型号: AT22LV10L-25JI
厂家: ATMEL    ATMEL
描述:

Low-Voltage UV Erasable Programmable Logic Device
低压紫外线擦除可编程逻辑器件

可编程逻辑器件 输入元件 时钟
文件: 总11页 (文件大小:510K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
Features  
Low Voltage Programmable Logic Device  
– Wide Power Supply Range - 3.0V to 5.5V  
– Ideal for Battery Powered Systems  
High Speed Operation  
– 20 ns max Propagation Delay at VCC = 3.0V  
Commercial and Industrial Temperature Ranges  
Familiar 22V10 Logic Architecture  
Low Power 3-Volt CMOS Operation  
Low-Voltage UV  
Erasable  
AT22LV10L  
Com./Ind.  
4 / 5  
AT22LV10  
Com./Ind.  
35 / 45  
Temp  
ICC (mA)  
VCC = 3.6V  
Programmable  
Logic Device  
CMOS and TTL Compatible Inputs and Outputs  
– 10 µA Leakage Maximum  
Reprogrammable - Tested 100% for Programmability  
High Reliability CMOS Technology  
– 2000V ESD Protection  
– 200 mA Latchup Immunity  
Dual-In-Line and Surface Mount Packages  
AT22LV10  
AT22LV10L  
Logic Diagram  
Description  
The AT22LV10 and AT22LV10L are low voltage compatible CMOS high performance  
Programmable Logic Devices (PLDs). Speeds down to 20 ns and power dissipation  
as low as 14.4 mW are offered. All speed ranges are specified over the 3.0V to 5.5V  
range. All pins offer a low ±10 µA leakage.  
(continued)  
Pin Configurations  
DIP/SOIC  
PLCC  
Pin Name Function  
CLK/IN  
IN  
Clock and Logic Input  
Logic Inputs  
I/O  
Bidirectional Buffers  
No Internal Connection  
3.0V to 5.5V Supply  
*
VCC  
Rev. 0190C—05/98  
The AT22LV10L provides the optimum low power CMOS  
PLD solution, with low DC power (1 mA typical at VCC  
Absolute Maximum Ratings*  
=
Temperature Under Bias ................................ -55°C to +125°C  
3.3V) and full CMOS output levels. The AT22LV10L signifi-  
cantly reduces total system power, allowing battery pow-  
ered operation.  
Storage Temperature ..................................... -65°C to +150°C  
Full CMOS output levels help reduce power in many other  
system components.  
Voltage on Any Pin with  
Respect to Ground........................................ -2.0V to +7.0V (1)  
The AT22LV10 and AT22LV10L logic architectures are  
identical to the familiar 22V10. Each output is allocated  
from eight to 16 product terms, which allows highly com-  
plex logic functions to be realized.  
Voltage on Input Pins  
with Respect to Ground  
During Programming................................... -2.0V to +14.0V (1)  
Two additional product terms are included to provide syn-  
chronous preset and asynchronous reset. These terms are  
common to all ten registers. All registers are automatically  
cleared upon power up.  
Programming Voltage with  
Respect to Ground...................................... -2.0V to +14.0V (1)  
Integrated UV Erase Dose ............................. 7258 Wsec/cm2  
Register preload simplifies testing. A security fuse prevents  
unauthorized copying of programmed fuse patterns.  
*NOTICE:  
Stresses beyond those listed under “Absolute Maxi-  
mum Ratings” may cause permanent damage to the  
device. This is a stress rating only and functional  
operation of the device at these or any other condi-  
tions beyond those indicated in the operational sec-  
tions of this specification is not implied. Exposure to  
absolute maximum rating conditions for extended  
periods may affect device reliability.  
Note:  
1. Minimum voltage is -0.6V dc whihc may undershoot  
to -2.0V for pulses of less than 20 ns. Maximum pin  
voltage is VCC + 0.75V dc which may undershoot to  
VCC + 2.0V for pulses of less than 20 ns.  
Logic Options  
Output Options  
DC and AC Operating Conditions  
Commercial  
Industrial  
-40°C - 85°C  
3.0V to 5.5V  
Operating Temperature (Case)  
VCC Power Supply  
0°C - 70°C  
3.0V to 5.5V  
AT22LV10(L)  
2
AT22LV10(L)  
DC Characteristics  
Symbol Parameter  
Condition  
Min  
Typ  
Max  
Units  
ILI  
Input Load Current  
VIN = -0.1V to VCC + 1V  
10  
µA  
Output Leakage  
Current  
ILO  
VOUT = -0.1V to VCC + 0.1V  
10  
µA  
Com.  
Ind.  
20/50  
20/50  
1/2  
35/90  
45/100  
4/12  
mA  
mA  
mA  
mA  
AT22LV10  
VCC = 3.6V / 5.5V,  
VIN = GND,  
Outputs Open  
Power Supply  
Current  
ICC  
Com.  
Ind.  
AT22LV10L  
1/2  
5/15  
Output Short Circuit  
Current  
(1)  
IOS  
VOUT = 0.5V  
-120  
mA  
VIL1  
VIL2  
VIH  
Input Low Voltage  
Input Low Voltage  
Input High Voltage  
4.5V VCC 5.5V  
3.0V VCC < 4.5V  
-0.6  
-0.6  
2.0  
0.8  
0.6  
V
V
V
V
V
V
V
V
VCC + 0.75  
0.5  
VCC = 3.0V  
Com.,Ind.  
Com.,Ind.  
Com.,Ind.  
IOH = -100 µA  
IOL = 8 mA  
IOL = 16 mA  
IOL = 6 mA  
Output Low Voltage  
VIN = VIH or VIL  
VOL  
V
CC = 4.5V  
CC = 3.0V  
0.5  
V
0.35  
VCC - 0.3  
2.4  
VIN = VIH or VIL,  
VCC = 3.0V / 4.5V  
VOH  
Output High Voltage  
I
OH = -0.4 mA / -4.0 mA  
Note:  
1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.  
3
AC Characteristics for the AT22LV10  
AT22LV10-20  
Typ  
AT22LV10-25  
Typ  
Symbol  
Parameter  
Min  
Max  
Min  
Max  
Units  
Input or Feedback to Non-  
Registered Output  
tPD  
12  
20  
15  
25  
ns  
tEA  
tER  
tCF  
tCO  
tS  
Input to Output Enable  
Input to Output Disable  
Clock to Feedback  
Clock to Output  
20  
20  
9
15  
15  
5
25  
25  
9
ns  
ns  
0
0
4
8
6
0
0
ns  
14  
10  
7
17  
ns  
Input or Feedback Setup Time  
Hold Time  
10  
0
12  
0
ns  
tH  
ns  
tP  
Clock Period  
10  
5
12  
6
ns  
tW  
Clock Width  
ns  
External Feedback 1/(tS+tCO  
)
41.6  
52.6  
34.5  
47.6  
83.3  
MHz  
MHz  
MHz  
ns  
FMAX  
Internal Feedback 1/(tS + tCF  
No Feedback 1/(tP)  
)
100.0  
tAW  
tAR  
Asynchronous Reset Width  
20  
20  
12  
12  
25  
25  
15  
15  
Asynchronous Reset,  
Synchronous Preset,  
Recovery Time  
ns  
ns  
Asynchronous Reset to  
Registered Output Reset  
tAP  
15  
25  
18  
28  
AC Waveforms(1)  
Note:  
1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.  
AT22LV10(L)  
4
AT22LV10(L)  
AC Characteristics for the AT22LV10L  
AT22LV10L-25  
Symbol  
tPD  
tEA  
tER  
tCF  
tCO  
tSF  
Parameter  
Min  
Typ  
15  
15  
15  
5
Max  
25  
25  
25  
9
Units  
ns  
Input or Feedback to Non-Registered Output  
Input to Output Enable  
Input to Output Disable  
Clock to Feedback  
Clock to Output  
ns  
ns  
0
0
ns  
10  
7
14  
ns  
Feedback Setup Time  
Input Setup Time  
12  
17  
0
ns  
tS  
15  
ns  
tH  
Hold Time  
ns  
tP  
Clock Period  
12  
6
ns  
tW  
Clock Width  
ns  
External Feedback 1/(tS + tCO  
)
32.2  
47.6  
83.3  
MHz  
MHz  
MHz  
ns  
FMAX  
Internal Feedback 1/(tSF + tCF  
No Feedback 1/(tP)  
)
tAW  
tAR  
tAP  
Asynchronous Reset Width  
25  
25  
15  
15  
18  
Asynchronous Reset Recovery Time  
ns  
Asynchronous Reset to Registered Output Reset  
28  
ns  
Input Test Waveforms and  
Measurement Levels  
Output Test Loads:  
Commercial  
5
Functional Logic Diagram AT22LV10(L)  
AT22LV10(L)  
6
AT22LV10(L)  
Preload of Registered Outputs  
The registers in the AT22LV10 and AT22LV10L are pro-  
vided with circuitry to allow loading of each register asyn-  
chronously with either a high or a low. This feature will  
simplify testing since any state can be forced into the regis-  
ters to control test sequencing. A VIH level on the I/O pin  
will force the register high; a VIL will force it low, indepen-  
dent of the polarity bit (C0) setting. The preload state is  
entered by placing an 11.5V to 13V signal on pin 8 on  
DIPs, and pin 10 on SMPs. When the clock pin is pulsed  
high, the data on the I/O pins is placed into the ten regis-  
ters.  
Level forced on registered output  
pin during preload cycle  
Register state after  
cycle  
VIH  
VIL  
High  
Low  
Power-Up Reset  
The registers in the AT22LV10 and AT22LV10L are  
designed to reset during power up. At a point delayed  
slightly from VCC crossing 2.5V, all registers will be reset  
to the low state. The output state will depend on the polarity  
of the output buffer.  
This feature is critical for state machine initialization. How-  
ever, due to the asynchronous nature of reset and the  
uncertainty of how VCC actually rises in the system, the fol-  
lowing conditions are required:  
1. The VCC rise must be monotonis;  
2. After reset occurs, all input and feedback setup  
times must be met before driving the clock pin high,  
and  
Parameter  
Description  
Min  
Typ  
Max  
Units  
Power-Up  
Reset Time  
tPR  
600  
1000  
ns  
3. The clock must remain stable during tPR  
.
Pin Capacitance (f = 1 MHz, T = 25°C)(1)  
Typ  
Max  
Units  
pF  
Conditions  
VIN = 0V  
CIN  
COUT  
Note:  
5
6
8
8
pF  
VOUT = 0V  
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.  
Erasure Characteristics  
The entire fuse array of an AT22LV10 or AT22LV10L is  
erased after exposure to ultraviolet light at a wavelength of  
2537 Å. Complete erasure is assured after a minimum of  
20 minutes exposure using 12,000 µW/cm2 intensity lamps  
spaced one inch away from the chip. Minimum erase time  
for lamps at other intensity ratings can be calculated from  
the minimum integrated erasure dose of 15 Wsec/cm2. To  
prevent unintentional erasure, an opaque label is recom-  
mended to cover the clear window on any UV erasable  
PLD which will be subjected to continuous fluorescent  
indoor lighting or sunlight.  
7
AT22LV10(L)  
8
AT22LV10(L)  
9
Ordering Information  
tPD  
tS  
tCO  
(ns)  
(ns)  
(ns)  
Ordering Code  
Package  
Operation Range  
20  
25  
25  
10  
12  
17  
14  
17  
14  
AT22LV10-20JC  
AT22LV10-20PC  
AT22LV10-20SC  
28J  
24P3  
24S  
Commercial  
(0°C to 70°C)  
AT22LV10-20JI  
AT22LV10-20PI  
AT22LV10-20SI  
28J  
24P3  
24S  
Industrial  
(-40°C to 85°C)  
AT22LV10-25JC  
AT22LV10-25PC  
AT22LV10-25SC  
28J  
24P3  
24S  
Commercial  
(0°C to 70°C)  
AT22LV10-25JI  
AT22LV10-25PI  
AT22LV10-25SI  
28J  
24P3  
24S  
Industrial  
(-40°C to 85°C)  
AT22LV10L-25JC  
AT22LV10L-25PC  
AT22LV10L-25SC  
28J  
24P3  
24S  
Commercial  
(0°C to 70°C)  
AT22LV10L-25JI  
AT22LV10L-25PI  
AT22LV10L-25SI  
28J  
24P3  
24S  
Industrial  
(-40°C to 85°C)  
Package Type  
28J  
28-Lead, Plastic J-Leaded Chip Carrier OTP (PLCC)  
24P3  
24S  
24-Lead, 0.300" Wide, Plastic Dual Inline Package OTP (PDIP)  
24-Lead, 0.300" Wide, Plastic Gull Wing Small Outline OTP (SOIC)  
AT22LV10(L)  
10  
AT22LV10(L)  
Packaging Information  
28J, 28-Lead, Plastic J-Leaded Chip Carrier (PLCC)  
24P3, 24-Lead, 0.300” Wide. Plastic Dual Inline  
Dimensions in Inches and (Millimeters)  
JEDEC STANDARD MS-018 AB  
Package (PDIP)  
Dimensions in Inches and (Millimeters)  
JEDEC STANDARD MS-011 AB  
1.27(32.3)  
1.25(31.7)  
.045(1.14) X 30° - 45°  
.045(1.14) X 45° PIN NO. 1  
IDENTIFY  
.012(.305)  
.008(.203)  
PIN  
1
.266(6.76)  
.250(6.35)  
.430(10.9)  
.390(9.91)  
.021(.533)  
.013(.330)  
SQ  
.456(11.6)  
.450(11.4)  
SQ  
.032(.813)  
.026(.660)  
.495(12.6)  
.485(12.3)  
.090(2.29)  
SQ  
MAX  
1.100(27.94) REF  
.200(5.06)  
MAX  
.005(.127)  
MIN  
.050(1.27) TYP  
.043(1.09)  
.300(7.62) REF SQ  
.020(.508)  
.120(3.05)  
.090(2.29)  
SEATING  
PLANE  
.180(4.57)  
.165(4.19)  
.070(1.78)  
.020(.508)  
.023(.584)  
.014(.356)  
.151(3.84)  
.125(3.18)  
.065(1.65)  
.040(1.02)  
.022(.559) X 45° MAX (3X)  
.110(2.79)  
.090(2.29)  
.325(8.26)  
.300(7.62)  
0
15  
REF  
.012(.305)  
.008(.203)  
.400(10.2) MAX  
24S, 24-Lead, 0.300” Wide, Plastic Gull Wing Small  
Outline (SOIC)  
Dimensions in Inches and (Millimeters)  
.020(.508)  
.013(.330)  
.299(7.60) .420(10.7)  
.291(7.39) .393(9.98)  
PIN 1 ID  
.050(1.27) BSC  
.616(15.6)  
.105(2.67)  
.598(15.2)  
.092(2.34)  
.012(.305)  
.003(.076)  
.013(.330)  
.009(.229)  
.050(1.27)  
0
REF  
.015(.381)  
8
11  

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