AT24C02B-10TQ-2.7 [ATMEL]
EEPROM, 256X8, Serial, CMOS, PDSO8, 4.40 MM, LEAD FREE AND HALOGEN FREE, PLASTIC, MO-153AA, TSSOP-8;
| 型号： | AT24C02B-10TQ-2.7 |
| 厂家： | 
ATMEL |
| 描述： | EEPROM, 256X8, Serial, CMOS, PDSO8, 4.40 MM, LEAD FREE AND HALOGEN FREE, PLASTIC, MO-153AA, TSSOP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
| 文件： | 总16页 (文件大小：369K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Medium-voltage and Standard-voltage Operation
– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
• Automotive Temperature Range –40°C to 125°C
• Internally Organized 256 x 8 (2K)
• Two-wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 400 kHz (2.7V) Compatibility
• Write Protect Pin for Hardware Data Protection
• 8-byte Page Write Modes
• Partial Page Writes are Allowed
• Self-timed Write Cycle (5 ms max)
• High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• 8-lead PDIP, 8-lead JEDEC SOIC, and 8-lead TSSOP Packages
Two-wire
Automotive
Temperature
Serial EEPROM
2K (256 x 8)
Description
The AT24C02B provides 2048 bits of serial electrically erasable and programmable
read-only memory (EEPROM) organized as 256 words of 8 bits each. The device is
optimized for use in many automotive applications where low-power and low-voltage
operation are essential. The AT24C02B is available in space-saving 8-lead PDIP, 8-
lead JEDEC SOIC, and 8-lead TSSOP packages and is accessed via a two-wire serial
interface. In addition, the entire family is available in 2.7V (2.7V to 5.5V) versions.
AT24C02B
Table 1. Pin Configurations
8-lead PDIP
Pin Name
A0 − A2
SDA
Function
A0
A1
1
2
3
4
8
7
6
5
VCC
WP
Address Inputs
Serial Data
A2
SCL
SDA
SCL
Serial Clock Input
Write Protect
No Connect
GND
WP
NC
8-lead SOIC
A0
A1
A2
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
GND
8-lead TSSOP
A0
A1
1
2
3
4
8
7
6
5
VCC
WP
A2
SCL
SDA
5181A–SEEPR–7/06
GND
Absolute Maximum Ratings
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Operating Temperature......................................−55°C to +125°C
Storage Temperature .........................................−65°C to +150°C
Voltage on Any Pin
with Respect to Ground........................................ −1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Figure 1. Block Diagram
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open-
collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device
address inputs that are hard wired for the AT24C02B. As many as eight 2K devices may
be addressed on a single bus system (device addressing is discussed in detail under
the Device Addressing section).
WRITE PROTECT (WP): The AT24C02B has a Write Protect pin that provides hard-
ware data protection. The Write Protect pin allows normal read/write operations when
2
AT24C02B
5181A–SEEPR–7/06
AT24C02B
connected to ground (GND). When the Write Protect pin is connected to VCC, the write
protection feature is enabled and operates as shown in the following table.
Table 2. Write Protect
Part of the Array Protected
WP Pin
Status
At VCC
At GND
24C02
Full (2K) Array
Normal Read/Write Operations
Memory Organization AT24C02, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each,
the 2K requires an 8-bit data word address for random word addressing.
3
5181A–SEEPR–7/06
Table 3. Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +2.7V
Symbol
CI/O
Test Condition
Max
8
Units
pF
Conditions
VI/O = 0V
VIN = 0V
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL)
CIN
6
pF
Note:
1. This parameter is characterized and is not 100% tested.
Table 4. DC Characteristics
Applicable over recommended operating range from: TA = −40°C to +125°C, VCC = +2.7V to +5.5V (unless otherwise noted)
Symbol
VCC1
ICC
Parameter
Test Condition
Min
Typ
Max
5.5
Units
V
Supply Voltage
2.7
Supply Current VCC = 5.0V
Supply Current VCC = 5.0V
Standby Current VCC = 2.7V
Standby Current VCC = 5.0V
Input Leakage Current
Output Leakage Current
Input Low Level(1)
Read at 100 kHz
Write at 100 kHz
VIN = VCC or VSS
VIN = VCC or VSS
VIN = VCC or VSS
VOUT = VCC or VSS
0.4
2.0
1.0
mA
mA
µA
µA
µA
µA
V
ICC
3.0
ISB1
ISB2
ILI
1.6
4.0
8.0
18.0
3.0
0.10
0.05
ILO
3.0
VIL
−0.6
VCC x 0.3
VCC + 0.5
0.4
VIH
Input High Level(1)
VCC x 0.7
V
VOL2
VOL1
Output Low Level VCC = 3.0V
Output Low Level VCC = 1.8V
IOL = 2.1 mA
V
IOL = 0.15 mA
0.2
V
Note:
1. VIL min and VIH max are reference only and are not tested.
4
AT24C02B
5181A–SEEPR–7/06
AT24C02B
Table 5. AC Characteristics
Applicable over recommended operating range from TA = −40°C to +125°C, VCC = +2.7V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted)
AT24C02B
Symbol
fSCL
tLOW
tHIGH
tI
Parameter
Min
Max
Units
kHz
µs
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time(1)
Clock Low to Data Out Valid
400
1.2
0.6
µs
50
ns
tAA
0.1
1.2
0.9
µs
Time the bus must be free before
a new transmission can start(2)
tBUF
µs
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
Start Hold Time
0.6
0.6
0
µs
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time(2)
Inputs Fall Time(2)
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
5.0V, 25°C, Page Mode
µs
µs
100
ns
300
300
ns
tF
ns
tSU.STO
tDH
0.6
50
µs
ns
tWR
5
ms
Endurance(2)
1M
Write Cycles
Notes: 1. This parameter is characterized and is not 100% tested (TA = 25°C).
2. This parameter is characterized.
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL low time periods (see to
Figure 4 on page 7). Data changes during SCL high periods will indicate a start or stop
condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (see to Figure 5 on page 7).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (see Figure 5 on page 7).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a “0” to acknowledge that it has received
each word. This happens during the ninth clock cycle.
STANDBY MODE: The AT24C02B features a low-power standby mode which is
enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion
of any internal operations.
5
5181A–SEEPR–7/06
MEMORY RESET: After an interruption in protocol, power loss or system reset, any
two-wire part can be reset by following these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition.
Bus Timing
Figure 2. SCL: Serial Clock, SDA: Serial Data I/O
Write Cycle Timing
Figure 3. SCL: Serial Clock, SDA: Serial Data I/O
SCL
SDA
ACK
8th BIT
WORDn
(1)
t
wr
START
CONDITION
STOP
CONDITION
Note:
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
6
AT24C02B
5181A–SEEPR–7/06
AT24C02B
Figure 4. Data Validity
Figure 5. Start and Stop Definition
Figure 6. Output Acknowledge
7
5181A–SEEPR–7/06
Device Addressing
The 2K EEPROM device requires an 8-bit device address word following a start condi-
tion to enable the chip for a read or write operation (see to Figure 7 on page 9).
The device address word consists of a mandatory “1”, “0” sequence for the first four
most significant bits as shown. This is common to all the Serial EEPROM devices.
The next 3 bits are the A2, A1 and A0 device address bits for the 2K EEPROM. These 3
bits must compare to their corresponding hardwired input pins.
The eighth bit of the device address is the read/write operation select bit. A read opera-
tion is initiated if this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a “0”. If a compare is
not made, the chip will return to a standby state.
Write Operations
BYTE WRITE: A write operation requires an 8-bit data word address following the
device address word and acknowledgment. Upon receipt of this address, the EEPROM
will again respond with a “0” and then clock in the first 8-bit data word. Following receipt
of the 8-bit data word, the EEPROM will output a “0” and the addressing device, such as
a microcontroller, must terminate the write sequence with a stop condition. At this time
the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All
inputs are disabled during this write cycle and the EEPROM will not respond until the
write is complete (see Figure 8 on page 9).
PAGE WRITE: The 2K EEPROM is capable of an 8-byte page write.
A page write is initiated the same as a byte write, but the microcontroller does not send
a stop condition after the first data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcontroller can transmit up to seven
data words. The EEPROM will respond with a “0” after each data word received. The
microcontroller must terminate the page write sequence with a stop condition (see Fig-
ure 9 on page 10).
The data word address lower three bits are internally incremented following the receipt
of each data word. The higher data word address bits are not incremented, retaining the
memory page row location. When the word address, internally generated, reaches the
page boundary, the following byte is placed at the beginning of the same page. If more
than eight data words are transmitted to the EEPROM, the data word address will “roll
over” and previous data will be overwritten.
ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-
ing a start condition followed by the device address word. The read/write bit is
representative of the operation desired. Only if the internal write cycle has completed
will the EEPROM respond with a “0”, allowing the read or write sequence to continue.
Read Operations
Read operations are initiated the same way as write operations with the exception that
the read/write select bit in the device address word is set to “1”. There are three read
operations: current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the
last address accessed during the last read or write operation, incremented by one. This
address stays valid between operations as long as the chip power is maintained. The
address “roll over” during read is from the last byte of the last memory page to the first
byte of the first page. The address “roll over” during write is from the last byte of the cur-
rent page to the first byte of the same page.
8
AT24C02B
5181A–SEEPR–7/06
AT24C02B
Once the device address with the read/write select bit set to “1” is clocked in and
acknowledged by the EEPROM, the current address data word is serially clocked out.
The microcontroller does not respond with an input “0” but does generate a following
stop condition (see Figure 10 on page 10).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the
data word address. Once the device address word and data word address are clocked
in and acknowledged by the EEPROM, the microcontroller must generate another start
condition. The microcontroller now initiates a current address read by sending a device
address with the read/write select bit high. The EEPROM acknowledges the device
address and serially clocks out the data word. The microcontroller does not respond
with a “0” but does generate a following stop condition (see Figure 11 on page 11).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or
a random address read. After the microcontroller receives a data word, it responds with
an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to
increment the data word address and serially clock out sequential data words. When the
memory address limit is reached, the data word address will “roll over” and the sequen-
tial read will continue. The sequential read operation is terminated when the
microcontroller does not respond with a “0” but does generate a following stop condition
(see Figure 12 on page 11).
Figure 7. Device Address
MSB
Figure 8. Byte Write
9
5181A–SEEPR–7/06
Figure 9. Page Write
Figure 10. Current Address Read
10
AT24C02B
5181A–SEEPR–7/06
AT24C02B
Figure 11. Random Read
Figure 12. Sequential Read
11
5181A–SEEPR–7/06
AT24C02B Ordering Information
Ordering Code
Package
Operation Range
AT24C02B-10PQ-2.7
AT24C02BN-10SQ-2.7
AT24C02B-10TQ-2.7
8P3
8S1
8A2
Lead-free/Halogen-free/Automotive
Temperature
(−40°C to 125°C)
Package Type
8P3
8S1
8A2
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
Options
−2.7
Low-voltage (2.7V to 5.5V)
12
AT24C02B
5181A–SEEPR–7/06
AT24C02B
Packaging Information
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
MIN
MAX
NOM
NOTE
SYMBOL
D1
A2 A
A
0.210
0.195
0.022
0.070
0.045
0.014
0.400
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
4 PLCS
0.310
0.250
0.325
0.280
b
E1
e
0.100 BSC
0.300 BSC
0.130
Side View
eA
L
4
2
0.115
0.150
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
B
R
13
5181A–SEEPR–7/06
8S1 – JEDEC SOIC
C
1
E
E1
L
N
Top View
End View
e
B
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.35
0.10
MAX
1.75
0.25
NOM
NOTE
SYMBOL
A1
A
–
–
A1
b
0.31
0.17
4.80
3.81
5.79
–
0.51
0.25
5.00
3.99
6.20
C
D
E1
E
e
–
–
D
–
–
Side View
1.27 BSC
L
0.40
0˚
–
–
1.27
8˚
Note:
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03
REV.
TITLE
DRAWING NO.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
8S1
B
R
Small Outline (JEDEC SOIC)
14
AT24C02B
5181A–SEEPR–7/06
AT24C02B
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
3.00
NOTE
SYMBOL
D
2.90
3.10
2, 5
A
b
E
6.40 BSC
4.40
E1
A
4.30
–
4.50
1.20
1.05
0.30
3, 5
–
A2
b
0.80
0.19
1.00
e
A2
–
4
D
e
0.65 BSC
0.60
L
0.45
0.75
Side View
L1
1.00 REF
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02
DRAWING NO.
TITLE
REV.
2325 Orchard Parkway
San Jose, CA 95131
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
B
8A2
R
15
5181A–SEEPR–7/06
Atmel Corporation
Atmel Operations
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San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Memory
RF/Automotive
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Tel: (49) 71-31-67-0
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Fax: 1(408) 436-4314
Regional Headquarters
Microcontrollers
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5181A–SEEPR–7/06
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