AT24C02C-CUM-T [ATMEL]
Two-wire Serial Electrically Erasable and Programmable Read-only Memory; 两线串行电可擦除和可编程只读存储器
| 型号： | AT24C02C-CUM-T |
| 厂家： | 
ATMEL |
| 描述： | Two-wire Serial Electrically Erasable and Programmable Read-only Memory |
| 文件： | 总23页 (文件大小：1003K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Low-voltage and Standard-voltage Operation
– VCC = 1.7V to 5.5V
• Internally Organized 256 x 8 (2K)
• Two-wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 1MHz (5V), 400kHz (1.7V, 2.5V, 2.7V) Compatibility
• Write Protect Pin for Hardware Data Protection
• 8-byte Page (2K) Write Modes
Two-wire
• Partial Page Writes Allowed
Serial Electrically
Erasable and
Programmable
Read-only Memory
2K (256 x 8)
• Self-timed Write Cycle (5ms max)
• High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• Green (Pb/Halide-free/RoHS Compliant) Package Options
• Die Sales: Wafer Form and Tape and Reel
Description
The Atmel® AT24C02C provides 2048-bits of serial electrically erasable and program-
mable read-only memory (EEPROM) organized as 256-words of 8-bits each. The
device is optimized for use in many industrial and commercial applications where low-
power and low-voltage operation are essential. The AT24C02C is available in space-
saving 8-lead PDIP, 8-lead TSSOP, 8-lead JEDEC SOIC, 8-lead UDFN, 5-lead
SOT23 and 8-ball VFBGA packages and is accessed via a two-wire serial interface.
Atmel AT24C02C
Table 0-1.
Pin Configuration
8-lead PDIP
8-lead SOIC
Pin Name
A0 - A2
SDA
Function
8
7
6
5
VCC
WP
A0
A1
1
2
3
4
A0
A1
1
2
3
4
8
7
6
5
VCC
WP
Address Inputs
Serial Data
SCL
SDA
A2
A2
SCL
SDA
GND
GND
SCL
Serial Clock Input
Write Protect
Ground
WP
8-lead UDFN
8-lead TSSOP
GND
A0
A1
1
2
3
4
8
7
6
5
VCC
WP
VCC
8
7
6
5
1
2
3
4
A0
A1
A2
VCC
Power Supply
WP
SCL
SDA
A2
SCL
SDA
Note:
For use of 5-lead
GND
GND
SOT23, the software
A2, A1, and A0 bits in
the device address
word must be set to
zero to properly
Bottom View
8-ball VFBGA
5-lead SOT23
8
7
6
5
1
2
3
4
A0
VCC
WP
WP
SCL
GND
SDA
1
2
3
5
communicate
A1
A2
SCL
SDA
VCC
4
GND
Bottom View
8700D–SEEPR–8/10
Absolute Maximum Ratings
Operating Temperature........................–55°C to +125°C
*NOTICE:
Stresses beyond those listed under “Abso-
lute Maximum Ratings” may cause perma-
nent damage to the device. This is a stress
rating only and functional operation of the
device at these or any other conditions
beyond those indicated in the operational
sections of this specification is not implied.
Exposure to absolute maximum rating condi-
tions for extended periods may affect device
reliability.
Storage Temperature ...........................–65°C to +150°C
Voltage on Any Pin
with Respect to Ground...........................–1.0V to +7.0V
Maximum Operating Voltage................................. 6.25V
DC Output Current .............................................. 5.0 mA
Figure 0-1. Block Diagram
VCC
GND
WP
START
STOP
LOGIC
SCL
SDA
SERIAL
CONTROL
LOGIC
EN
H.V. PUMP/TIMING
DATA RECOVERY
LOAD
COMP
DEVICE
ADDRESS
COMPARATOR
LOAD
INC
A2
A1
A0
R/W
DATA WORD
EEPROM
ADDR/COUNTER
Y DEC
SERIAL MUX
DOUT/ACK
LOGIC
DIN
DOUT
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Atmel AT24C02C
8700D–SEEPR–8/10
Atmel AT24C02C
1.
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and
negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may
be wire-ORed with any number of other open-drain or open-collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hard wired
for the Atmel® AT24C02C. As many as eight 2K devices may be addressed on a single bus system (device
addressing is discussed in detail under the Device Addressing section).
WRITE PROTECT (WP): AT24C02C has a write protect pin that provides hardware data protection. The write
protect pin allows normal read/write operations when connected to ground (GND). When the write protect pin is
connected to VCC, the write protection feature is enabled and operates as shown in Table 1-1.
Table 1-1.
Write Protect
WP Pin
Status
Part of the Array Protected
Atmel 24C02C
Full (2K) Array
At VCC
At GND
Normal Read/Write Operations
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8700D–SEEPR–8/10
2.
Memory Organization
Atmel AT24C02C, 2K SERIAL EEPROM: Internally organized with 32 pages of 8-bytes each, the 2K requires an
8-bit data word address for random word addressing.
Table 2-1.
Applicable over recommended operating range from TA = 25⋅C, f = 1.0MHz, VCC = +1.7V to +5.5V
Pin Capacitance(1)
Symbol
CI/O
Test Condition
Max
8
Units
pF
Conditions
VI/O = 0V
VIN = 0V
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL)
CIN
6
pF
Note:
1. This parameter is characterized and is not 100% tested
Table 2-2.
DC Characteristics
Applicable over recommended operating range from: TAI = –40°C to +85°C, VCC = +1.7V to +5.5V (unless otherwise noted)
Symbol
VCC1
VCC2
VCC3
VCC4
ICC
Parameter
Test Condition
Min
1.7
2.5
2.7
4.5
Typ
Max
5.5
Units
V
Supply Voltage
Supply Voltage
5.5
V
Supply Voltage
5.5
V
Supply Voltage
5.5
V
Supply Current VCC = 5.0V
Supply Current VCC = 5.0V
Standby Current VCC = 1.7V
Standby Current VCC = 2.5V
Standby Current VCC = 2.7V
Standby Current VCC = 5.0V
Input Leakage Current
Output Leakage Current
Input Low Level(1)
READ at 100kHz
WRITE at 100kHz
VIN = VCC or VSS
VIN = VCC or VSS
VIN = VCC or VSS
VIN = VCC or VSS
VIN = VCC or VSS
VOUT = VCC or VSS
0.4
2.0
1.0
mA
mA
µA
µA
µA
µA
µA
µA
V
ICC
3.0
ISB1
ISB2
ISB3
ISB4
ILI
0.6
3.0
1.4
4.0
1.6
4.0
8.0
18.0
3.0
0.10
0.05
ILO
3.0
VIL
–0.6
VCC x 0.3
VCC + 0.5
0.4
VIH
Input High Level(1)
VCC x 0.7
V
VOL2
VOL1
Output Low Level VCC = 3.0V
Output Low Level VCC = 1.7V
IOL = 2.1mA
V
IOL = 0.15mA
0.2
V
Note:
1. VIL min and VIH max are reference only and are not tested
4
Atmel AT24C02C
8700D–SEEPR–8/10
Atmel AT24C02C
Table 2-3.
AC Characteristics
Applicable over recommended operating range from TAI = –40°C to +85°C, VCC = +1.7V to +5.5V, CL = 1TTL Gate and
100pF (unless otherwise noted)
1.7, 2.5, 2.7
5.0V
Symbol
fSCL
Parameter
Min
Max
Min
Max
Units
kHz
µs
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time
Clock Low to Data Out Valid
Time the bus must be free before a new transmission can start
Start Hold Time
400
1000
tLOW
tHIGH
tI
1.2
0.6
0.4
0.4
µs
50
50
ns
tAA
0.1
1.2
0.6
0.6
0
0.9
0.05
0.5
0.55
µs
tBUF
µs
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
0.25
0.25
0
µs
Start Setup Time
µs
Data In Hold Time
µs
Data In Setup Time
100
100
ns
Inputs Rise Time(1)
0.3
0.3
µs
tF
Inputs Fall Time(1)
300
100
ns
tSU.STO
tDH
Stop Setup Time
0.6
50
.25
50
µs
Data Out Hold Time
ns
tWR
Write Cycle Time
5
5
ms
Write
Cycles
Endurance(1)
5.0V, 25⋅C, Byte Mode
1 Million
Note:
1. This parameter is ensured by characterization only
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8700D–SEEPR–8/10
3.
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA
pin may change only during SCL low time periods (see Figure 5-2 on page 8). Data changes during SCL high
periods will indicate a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any
other command (see Figure 5-3 on page 8).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the
stop command will place the EEPROM in a standby power mode (see Figure 5-3 on page 8).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock
cycle.
STANDBY MODE: The Atmel® AT24C02C features a low-power standby mode which is enabled: (a) upon power-
up and (b) after the receipt of the STOP bit and the completion of any internal operations.
2-Wire Software Reset: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset
by following these steps: (a) Create a start bit condition, (b) clock 9 cycles, (c) create another start bit followed by
stop bit condition as shown below. The device is ready for next communication after above steps have been
completed.
Figure 3-1. Software reset
Dummy Clock Cycles
Start bit
Stop bit
Start bit
1
2
3
8
9
SCL
SDA
6
Atmel AT24C02C
8700D–SEEPR–8/10
Atmel AT24C02C
4.
Bus Timing
Figure 4-1. SCL: Serial Clock, SDA: Serial Data I/O
tHIGH
tF
tR
tLOW
tLOW
SCL
tSU.STA
tHD.STA
tHD.DAT
tSU.DAT
tSU.STO
SDA IN
tAA
tDH
tBUF
SDA OUT
5.
Write Cycle Timing
Figure 5-1. SCL: Serial Clock, SDA: Serial Data I/O
SCL
ACK
SDA
8th BIT
WORDn
(1)
t
wr
START
STOP
CONDITION
CONDITION
Notes: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal
clear/write cycle
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8700D–SEEPR–8/10
Figure 5-2. Data Validity
SDA
SCL
DATA STABLE
DATA STABLE
DATA
CHANGE
Figure 5-3. Start and Stop Definition
SDA
SCL
START
STOP
Figure 5-4. Output Acknowledge
1
8
9
SCL
DATA IN
DATA OUT
START
ACKNOWLEDGE
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Atmel AT24C02C
8700D–SEEPR–8/10
Atmel AT24C02C
6.
Device Addressing
The 2K EEPROM device requires an 8-bit device address word following a start condition to enable the chip for a
read or write operation (refer to Figure 8-1).
The device address word consists of a mandatory one, zero sequence for the first four most significant bits as
shown. This is common to all the EEPROM devices.
The next three bits are the A2, A1 and A0 device address bits for the 2K EEPROM. These three bits must compare
to their corresponding hard-wired input pins.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is
high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the chip will
return to a standby state.
7.
Write Operations
BYTE WRITE: A write operation requires an 8-bit data word address following the device address word and
acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the
first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing
device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the
EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this
write cycle and the EEPROM will not respond until the write is complete (see Figure 8-2 on page 10).
PAGE WRITE: The 2K EEPROM is capable of an 8-byte page write.
A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the
first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the
microcontroller can transmit up to seven data words. The EEPROM will respond with a zero after each data word
received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 8-3 on
page 10).
The data word address lower three bits are internally incremented following the receipt of each data word. The
higher data word address bits are not incremented, retaining the memory page row location. When the word
address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the
same page. If more than eight data words are transmitted to the EEPROM, the data word address will “roll over”
and previous data will be overwritten.
ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are
disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device
address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has
completed will the EEPROM respond with a zero allowing the read or write sequence to continue.
8.
Read Operations
Read operations are initiated the same way as write operations with the exception that the read/write select bit in
the device address word is set to one. There are three read operations: current address read, random address
read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during
the last read or write operation, incremented by one. This address stays valid between operations as long as the
chip power is maintained. The address “roll over” during read is from the last byte of the last memory page to the
9
8700D–SEEPR–8/10
first byte of the first page. The address “roll over” during write is from the last byte of the current page to the first
byte of the same page.
Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM,
the current address data word is serially clocked out. The microcontroller does not respond with an input zero but
does generate a following stop condition (see Figure 8-4 on page 11).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once
the device address word and data word address are clocked in and acknowledged by the EEPROM, the
microcontroller must generate another start condition. The microcontroller now initiates a current address read by
sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and
serially clocks out the data word. The microcontroller does not respond with a zero but does generate a following
stop condition (see Figure 8-5 on page 11).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read.
After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives
an acknowledge, it will continue to increment the data word address and serially clock out sequential data words.
When the memory address limit is reached, the data word address will “roll over” and the sequential read will
continue. The sequential read operation is terminated when the microcontroller does not respond with a zero but
does generate a following stop condition (see Figure 8-6 on page 11).
Figure 8-1. Device Address
MSB
LSB
Figure 8-2. Byte Write
Figure 8-3. Page Write
10
Atmel AT24C02C
8700D–SEEPR–8/10
Atmel AT24C02C
Figure 8-4. Current Address Read
Figure 8-5. Random Read
Figure 8-6. Sequential Read
11
8700D–SEEPR–8/10
9.
Ordering Code Detail
A T 2 4 C 0 2 C - S S H M - B
Atmel Designator
Product Family
Shipping Carrier Option
B or blank = Bulk (tubes)
T
= Tape and Reel
Operating Voltage
M
= 1.7V to 5.5V
Device Density
Package Device Grade or
Wafer/Die Thickness
02 = 2k
H
=
Green, NiPdAu lead finish,
Industrial Temperature Range
(-40˚C to +85˚C)
Device Revision
U
=
Green, matte Sn lead finish,
Industrial Temperature range
(-40˚C to +85˚C)
11 = 11mil wafer thickness
Package Option
P
=
PDIP
SS = JEDEC SOIC
TSSOP
X
=
MA = UDFN
ST = SOT23
C
= VFBGA
WWU = Wafer unsawn
WDT = Die in Tape and Reel
12
Atmel AT24C02C
8700D–SEEPR–8/10
Atmel AT24C02C
10. Part Markings
Atmel AT24C02C-PUM
Top Mark
Seal Year
| Seal Week
| | |
U = Material Set
Y = Seal Year
WW = Seal Week
02C= Device
|---|---|---|---|---|---|---|---|
A T M L U Y W W
|---|---|---|---|---|---|---|---|
@ = Country of Assembly
0 2 C
M
@
M = Voltage Indicator
|---|---|---|---|---|---|---|---|
* LOT NUMBER
*Lot Number to Use ALL Characters in Marking
|---|---|---|---|---|---|---|---|
|
BOTTOM MARK
PIN 1 INDICATOR (DOT)
No Bottom Mark
Atmel AT24C02C-SSHM
Top Mark
Seal Year
| Seal Week
| | |
H = Material Set
Y = Seal Year
|---|---|---|---|---|---|---|---|
A T M L H Y W W
|---|---|---|---|---|---|---|---|
WW = Seal Week
02C= Device
M = Voltage Indicator
@ = Country of Assembly
*Lot Number to Use ALL Characters in Marking
0 2 C
M
@
|---|---|---|---|---|---|---|---|
* LOT NUMBER
|---|---|---|---|---|---|---|---|
|
BOTTOM MARK
PIN 1 INDICATOR (DOT)
No Bottom Mark
Atmel AT24C02C-XHM
Top Mark
PIN 1 INDICATOR (DOT)
H = Material Set
Y = Seal Year
|
|---|---|---|---|---|---|
WW = Seal Week
* A T H Y W W
|---|---|---|---|---|---|
02C= Device
M = Voltage Indicator
@ = Country of Assembly
0 2 C M
@
|---|---|---|---|---|---|
ATMEL LOT NUMBER
|---|---|---|---|---|---|---|
BOTTOM MARK
No Bottom Mark
13
8700D–SEEPR–8/10
Atmel AT24C02C-MAHM
Top Mark
|---|---|---|
02C= Device
0 2 C
|---|---|---|
H M @
H = Material Set
M = Voltage Indicator
@ = Country of Assembly
Y = Year of Assembly
TC = Trace Code
|---|---|---|
Y T C
|---|---|---|
*
| PIN 1 INDICATOR (DOT)
Atmel AT24C02C-STUM
Top Mark
|---|---|---|---|---|
2C = Device
Line 1 --------> 2 C M B U
M = Voltage Indicator
B = Write Protection
U = Material Set
|---|---|---|---|---|
*
|
PIN 1 INDICATOR (DOT)
Bottom Mark
|---|---|---|---|
Y M T C
Y = One Digit Year Code
M = Seal Month
|---|---|---|---|
TC = Trace Code
Atmel AT24C02C-CUM
Top Mark
02C= Device
Line 1 -------> 02CU
Line 2 -------> YMTC
|<--PIN 1 THIS CORNER
U = Material Set
Y = One Digit Year Code
M = Seal Month
TC = Trace Code
14
Atmel AT24C02C
8700D–SEEPR–8/10
Atmel AT24C02C
11. Ordering Codes
Atmel AT24C02C Ordering Information
Ordering Code
Voltage
Package
8P3
Operation Range
AT24C02C-PUM (Bulk form only)
AT24C02C-SSHM-B(1) (NiPdAu Lead Finish)
AT24C02C-SSHM-T(2) (NiPdAu Lead Finish)
AT24C02C-XHM-B(1) (NiPdAu Lead Finish)
AT24C02C-XHM-T(2) (NiPdAu Lead Finish)
AT24C02C-MAHM-T(2) (NiPdAu Lead Finish)
AT24C02C-STUM-T(2)
1.7V to 5.5V
1.7V to 5.5V
1.7V to 5.5V
1.7V to 5.5V
1.7V to 5.5V
1.7V to 5.5V
1.7V to 5.5V
1.7V to 5.5V
8S1
8S1
Lead-free/Halogen-free/
Industrial Temperature
8A2
8A2
(–40°C to 85°C)
8Y6
5TS1
8U3-1
AT24C02C-CUM-T(2)
Industrial Temperature
AT24C02C-WWU11(3)
1.7V to 5.5V
Die Sale
(–40°C to 85°C)
Notes: 1. “-B” denotes bulk
2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP, UDFN, SOT23, and VFBGA = 5K per reel
3. For Wafer sales, please contact Atmel Sales
Package Type
8P3
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8-lead, 4.4mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
8-lead, 2.00mm x 3.00mm Body, 0.50mm Pitch, Dual No Lead Package (UDFN)
5-lead, 2.90mm x 1.60mm Body, Plastic Thin Shrink Small Outline Package (SOT23)
8-ball, die Ball Grid Array Package (VFBGA)
8A2
8Y6
5TS1
8U3-1
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8700D–SEEPR–8/10
12. Packaging Information
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
D
(Unit of Measure = inches)
e
MIN
MAX
NOM
NOTE
SYMBOL
D1
A2 A
A
0.210
0.195
0.022
0.070
0.045
0.014
0.400
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
0.310
0.250
0.325
0.280
b
4 PLCS
E1
e
0.100 BSC
0.300 BSC
0.130
Side View
eA
L
4
2
0.115
0.150
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25mm).
07/19/10
TITLE
GPC
PTC
DRAWING NO.
REV.
Package Drawing Contact:
packagedrawings@atmel.com
8P3, 8-lead, 0.300” Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
C
16
Atmel AT24C02C
8700D–SEEPR–8/10
Atmel AT24C02C
8S1 – JEDEC SOIC
C
1
E
E1
L
N
Ø
TOP VIIEWW
END VIEW
e
b
A
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
1.35
0.10
MAX
1.75
0.25
NOM
NOTE
SYMBOL
A1
A
–
–
A1
b
0.31
0.17
4.80
3.81
5.79
–
0.51
0.25
5.05
3.99
6.20
C
D
E1
E
e
–
D
–
–
–
SIDE VIEW
1.27 BSC
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
L
0.40
0°
–
–
1.27
8°
Ø
5/19/10
TITLE
GPC
DRAWING NO.
REV.
Package Drawing Contact:
packagedrawings@atmel.com
8S1, 8-lead (0.150”Wide Body), Plastic Gull
Wing Small Outline (JEDEC SOIC)
SWB
8S1
F
17
8700D–SEEPR–8/10
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
3.00
NOTE
SYMBOL
D
2.90
3.10
2, 5
A
E
6.40 BSC
4.40
b
E1
A
4.30
–
4.50
1.20
1.05
0.30
3, 5
4
–
A2
b
0.80
0.19
1.00
e
A2
–
D
e
0.65 BSC
0.60
L
0.45
0.75
Side View
L1
1.00 REF
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions,
tolerances, datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall
not exceed 0.15mm (0.006in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed
0.25mm (0.010in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08mm total in excess
of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot.
Minimum space between protrusion and adjacent lead is 0.07mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/19/10
TITLE
GPC
TNR
DRAWING NO.
REV.
Package Drawing Contact:
packagedrawings@atmel.com
8A2, 8-lead 4.4mm Body, Plastic Thin
Shrink Small Outline Package (TSSOP)
8A2
E
18
Atmel AT24C02C
8700D–SEEPR–8/10
Atmel AT24C02C
8Y6 - UDFN
A
D2
b
(8X)
Pin 1
Index
Area
Pin 1 ID
L (8X)
D
e (6X)
A1
A2
1.50 REF.
A3
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
2.00 BSC
3.00 BSC
1.50
MAX
NOTE
D
E
1.60
1.40
0.60
0.05
0.55
D2
E2
A
1.40
–
Notes: 1. This drawing is for general information only. Refer to
JEDEC Drawing MO-229, for proper dimensions,
tolerances, datums, etc.
–
–
–
2. Dimension b applies to metallized terminal and is
measured between 0.15mm and 0.30mm from the
terminal tip. If the terminal has the optional radius on the
other end of the terminal, the dimension should not be
measured in that radius area.
A1
A2
A3
L
0.00
–
0.02
–
0.20 REF
0.30
3. Soldering the large thermal pad is optional, but not
0.40
0.30
0.20
0.20
recommended.
No
electrical
connection
is
e
0.50 BSC
0.25
accomplished to the device through this pad, so if
soldered it should be tied to ground
2
b
11/21/08
TITLE
GPC
YNZ
DRAWING NO.
REV.
Package Drawing Contact:
8Y6, 8-lead, 2.0x3.0mm Body, 0.50mm Pitch,
packagedrawings@atmel.com UltraThin Mini-MAP, Dual No Lead Package
8Y6
E
(Sawn)(UDFN)
19
8700D–SEEPR–8/10
5TS1 – SOT23
e1
C
5
4
C
L
E1
E
L1
1
2
3
End View
Top View
b
A2
A
SEATING
PLANE
A1
e
COMMON DIMENSIONS
(Unit of Measure = mm)
D
Side View
SYMBOL
MIN
–
NOM
–
MAX
1.10
0.10
1.00
0.20
NOTE
Notes: 1. Dimensions D does not include mold flash, protrusions or gate
burrs. Mold flash protrusions or gate burrs shall not exceed
0.15mm per end. Dimensions E1 does not include interlead flash or
protrusion. Interlead flasg or protrusion shall not exceed 0.15mm
per side.
A
A1
A2
c
0.00
0.70
0.08
–
0.90
2. The package top may be smaller than the package bottom.
Dimensions D and E1 are deteremined at the outermost extremes
of the plastic body exclusive of mold flash, tie bar burrs, gate burrs,
and interlead flash, but including any mismatch between the top
and bottom of the plastic body.
3
–
1, 2
1, 2
1, 2
D
2.90 BSC
2.80 BSC
1.60 BSC
0.60 REF
0.95 BSC
1.90 BSC
–
E
3. These dimensions apply to the flat section of the lead between
0.08mm and 0.15mm from the lead tip.
E1
L1
e
4. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.80mm total in excess of the “b”
dimension at maximum material condition. The dambar cannot be
located on the lower radius of the foot. Minimum space between
protrusion and an adjacent lead shall not be less than 0.07mm.
5. This drawing is for general information only. Refer to JEDEC
Drawing MO-193, Variation AB for additional information.
e1
b
0.50
3, 4
0.30
11/05/08
TITLE
GPC
DRAWING NO.
REV.
Package Drawing Contact:
packagedrawings@atmel.com Shrink Small Outline Package (Shrink SOT)
5TS1, 5-lead, 1.60mm Body, Plastic Thin
TSZ
5TS1
B
20
Atmel AT24C02C
8700D–SEEPR–8/10
Atmel AT24C02C
8U3-1 – VFBGA
E
D
5.
b
1
A
PIN 1 BALL PAD CORNER
2
A
A
TOP VIEW
SIDE VIEW
PIN 1 BALL PAD CORNER
2
4
1
3
d
(d1)
6
5
8
7
COMMON DIMENSIONS
(Unit of Measure - mm)
e
(e1)
SYMBOL
NOM
MIN
MAX
NOTE
A
0.73
0.09
0.40
0.20
0.79
0.85
0.19
0.50
0.30
BOTTOM VIEW
8 SOLDER BALLS
A1
A2
b
0.14
0.45
Notes:
0.25
2
1. This drawing is for general information only.
D
1.50 BSC
2.0 BSC
0.50 BSC
0.25 REF
1.00 BSC
0.25 REF
E
2. Dimension ‘b’ is measured at maximum solder ball diameter.
3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu.
e
e1
d
d1
07/14/10
TITLE
GPC
DRAWING NO.
REV.
Package Drawing Contact:
packagedrawings@atmel.com
8U3-1, 8-ball, 1.50 x 2.00mm Body,
0.50 pitch, VFBGA Package (dBGA2)
GXU
8U3-1
D
21
8700D–SEEPR–8/10
13. Revision History
Doc. Rev.
Date
08/2010
Comments
8700D
Changed AT24C02C-XHM Part Marking from C02CM@ to 02CM @
Ordering Information:
- Changed Atmel AT24C02C-TSUM-T to Atmel AT24C02C-STUM-T
- Changed Atmel AT24C02CY6-MAHM-T to Atmel AT24C02C-MAHM-T
- Changed Atmel AT24C02CU3-CUM-T to Atmel AT24C02C-CUM-T
Catalog Numbering Scheme, changed TS = SOT23 to ST = SOT23
Part Marking SOT23:
- Changed 2CMWU to 2CMBU
- Changed W = Write Protection Feature to B = Write Protection
8700C
07/2010
Part Marking PDIP and SOIC: Added @ = Country of Assembly
Part Marking TSSOP: Replaced and removed bottom mark
Part Marking UDFN: Added HM@
Remove Preliminary Status
Changed tI Max 40 to 50 in Table AC Characteristics
8700B
8700A
02/2010
12/2009
Corrected Catalog Numbering Scheme and Ordering Information
Initial Document Release
22
Atmel AT24C02C
8700D–SEEPR–8/10
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8700D–SEEPR–8/10
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