AT24C1024C1-10CC-2.7 [ATMEL]
EEPROM, 128KX8, Serial, CMOS, PDSO8, 0.300 INCH, LAP-8;
| 型号： | AT24C1024C1-10CC-2.7 |
| 厂家： | 
ATMEL |
| 描述： | EEPROM, 128KX8, Serial, CMOS, PDSO8, 0.300 INCH, LAP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
| 文件： | 总16页 (文件大小：256K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Low-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
• Internally Organized 131,072 x 8
• 2-wire Serial Interface
• Schmitt Triggers, Filtered Inputs for Noise Suppression
• Bi-directional Data Transfer Protocol
• 400 kHz (2.7V) and 1 MHz (5V) Clock Rate
• Write Protect Pin for Hardware and Software Data Protection
• 256-byte Page Write Mode (Partial Page Writes Allowed)
• Random and Sequential Read Modes
• Self-timed Write Cycle (5 ms Typical)
• High Reliability
2-wire Serial
EEPROM
– Endurance: 100,000 Write Cycles/Page
– Data Retention: 40 Years
• 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead LAP and 8-ball dBGATM Packages
1M (131,072 x 8)
Description
AT24C1024
The AT24C1024 provides 1,048,576 bits of serial electrically erasable and program-
mable read only memory (EEPROM) organized as 131,072 words of 8 bits each. The
device’s cascadable feature allows up to 2 devices to share a common 2-wire bus.
The device is optimized for use in many industrial and commercial applications where
low-power and low-voltage operation are essential. The devices are available in
space-saving 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead Leadless Array (LAP), and 8-ball
dBGA packages. In addition, the entire family is available in 2.7V (2.7V to 5.5V)
versions.
Advance
Information
8-lead PDIP
Pin Configurations
Pin Name
Function
NC
A1
1
2
3
4
8
7
6
5
VCC
WP
A1
Address Input
Serial Data
NC
SCL
SDA
SDA
SCL
WP
GND
Serial Clock Input
Write Protect
No Connect
8-lead Leadless Array
Bottom View
NC
VCC
WP
8
7
6
5
1
2
3
4
NC
A1
SCL
SDA
NC
GND
8-lead SOIC
NC
A1
1
2
3
4
8
7
6
5
VCC
WP
8-ball dBGA
Bottom View
NC
SCL
SDA
8
7
6
5
1
2
3
4
GND
NC
VCC
A1
WP
SCL
SDA
NC
GND
Rev. 1471D–07/01
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Operating Temperature.................................. -40°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground.....................................-1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Block Diagram
2
AT24C1024
1471D–07/01
AT24C1024
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-
drain driven and may be wire-ORed with any number of other open-drain or open-collector
devices.
DEVICE/PAGE ADDRESSES (A1): The A1 pin is a device address input that can be hard-
wired or left not connected for hardware compatibility with AT24C128/256/512. When the A1
pin is hardwired, as many as two 1024K devices may be addressed on a single bus system
(device addressing is discussed in detail under the Device Addressing section). When the pin
is not hardwired, the default A1 is zero.
WRITE PROTECT (WP): The hardware Write Protect pin is useful for protecting the entire
contents of the memory from inadvertent write operations. The write-protect input, when tied to
GND, allows normal write operations. When WP is tied high to VCC, all write operations to the
memory are inhibited. If left unconnected, WP is internally pulled down to GND. Switching WP
to VCC prior to a write operation creates a software write-protect function.
Memory
Organization
AT24C1024, 1024K SERIAL EEPROM: The 1024K is internally organized as 512 pages of
256 bytes each. Random word addressing requires a 17-bit data word address.
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1471D–07/01
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +2.7V.
Symbol
CI/O
Test Condition
Max
8
Units
pF
Conditions
VI/O = 0V
VIN = 0V
Input/Output Capacitance (SDA)
CIN
Input Capacitance (A1, SCL)
6
pF
Note:
1. This parameter is characterized and is not 100% tested.
DC Characteristics
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +2.7V to +5.5V, TAC = 0°C to +70°C,
VCC = +2.7V to +5.5V (unless otherwise noted).
Symbol
VCC
Parameter
Test Condition
Min
Typ
Max
5.5
2.0
5.0
1.0
6.0
3.0
Units
V
Supply Voltage
Supply Current
Supply Current
2.7
ICC
VCC = 5.0V
READ at 400 kHz
WRITE at 400 kHz
VIN = VCC or VSS
mA
mA
µA
ICC
VCC = 5.0V
VCC = 2.7V
ISB
Standby Current
VCC = 5.5V
µA
ILI
Input Leakage Current
VIN = VCC or VSS
VOUT = VCC or VSS
0.10
0.05
µA
Output Leakage
Current
ILO
3.0
µA
VIL
Input Low Level(1)
Input High Level(1)
Output Low Level
-0.6
VCC x 0.3
VCC + 0.5
0.4
V
V
V
VIH
VOL
VCC x 0.7
VCC = 3.0V
IOL = 2.1 mA
Note:
1. VIL min and VIH max are reference only and are not tested.
4
AT24C1024
1471D–07/01
AT24C1024
AC Characteristics
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +2.7V to +5.5V, CL = 100 pF (unless
otherwise noted). Test conditions are listed in Note 2.
Symbol
Parameter
Test Conditions
Min
Max
Units
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1000
400
fSCL
Clock Frequency, SCL
kHz
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
0.6
1.3
tLOW
tHIGH
tAA
Clock Pulse Width Low
Clock Pulse Width High
Clock Low to Data Out Valid
µs
µs
µs
µs
µs
µs
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
0.4
1.0
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
0.05
0.05
0.55
0.9
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
0.5
1.3
Time the bus must be free before a new
transmission can start(1)
tBUF
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
0.25
0.6
tHD.STA
Start Hold Time
Start Setup Time
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
0.25
0.6
tSU.STA
tHD.DAT
tSU.DAT
tR
Data In Hold Time
Data In Setup Time
Inputs Rise Time(1)
0
µs
ns
µs
100
0.3
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
100
300
tF
Inputs Fall Time(1)
ns
µs
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
0.25
0.6
tSU.STO
Stop Setup Time
tDH
Data Out Hold Time
Write Cycle Time
50
ns
ms
tWR
10
Endurance(1)
5.0V, 25°C, Page Mode
100K
Write Cycles
Notes: 1. This parameter is characterized and is not 100% tested.
2. AC measurement conditions:
RL (connects to VCC): 1.3 kΩ (2.7V, 5V)
Input pulse voltages: 0.3 VCC to 0.7 VCC
Input rise and fall times: ≤50 ns
Input and output timing reference voltages: 0.5 VCC
5
1471D–07/01
Device
Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external
device. Data on the SDA pin may change only during SCL low time periods (refer to Data
Validity timing diagram). Data changes during SCL high periods will indicate a start or stop
condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which
must precede any other command (refer to Start and Stop Definition timing diagram).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a
read sequence, the Stop command will place the EEPROM in a standby power mode (refer to
Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowl-
edge that it has received each word.
STANDBY MODE: The AT24C1024 features a low-power standby mode which is enabled: a)
upon power-up and b) after the receipt of the STOP bit and the completion of any internal
operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire
part can be reset by following these steps:
1. Clock up to 9 cycles,
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition.
6
AT24C1024
1471D–07/01
AT24C1024
Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)
Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)
(1)
Note:
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
7
1471D–07/01
Data Validity
Start and Stop Definition
Output Acknowledge
8
AT24C1024
1471D–07/01
AT24C1024
Device
Addressing
The 1024K EEPROM requires an 8-bit device address word following a start condition to
enable the chip for a read or write operation (refer to Figure 1). The device address word con-
sists of a mandatory one, zero sequence for the first five most significant bits as shown. This is
common to all 2-wire EEPROM devices.
The 1024K uses the one device address bit, A1, to allow up to two devices on the same bus.
The A1 bit must compare to the corresponding hardwired input pin. The A1 pin uses an inter-
nal proprietary circuit that biases it to a logic low condition if the pin is allowed to float.
The seventh bit (P0) of the device address is a memory page address bit. This memory page
address bit is the most significant bit of the data word address that follows. The eighth bit of
the device address is the read/write operation select bit. A read operation is initiated if this bit
is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is not
made, the device will return to a standby state.
DATA SECURITY: The AT24C1024 has a hardware data protection scheme that allows the
user to write-protect the entire memory when the WP pin is at VCC
.
Write
Operations
BYTE WRITE: To select a data word in the 1024K memory requires a 17-bit word address.
The word address field consists of the P0 bit of the device address, then the most significant
word address followed by the least significant word address (refer to Figure 2)
A write operation requires the P0 bit and two 8-bit data word addresses following the device
address word and acknowledgment. Upon receipt of this address, the EEPROM will again
respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit
data word, the EEPROM will output a zero. The addressing device, such as a microcontroller,
then must terminate the write sequence with a stop condition. At this time the EEPROM enters
an internally timed write cycle, TWR, to the nonvolatile memory. All inputs are disabled during
this write cycle and the EEPROM will not respond until the write is complete (refer to Figure 2).
PAGE WRITE: The 1024K EEPROM is capable of 256-byte page writes.
A page write is initiated the same way as a byte write, but the microcontroller does not send a
stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges
receipt of the first data word, the microcontroller can transmit up to 255 more data words. The
EEPROM will respond with a zero after each data word received. The microcontroller must ter-
minate the page write sequence with a stop condition (refer to Figure 3).
The data word address lower 8 bits are internally incremented following the receipt of each
data word. The higher data word address bits are not incremented, retaining the memory page
row location. When the word address, internally generated, reaches the page boundary, the
following byte is placed at the beginning of the same page. If more than 256 data words are
transmitted to the EEPROM, the data word address will “roll over” and previous data will be
overwritten. The address “rollover” during write is from the last byte of the current page to the
first byte of the same page.
ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a
start condition followed by the device address word. The read/write bit is representative of the
operation desired. Only if the internal write cycle has completed will the EEPROM respond
with a zero, allowing the read or write sequence to continue.
Read
Operations
Read operations are initiated the same way as write operations with the exception that the
read/write select bit in the device address word is set to one. There are three read operations:
current address read, random address read and sequential read.
9
1471D–07/01
CURRENT ADDRESS READ: The internal data word address counter maintains the last
address accessed during the last read or write operation, incremented by one. This address
stays valid between operations as long as the chip power is maintained. The address “rollover”
during read is from the last byte of the last memory page, to the first byte of the first page.
Once the device address with the read/write select bit set to one is clocked in and acknowl-
edged by the EEPROM, the current address data word is serially clocked out. The
microcontroller does not respond with an input zero but does generate a following stop condi-
tion (refer to Figure 4).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data
word address. Once the device address word and data word address are clocked in and
acknowledged by the EEPROM, the microcontroller must generate another start condition.
The microcontroller now initiates a current address read by sending a device address with the
read/write select bit high. The EEPROM acknowledges the device address and serially clocks
out the data word. The microcontroller does not respond with a zero but does generate a fol-
lowing stop condition (refer to Figure 5).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a ran-
dom address read. After the microcontroller receives a data word, it responds with an
acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment
the data word address and serially clock out sequential data words. When the memory
address limit is reached, the data word address will “roll over” and the sequential read will con-
tinue. The sequential read operation is terminated when the microcontroller does not respond
with a zero, but does generate a following stop condition (refer to Figure 6).
10
AT24C1024
1471D–07/01
AT24C1024
Figure 1. Device Address
0
Figure 2. Byte Write
MOST
SIGNIFICANT
LEAST
SIGNIFICANT
P
0
Figure 3. Page Write
MOST
SIGNIFICANT
LEAST
SIGNIFICANT
P
0
Figure 4. Current Address Read
11
1471D–07/01
Figure 5. Random Read
P
0
Figure 6. Sequential Read
P
0
12
AT24C1024
1471D–07/01
AT24C1024
Ordering Information
tWR (max)
ICC (max)
ISB (max)
fMAX
(ms)
(µA)
(µA)
(kHz)
Package
Operation Range
Ordering Code
AT24C1024-10CC-2.7
AT24C1024C1-10CC-2.7
AT24C1024-10PC-2.7
AT24C1024W-10SC-2.7
AT24C1024-10UC-2.7
8C
8C1
8P3
8S2
8U8
Commercial
2000
2000
3.0
3.0
400
400
(0°C to 70°C)
10
AT24C1024-10CI-2.7
AT24C1024C1-10CI-2.7
AT24C1024-10PI-2.7
AT24C1024W-10SI-2.7
AT24C1024-10UI-2.7
8C
8C1
8P3
8S2
8U8
Industrial
(-40°C to 85°C)
Package Type
8C
8-lead, 0.230" Wide, Leadless Array Package (LAP)
8-lead, 0.300" Wide, Leadless Array Package (LAP)
8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP)
8-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)
8-ball, die Ball Grid Array Package (dBGA)
Options
8C1
8P3
8S2
8U8
-2.7
Low Voltage (2.7V to 5.5V)
13
1471D–07/01
Packaging Information
8C, 8-lead, 0.230" Wide,
Leadless Array Package (LAP)
8C1, 8-lead 0.300" Wide, Leadless Array Package
(LAP)
Dimensions in Millimeters and (Inches)*
Dimensions in Millimeters and (Inches)*
SIDE
SIDE
VIEW
TOP VIEW
VIEW
TOP VIEW
5.10 (0.201)
4.90 (0.193)
5.03 (0.198)
4.83 (0.190)
1.14 (0.045)
0.94 (0.037)
8.10 (0.319)
7.90 (0.311)
1.14 (0.045)
0.94 (0.037)
6.09 (0.240)
5.89 (0.232)
0.38 (0.015)
0.30 (0.012)
0.38 (0.015)
0.30 (0.012)
BOTTOM VIEW
BOTTOM VIEW
1
1.32 (0.052)
1.22 (0.048)
1.12 (0.044)
1.32 (0.052)
1.22 (0.048)
1.19 (0.047)
1.09 (0.043)
1.22 (0.048)
8
7
6
5
1
8
7
6
5
0.95 (0.037)
0.85 (0.033)
0.61 (0.024)
2
3
4
2
3
4
4.76 (0.187)
4.66 (0.183)
0.51 (0.020)
0.92 (0.036)
0.82 (0.032)
0.89 (0.035)
0.79 (0.031)
0.34 (0.013)
0.24 (0.009)
0.61 (0.024)
0.51 (0.020)
* Controlling dimension: millimeters
*Controlling dimension: millimeters
8P3, 8-lead, 0.300" Wide,
8S2, 8-lead, 0.200" Wide, Plastic Gull Wing
Small Outline Package (EIAJ SOIC)
Dimensions in Inches and (Millimeters)
Plastic Dual In-line Package (PDIP)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-001 BA
.400 (10.16)
.355 (9.02)
.020 (.508)
.012 (.305)
PIN
1
.213 (5.41) .330 (8.38)
.205 (5.21) .300 (7.62)
.280 (7.11)
.240 (6.10)
PIN 1
.037 (.940)
.027 (.690)
.300 (7.62) REF
.210 (5.33) MAX
.050 (1.27) BSC
.100 (2.54) BSC
.212 (5.38)
.203 (5.16)
.080 (2.03)
.070 (1.78)
SEATING
PLANE
.015 (.380) MIN
.150 (3.81)
.115 (2.92)
.022 (.559)
.014 (.356)
.070 (1.78)
.045 (1.14)
.013 (.330)
.004 (.102)
.325 (8.26)
.300 (7.62)
0
8
REF
.010 (.254)
.007 (.178)
0
REF
15
.012 (.305)
.008 (.203)
.035 (.889)
.020 (.508)
.430 (10.9) MAX
14
AT24C1024
1471D–07/01
AT24C1024
Packaging Information
8U8, 8-ball, die Ball Grid Array Package (dBGA)
Dimensions in Millimeters and (Inches)
TOP VIEW
2.85 (0.112)
3.84 (0.151)
SIDE VIEW
0.90 (0.035)
BOTTOM VIEW
1
2
3
4
8
7
6
5
0.75 (0.029)
0.80 (0.031)
0.75 (0.029)
1.05 (0.041)
0.38 (0.015)
15
1471D–07/01
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© Atmel Corporation 2001.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
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1471D–07/01/xM
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