AT24C1024SC-09BT [ATMEL]
EEPROM, 128KX8, Serial, CMOS, CARD-8;
| 型号： | AT24C1024SC-09BT |
| 厂家： | 
ATMEL |
| 描述： | EEPROM, 128KX8, Serial, CMOS, CARD-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总14页 (文件大小：212K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Low-voltage and Standard-voltage Operation, VCC = 2.7V–5.5V
• Internally Organized 131,072x 8
• Two-wire Serial Interface
• Schmitt Triggers, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 1 MHz (5V) and 400 kHz (2.7V) Compatibility
• 256-byte Page Write Mode (Partial Page Writes Allowed)
• Self-timed Write Cycle (5 ms Typical)
• High Reliability
– Endurance: 100,000 Write Cycles
– Data Retention: 40 Years
– 5.5V ESD Protection: >4000V
Two-wire Serial
EEPROM Smart
Card Module
Description
The AT24C1024SC provides 1,048,576 bits of serial electrically erasable and pro-
grammable read only memory (EEPROM) organized as 131,072 words of 8 bits each.
This device is optimized for use in smart card applications where low-power and low-
voltage operation may be essential. This device is available in a standard ISO 7816
smart card module (see Ordering Information, page 11). All devices are functionally
equivalent to Atmel serial EEPROM products offered in standard IC packages (PDIP,
SOIC, dBGA, LAP), with the exception of the slave address and write protect func-
tions, which are not required for smart card applications.
1K (131,072 x 8)
AT24C1024SC
Table 1. Pin Configurations
Pad Name
VCC
Description
ISO Module Contact
Power Supply Voltage
Ground
C1
GND
SCL
C5
Serial Clock Input
Serial Data Input/Output
No Connect
C3
C7
SDA
NC
C2, C4, C6, C8
Figure 1. Card Module Contact
C5 = GND
C6 = NC
VCC = C1
NC = C2
SCL = C3
NC = C4
C7 = SDA
C8 = NC
5045A–SEEPR–04/04
Absolute Maximum Ratings*
NOTICE:* Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only; functional opera-
tion of the device at these or any other conditions
beyond those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
Operating Temperature......................................−55°C to +125°C
Storage Temperature .........................................−65°C to +150°C
Voltage on Any Pin
with Respect to Ground........................................ −1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Figure 2. Block Diagram
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.
Memory Organization AT24C1024SC, 1024K SERIAL EEPROM: The 1024K is internally organized as 512
pages of 256 bytes each. Random word addressing requires a 17-bit data word
address.
2
AT24C1024SC
5045A–SEEPR–04/04
AT24C1024SC
Pin Capacitance
Table 2. Pin Capacitance(1)
Applicable over recommended operating range fromTA = 25°C, f = 1.0 MHz, VCC = +2.7V
Symbol
CI/O
Test Condition
Max
8
Units
pF
Conditions
VI/O = 0V
VIN = 0V
Input/Output Capacitance (SDA)
Input Capacitance (SCL)
CIN
6
pF
Note:
1. This parameter is characterized and is not 100% tested.
DC Characteristics
Table 3. DC Characteristics(1)
Symbol
VCC
Parameter
Test Condition
Min
Typ
Max
5.5
2.0
5.0
3.0
6.0
3.0
Units
V
Supply Voltage
Supply Current
Supply Current
2.7
ICC1
VCC = 5.0V
VCC = 5.0V
VCC = 2.7V
Read at 400 kHz
mA
mA
µA
ICC2
Write at 400 kHz
ISB
Standby Current
VIN = VCC or GND
V
CC = 5.5V
ILI
Input Leakage Current
VIN = VCC or GND
VOUT = VCC or GND
0.10
0.05
µA
µA
Output Leakage
Current
ILO
3.0
VIL
Input Low Level(2)
Input High Level(2)
Output Low Level
−0.6
V
CC x 0.3
V
V
V
VIH
VOL
VCC x 0.7
VCC + 0.5
0.4
VCC = 3.0V
IOL = 2.1 mA
Note:
1. Applicable over recommended operating range fromTAC = 0°C to +70°C, VCC = +2.7V to +5.5V (unless otherwise noted)
2. VIL min and VIH max are reference only and are not tested.
AC Characteristics
Table 4. AC Characteristics(1)
2.7-volt
Max
5.0-volt
Max
Symbol
fSCL
Parameter
Min
Min
Units
kHz
µs
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Clock Low to Data Out Valid
400
1000
tLOW
1.3
0.6
0.4
0.4
tHIGH
tAA
µs
0.05
0.9
0.05
0.55
µs
Time the bus must be free before a new
transmission can start(2)
tBUF
1.3
0.5
µs
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
Start Hold Time
0.6
0.6
0
0.25
0.25
0
µs
µs
µs
ns
µs
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time(2)
100
100
0.3
0.3
3
5045A–SEEPR–04/04
Table 4. AC Characteristics(1) (Continued)
2.7-volt
Max
5.0-volt
Symbol
Parameter
Min
Min
Max
Units
tF
Inputs Fall Time(2)
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
5.0V, 25°C, Page Mode
300
100
ns
tSU.STO
tDH
0.6
50
0.25
50
µs
ns
tWR
10
10
ms
Endurance(2)
100K
100K
Write Cycles
Note:
1. Applicable over recommended operating range from TA = 0°C to +70°C, VCC = +2.7V to +5.5V, CL = 100 pF (unless other-
wise noted). Test conditions are listed in Note 2.
2. This parameter is characterized and is not 100% tested.
3. AC measurement conditions:
RL (connects to VCC): 1.3 kΩ (2.7V, 5V)
Input pulse voltages: 0.3VCC to 0.7VCC
Input rise and fall times: ≤ 50ns
Input and output timing reference voltages: 0.5VCC
4
AT24C1024SC
5045A–SEEPR–04/04
AT24C1024SC
Device Operation
CLOCK AND DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL-low time periods (see
Figure 5 on page 6). Data changes during SCL-high periods will indicate a start or stop
condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
that must precede any other command (see Figure 6 on page 7).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (Figure 6 on page 7).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to
acknowledge that it has received each word.
STANDBY MODE: The AT24C1024SC features a low-power standby mode that is
enabled upon power-up and after the receipt of the stop bit and the completion of any
internal operations.
MEMORY RESET: After an interruption in protocol, power loss, or system reset, any
two-wire part can be reset by following these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition as SDA is high.
5
5045A–SEEPR–04/04
Timing Diagrams
Bus Timing
Figure 3. Bus Timing(1)
Note:
1. SCL: Serial Clock; SDA: Serial Data I/O
2. The write cycle time tWR is the time from a valid stop condition of a write sequence to
the end of the internal clear/write cycle.
Write Cycle Timing
Figure 4. Write Cycle Timing
(1)
tWR
Note:
1. SCL: Serial Clock; SDA: Serial Data I/O
Data Validity
Figure 5. Data Validity
SDA
SCL
DATA STABLE
DATA STABLE
DATA
CHANGE
6
AT24C1024SC
5045A–SEEPR–04/04
AT24C1024SC
Start and Stop Definition Figure 6. Start and Stop Definition
SDA
SCL
START
STOP
Output Acknowledge
Figure 7. Output Acknowledge
SCL
DATA IN
DATA OUT
START
ACKNOWLEDGE
7
5045A–SEEPR–04/04
Device Addressing
The 1024K EEPROM requires an 8-bit device address word following a start condition to
enable the chip for a read or write operation (see Figure 8). The device address word
consists of a mandatory “one, zero” sequence for the first four most significant bits as
shown. This is common to all two-wire EEPROM devices.
The next three bits of the device address word are unused. These three unused bits
should be set to “0”.
The seventh bit (P0) of the device address is a memory page address bit. The memory
page address bit is the most significant bit of the data word address that follows.
The eighth bit of the device address is the read/write operation select bit. A read opera-
tion is initiated if this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a “0”. If a compare is
not made, the device will return to a standby state.
Figure 8. Device Address
1
0
1
0
0
0
P0 R/W
LSB
MSB
Write Operations
BYTE WRITE: To select a data word in the 1024K memory requires a 17-bit word
address. The word address field consists of the P0 bit of the device address, then the
most significant word address followed by the least significant word address (see Figure
9).
A write operation requires the P0 bit and two 8-bit word addresses following the device
address word and acknowledgment. Upon receipt of this address, the EEPROM will
again respond with a “0” and then clock in the first 8-bit data word. Following receipt of
the 8-bit data word, the EEPROM will output a “0”. The addressing device, such as a
microcontroller, then must terminate the write sequence with a stop condition. At this
time the EEPROM enters an internally-timed write cycle, tWR, to the nonvolatile memory.
All inputs are disabled during this write cycle and the EEPROM will not respond until the
write is complete (see Figure 9).
Figure 9. Byte Write
LEAST
MOST SIGNIFICANT
SIGNIFICANT
P0
PAGE WRITE: The 1024K EEPROM is capable of 256-byte page writes.
A page write is initiated the same way as a byte write, but the microcontroller does not
send a stop condition after the first data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcontroller can transmit up to 255
more data words. The EEPROM will respond with a “0” after each data word received.
The microcontroller must terminate the page write sequence with a stop condition (see
Figure 10).
8
AT24C1024SC
5045A–SEEPR–04/04
AT24C1024SC
Figure 10. Page Write
LEAST
MOST SIGNIFICANT
SIGNIFICANT
P0
L
S
B
The lower eight data word address bits are internally incremented following the receipt
of each data word. The higher data word address bits are not incremented, retaining the
memory page row location. When the word address, internally generated, reaches the
page boundary, the following byte is placed at the beginning of the same page. If more
than 256 data words are transmitted to the EEPROM, the data word address will “roll
over” and previous data will be overwritten. The address “roll over” during write is from
the last byte of the current page to the first byte of the same page.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-
ing a start condition followed by the device address word. The read/write bit is
representative of the operation desired. Only if the internal write cycle has completed
will the EEPROM respond with a “0”, allowing the read or write sequence to continue.
9
5045A–SEEPR–04/04
Read Operations
Read operations are initiated the same way as write operations with the exception that
the read/write select bit in the device address word is set to one. There are three read
operations: current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the
last address accessed during the last read or write operation, incremented by one. This
address stays valid between operations as long as the chip power is maintained. The
address “roll over” during read is from the last byte of the last memory page to the first
byte of the first page.
Once the device address with the read/write select bit set to one is clocked in and
acknowledged by the EEPROM, the current address data word is serially clocked out.
The microcontroller does not respond with an input “0” but does generate a following
stop condition (see Figure 11).
Figure 11. Current Address Read
S
R
E
A
D
T
A
R
T
S
T
O
P
DEVICE
ADDRESS
SDA LINE
R
/
W
DATA
M
S
B
A
C
K
N
O
L
S
B
A
C
K
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the
data word address. Once the device address word and data word address are clocked
in and acknowledged by the EEPROM, the microcontroller must generate another start
condition. The microcontroller now initiates a current address read by sending a device
address with the read/write select bit high. The EEPROM acknowledges the device
address and serially clocks out the data word. The microcontroller does not respond
with a “0” but does generate a following stop condition (see Figure 12).
Figure 12. Random Read
S
T
A
R
T
W
R
I
T
E
S
T
A
R
T
S
T
O
P
R
E
A
D
1st, 2nd WORD
ADDRESS n
DEVICE
ADDRESS
DEVICE
ADDRESS
0
SDA LINE
M
S
B
DATA n
P0
A
C
K
L
S C
B
A
A
C
K
N
O
R
/
W
K
A
C
K
DUMMY WRITE
10
AT24C1024SC
5045A–SEEPR–04/04
AT24C1024SC
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or
a random address read. After the microcontroller receives a data word, it responds with
an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to
increment the data word address and serially clock out sequential data words. When the
memory address limit is reached, the data word address will “roll over” and the sequen-
tial read will continue. The sequential read operation is terminated when the
microcontroller does not respond with a “0” but does generate a following stop condition
(see Figure 13)
Figure 13. Sequential Read.
S
T
A
R
T
W
R
I
T
E
S
T
A
R
T
S
T
O
P
R
E
A
D
1st, 2nd WORD
ADDRESS n
DEVICE
ADDRESS
DEVICE
ADDRESS
0
SDA LINE
M
S
B
DATA n
P0
A
C
K
L
S C
B
A
A
C
K
N
O
R
/
W
K
A
C
K
DUMMY WRITE
11
5045A–SEEPR–04/04
AT24C32SC Ordering Information
Ordering Code
Package(1)
Voltage Range
2.7V–5.5V
Temperature Range
Commercial (0°C–70°C)
Commercial (0°C–70°C)
Industrial (−40°C–85°C)
AT24C1024SC-09AT
AT24C1024SC-09BT
AT24C1024SC-10WI
M2 – A Module
M2 – B Module
7 mil Wafer
2.7V–5.5V
2.7V–5.5V
Package Type(1)
M2 – A Module
M2 – B Module
Description
M2 ISO 7816 Smart Card Module
M2 ISO 7816 Smart Card Module with Atmel Logo
Note:
1. Formal drawings may be obtained from an Atmel sales office.
12
AT24C1024SC
5045A–SEEPR–04/04
AT24C1024SC
Smart Card Module
Ordering Code: 09AT
Ordering Code: 09BT
Module Size: M2
Module Size: M2
Dimension*: 12.6 x 11.4 [mm]
Glob Top: Square - 8.6 x 8.6 [mm]
Thickness: 0.58 [mm] max.
Pitch: 14.25 mm
Dimension*: 12.6 x 11.4 [mm]
Glob Top: Square - 8.6 x 8.6 [mm]
Thickness: 0.58 [mm] max.
Pitch: 14.25 mm
Note:
* 1
The module dimensions listed refer to the dimensions of the exposed metal contact
area. The actual dimensions of the module after excise or punching from the carrier tape
are generally 0.4 mm greater in both directions (i.e., a punched M2 module will yield
13.0 x 11.8 mm).
13
5045A–SEEPR–04/04
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5045A–SEEPR–04/04
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