AT24C11-10PN-2.7 [ATMEL]
EEPROM, 128X8, Serial, PDIP8;
| 型号： | AT24C11-10PN-2.7 |
| 厂家： | 
ATMEL |
| 描述： | EEPROM, 128X8, Serial, PDIP8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
| 文件： | 总15页 (文件大小：294K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
•
•
•
•
•
•
•
•
Low Voltage and Standard Voltage Operation: 2.7 (VCC = 2.7V to 5.5V)
Internally Organized 128 x 8
Two-wire Serial Interface
Bidirectional Data Transfer Protocol
1 MHz (2.7V, 5V) Compatibility
4-Byte Page Write Mode
Self-Timed Write Cycle (5 ms max)
High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
Two-wire
•
•
Automotive Grade and Lead-Free/Halogen-Free Devices Available
8-lead PDIP, 8-lead JEDEC SOIC, 8-lead TSSOP Packages
Automotive
Temperature
Serial EEPROM
1K (128 x 8)
Description
The AT24C11 provides 1024 bits of serial electrically erasable and programmable
read only memory (EEPROM) organized as 128 words of 8 bits each. The device is
optimized for use in many automotive applications where low power and low voltage
operation are essential. The AT24C11 is available in space saving 8-lead PDIP, 8-lead
JEDEC SOIC, and 8-lead TSSOP packages and is accessed via a Two-wire serial
interface. In addition, the entire family is available in 2.7V (2.7V to 5.5V).
AT24C11
Table 1. Pin Configuration
Pin Name
NC
Function
No Connect
SDA
Serial Data
SCL
Serial Clock Input
Test Input (GND or VCC)
TEST
8-lead TSSOP
NC
NC
1
2
3
4
8
7
6
5
VCC
TEST
SCL
NC
GND
SDA
8-lead SOIC
NC
NC
1
8
7
6
5
VCC
TEST
SCL
2
3
4
NC
GND
SDA
8-lead PDIP
NC
NC
NC
1
2
3
4
8
7
6
5
VCC
TEST
SCL
GND
SDA
Rev. 5093C–SEEPR–09/06
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Operating Temperature..................................–55°C to +125°C
Storage Temperature.....................................–65°C to +150°C
Voltage on Any Pin
with Respect to Ground....................................–1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Figure 1. Block Diagram
2
AT24C11
5093C–SEEPR–09/06
AT24C11
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.
Memory Organization AT24C11, 1K SERIAL EEPROM: Internally organized with 32 pages of 4 bytes each.
The 1K requires a 7-bit data word address for random word addressing.
Table 2. Pin Capacitance
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +2.7V to +5.5V
Symbol
CI/O
Test Condition
Max
8
Units
pF
Condition
VI/O = 0V
VIN = 0V
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL)
CIN
6
pF
Table 3. DC Characteristics
Applicable over recommended operating range from: TAE
noted)
= –40°C to +125°C, VCC = +2.7V to +5.5V (unless otherwise
Symbol
VCC1
VCC2
ICC
Parameter
Test Condition
Min
2.7
4.5
Typ
Max
5.5
Units
V
Supply Voltage
Supply Voltage
5.5
V
Supply Current VCC = 5.0V
Supply Current VCC = 5.0V
Standby Current VCC = 1.8V
Standby Current VCC = 2.5V
Standby Current VCC = 2.7V
Standby Current VCC = 5.0V
Input Leakage Current
Output Leakage Current
Input Low Level(1)
READ at 100 kHz
WRITE at 100 kHz
VIN = VCC or VSS
VIN = VCC or VSS
VIN = VCC or VSS
VIN = VCC or VSS
VIN = VCC or VSS
VOUT = VCC or VSS
0.4
2.0
1.0
mA
mA
µA
µA
µA
µA
µA
µA
V
ICC
3.0
ISB1
ISB2
ISB3
ISB4
ILI
0.6
3.0
1.4
4.0
1.6
4.0
8.0
18.0
3.0
0.10
0.05
ILO
3.0
VIL
–0.6
VCC × 0.3
VCC + 0.5
0.4
VIH
Input High Level(1)
VCC × 0.7
V
VOL2
VOL1
Output Low Level VCC = 3.0V
Output Low Level VCC = 1.8V
IOL = 2.1 mA
V
IOL = 0.15 mA
0.2
V
Note:
1. VIL min and VIH max are reference only and are not tested.
3
5093C–SEEPR–09/06
Table 4. AC Characteristics
Applicable over recommended operating range from TA = –40°C to +125°C, VCC = +2.7V
to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted)
2.7V, 5.0V
Symbol
fSCL
Parameter
Min
Max
Units
kHz
µs
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Clock Low to Data Out Valid
1000
tLOW
0.4
0.4
tHIGH
tAA
µs
0.05
0.55
µs
Time the bus must be free before a new
transmission can start(1)
tBUF
0.5
µs
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
Start Hold Time
0.25
0.6
0
µs
µs
µs
ns
µs
ns
µs
ns
ms
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time(1)
Inputs Fall Time(1)
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
100
0.3
tF
100
tSU.STO
tDH
0.25
50
tWR
5
Write
Cycles
Endurance(1)
5.0V, 25°C, Page Mode
1M
Note:
1. This parameter is ensured by characterization only.
4
AT24C11
5093C–SEEPR–09/06
AT24C11
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL low time periods (see
Figure 4 on page 6). Data changes during SCL high periods will indicate a start or stop
condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (see Figure 5 on page 7).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition
which terminates all communications. After a read sequence, the stop command will
place the EEPROM in a standby power mode (see Figure 5 on page 7).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from
the EEPROM in 8-bit words. Any device on the system bus receiving data (when com-
municating with the EEPROM) must pull the SDA bus low to acknowledge that it has
successfully received each word. This must happen during the ninth clock cycle after
each word received and after all other system devices have freed the SDA bus. The
EEPROM will likewise acknowledge by pulling SDA low after receiving each address or
data word (see Figure 6 on page 7).
STANDBY MODE: The AT24C11 features a low power standby mode which is enabled:
(a) upon power-up and (b) after the receipt of the STOP bit and the completion of any
internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-
wire part can be reset by following these steps:
(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then
(c) create a start condition as SDA is high.
5
5093C–SEEPR–09/06
Figure 2. Bus Timing
SCL: Serial Clock, SDA: Serial Data I/O
Figure 3. Write Cycle Timing
SCL: Serial Clock, SDA: Serial Data I/O
SCL
SDA
ACK
8th BIT
WORDn
(1)
wr
t
START
CONDITION
STOP
CONDITION
Note:
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
Figure 4. Data Validity
6
AT24C11
5093C–SEEPR–09/06
AT24C11
Figure 5. Start and Stop Definition
Figure 6. Output Acknowledge
7
5093C–SEEPR–09/06
Write Operations
BYTE WRITE: Following a start condition, a write operation requires a 7-bit data word
address and a low write bit. Upon receipt of this address, the EEPROM will again
respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-
bit data word, the EEPROM will output a zero and the addressing device, such as a
microcontroller, must terminate the write sequence with a stop condition. At this time the
EEPROM enters an internally-timed write cycle to the nonvolatile memory. All inputs are
disabled during this write cycle, tWR, and the EEPROM will not respond until the write is
complete (see refer to Figure 7 on page 9).
PAGE WRITE: The AT24C11 is capable of a 4-byte page write.
A page write is initiated the same as a byte write but the microcontroller does not send a
stop condition after the first data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcontroller can transmit up to three
more data words. The EEPROM will respond with a zero after each data word received.
The microcontroller must terminate the page write sequence with a stop condition (see
Figure 8 on page 9).
The data word address lower 2 bits are internally incremented following the receipt of
each data word. The higher five data word address bits are not incremented, retaining
the memory page row location. When the word address, internally generated, reaches
the page boundary, the following byte is placed at the beginning of the same page. If
more than four data words are transmitted to the EEPROM, the data word address will
“roll over” and previous data will be overwritten. Access to 1 additional page is available
upon request.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-
ing a start condition followed by the device address word. The read/write bit is
representative of the operation desired. Only if the internal write cycle has completed
will the EEPROM respond with a zero allowing the read or write sequence to continue.
Read Operations
Read operations are initiated the same way as write operations with the exception that
the read/write select bit in the device address word is set to one. There are two read
operations: byte read and sequential read.
BYTE READ: A byte read is initiated with a start condition followed by a 7-bit data word
address and a high read bit. The AT24C11 will respond with an acknowledge and then
serially output 8 data bits. The microcontroller does not respond with a zero but does
generate a following stop condition (see Figure 9 on page 9).
SEQUENTIAL READ: Sequential reads are initiated the same as a byte read. After the
microcontroller receives an 8-bit data word, it responds with an acknowledge. As long as
the EEPROM receives an acknowledge, it will continue to increment the data word
address and serially clock out sequential data words. When the memory address limit is
reached, the data word address will “roll over” and the sequential read will continue. The
sequential read operation is terminated when the microcontroller does not respond with
an input zero but does generate a following stop condition (see Figure 10 on page 9).
8
AT24C11
5093C–SEEPR–09/06
AT24C11
Figure 7. Byte Write
Figure 8. Page Write
Figure 9. Byte Read
Figure 10. Sequential Read
9
5093C–SEEPR–09/06
AT24C11 Ordering Information
Ordering Code
Package
Operation Range
8P3
8S1
8A2
AT24C11-10PE-2.7
AT24C11N-10SE-2.7
AT24C11-10TE-2.7
Automotive Temperature
(–40°C to 85°C)
AT24C11-10PQ-2.7(1)
AT24C11N-10SQ-2.7(1)
AT24C11-10TQ-2.7(1)
8P3
8S1
8A2
Lead-free/Halogen-free/
Automotive Temperature
(–40°C to 85°C)
Notes: 1. “Q” designates Green Package + RoHS compliant.
2. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics
tables.
Package Type
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
Options
8P3
8S1
8A2
–2.7
Low-Voltage (2.7V to 5.5V)
10
AT24C11
5093C–SEEPR–09/06
AT24C11
Packaging Information
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
MIN
MAX
NOM
NOTE
SYMBOL
D1
A2 A
A
0.210
0.195
0.022
0.070
0.045
0.014
0.400
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
4 PLCS
0.310
0.250
0.325
0.280
b
E1
e
0.100 BSC
0.300 BSC
0.115
Side View
eA
L
4
0.130
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
B
R
11
5093C–SEEPR–09/06
8S1 – JEDEC SOIC
C
1
E
E1
L
N
Top View
End View
e
B
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.35
0.10
MAX
1.75
0.25
NOM
NOTE
SYMBOL
A1
A
–
–
A1
b
0.31
0.17
4.80
3.81
5.79
–
0.51
0.25
5.00
3.99
6.20
C
D
E1
E
e
–
–
D
–
–
Side View
1.27 BSC
L
0.40
0˚
–
–
1.27
8˚
Note:
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03
REV.
TITLE
DRAWING NO.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
8S1
B
R
Small Outline (JEDEC SOIC)
12
AT24C11
5093C–SEEPR–09/06
AT24C11
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
3.00
NOTE
SYMBOL
D
2.90
3.10
2, 5
A
b
E
6.40 BSC
4.40
E1
A
4.30
–
4.50
1.20
1.05
0.30
3, 5
4
–
A2
b
0.80
0.19
1.00
e
A2
–
D
e
0.65 BSC
0.60
L
0.45
0.75
Side View
L1
1.00 REF
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02
DRAWING NO.
TITLE
REV.
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
2325 Orchard Parkway
San Jose, CA 95131
B
8A2
R
13
5093C–SEEPR–09/06
Revision History
Doc. Rev.
Comments
5093C
Revision history implemented; Removed ‘Preliminary’ status from datasheet.
14
AT24C11
5093C–SEEPR–09/06
Atmel Corporation
Atmel Operations
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San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Memory
RF/Automotive
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Tel: (49) 71-31-67-0
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San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
Regional Headquarters
Microcontrollers
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San Jose, CA 95131, USA
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Japan
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Japan
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5093C–SEEPR–09/06
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