AT24C256BN-10SU-2.7 [ATMEL]
EEPROM, 32KX8, Serial, PDSO8;
| 型号： | AT24C256BN-10SU-2.7 |
| 厂家： | 
ATMEL |
| 描述： | EEPROM, 32KX8, Serial, PDSO8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总18页 (文件大小：306K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 3.6V)
• Internally Organized as 32,768 x 8
• 2-wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 1 MHz (5V), 400 kHz (2.7V, 2.5V) and 100 kHz (1.8V) Compatibility
• Write Protect Pin for Hardware and Software Data Protection
• 64-byte Page Write Mode (Partial Page Writes Allowed)
• Self-timed Write Cycle (5 ms Max)
2-wire Serial
EEPROM
• High Reliability
– Endurance: One Million Write Cycles
– Data Retention: 40 Years
• Extended Temperature and Lead-free/Halogen-free Devices Available
• 8-lead JEDEC PDIP, 8-lead JEDEC 12
256K (32,768 x 8)
• SOIC, 8-lead MAP, 8-lead TSSOP and 8-ball dBGA2TM Packages
Description
AT24C256B
The AT24C256B provides 262,144 bits of serial electrically erasable and programma-
ble read only memory (EEPROM) organized as 32,768 words of 8 bits each. The
device’s cascadable feature allows up to 8 devices to share a com mon 2-wire bus.
The device is optimized for use in many industrial and commercial applications where
low power and low voltage operation are essential. The devices are available in
space-saving 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead MAP, 8-lead TSSOP
and 8-ball dBGA2 packages. In addition, the entire family is available in 2.7V (2.7V to
5.5V) and 1.8V (1.8V to 3.6V) versions.
Preliminary
Pin Configurations
8-lead PDIP
8-lead SOIC
Pin Name
A0–A2
SDA
Function
1
2
3
4
8
7
6
5
8
7
6
5
A0
A1
VCC
WP
A0
A1
1
2
3
4
VCC
WP
Address Inputs
Serial Data
Serial Clock Input
Write Protect
No Connect
Ground
A2
SCL
SDA
A2
SCL
SDA
GND
GND
SCL
WP
8-lead dBGA2
8
8-lead TSSOP
NC
VCC
1
A0
8
A0
1
2
3
4
VCC
WP
SCL
SDA
7
6
5
2
3
4
A1
GND
7
6
5
A1
A2
WP
A2
SCL
SDA
GND
GND
8-lead MAP
VCC
WP
8
7
6
5
1
2
3
4
A0
A1
A2
SCL
SDA
GND
Rev. 0670O–SEEPR–7/04
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only;
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Operating Temperature......................................−55°C to +125°C
Storage Temperature .........................................−65°C to +150°C
Voltage on Any Pin
with Respect to Ground........................................ −1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Block Diagram
2
AT24C256B
0670O–SEEPR–7/04
AT24C256B
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive-edge clock data into each
EEPROM device and negative-edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-
drain driven and may be wire-ORed with any number of other open-drain or open-collector
devices.
DEVICE/ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that
are hardwired or left not connected for hardware compatibility with other AT24CXX devices.
When the pins are hardwired, as many as eight 256K devices may be addressed on a single
bus system (device addressing is discussed in detail in Device Addressing, page 8). If the pins
are left floating, the A2, A1 and A0 pins will be internally pulled down to GND if the capacitive
coupling to the circuit board VCC plane is <3 pF. If coupling is >3 pF, Atmel recommends con-
necting the address pins to GND.
WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal
write operations. When WP is connected high to VCC, all write operations to the memory are
inhibited. If the pin is left floating, the WP pin will be internally pulled down to GND if the
capacitive coupling to the circuit board VCC plane is <3 pF. If coupling is >3 pF, Atmel recom-
mends connecting the pin to GND.
Memory
Organization
AT24C256B, 256K SERIAL EEPROM: The 256K is internally organized as 512 pages of 64-
bytes each. Random word addressing requires a 15-bit data word address.
3
0670O–SEEPR–7/04
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V.
Symbol
CI/O
Test Condition
Max
8
Units
pF
Conditions
VI/O = 0V
VIN = 0V
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, SCL)
CIN
6
pF
Note:
1. This parameter is characterized and is not 100% tested.
DC Characteristics(1)
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V; TAE= −40°C to +125°C,
V
CC = +2.7V to +5.5V(unless otherwise noted).
Symbol
Parameter
Test Condition
Min
1.8
2.5
4.5
Typ
Max
3.6
5.5
5.5
2.0
3.0
0.2
2.0
0.5
6.0
Units
V
VCC1
VCC2
VCC3
ICC1
Supply Voltage
Supply Voltage
Supply Voltage
Supply Current
Supply Current
V
V
VCC = 5.0V
VCC = 5.0V
READ at 400 kHz
WRITE at 400 kHz
1.0
2.0
mA
mA
µA
ICC2
V
CC = 1.8V
Standby Current
(1.8V option)
ISB1
VIN = VCC or VSS
VCC = 3.6V
V
V
CC = 2.5V
CC = 5.5V
µA
Standby Current
(2.5V option)
ISB2
VIN = VCC or VSS
Standby Current
(5.0V option)
ISB3
ILI
V
CC = 4.5 - 5.5V VIN = VCC or VSS
6.0
3.0
3.0
µA
µA
µA
Input Leakage Current
VIN = VCC or VSS
0.10
0.05
Output Leakage
Current
ILO
VOUT = VCC or VSS
VIL
Input Low Level(1)
Input High Level(1)
Output Low Level
Output Low Level
-0.6
VCC x 0.3
VCC + 0.5
0.4
V
V
V
V
VIH
VCC x 0.7
VOL2
VOL1
VCC = 3.0V
VCC = 1.8V
IOL = 2.1 mA
IOL = 0.15 mA
0.2
Notes: 1. VIL min and VIH max are reference only and are not tested.
4
AT24C256B
0670O–SEEPR–7/04
AT24C256B
AC Characteristics – Industrial Temperature
Applicable over recommended operating range from TAI = −40°C to +85°C, VCC = +1.8V to +5.5V, CL = 100 pF (unless oth-
erwise noted). Test conditions are listed in Note 2.
1.8-volt
Max
2.5-volt
Max
5.0-volt
Max
Symbol
fSCL
Parameter
Min
Min
Min
Units
kHz
µs
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Clock Low to Data Out Valid
400
1000
1000
tLOW
1.3
0.6
0.4
0.4
0.4
0.4
tHIGH
tAA
µs
0.05
0.9
0.05
0.55
0.05
0.55
µs
Time the bus must be free before a
new transmission can start(1)
tBUF
1.3
0.5
0.5
µs
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
Start Hold Time
0.6
0.6
0
0.25
0.25
0
0.25
0.25
0
µs
µs
µs
ns
µs
ns
µs
ns
ms
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time(1)
Inputs Fall Time(1)
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
100
100
100
0.3
0.3
0.3
tF
300
100
100
tSU.STO
tDH
0.6
50
0.25
50
0.25
50
tWR
5
5
5
Write
Cycles
Endurance(1)
25°C, Page Mode, 3.3V
1,000,000
Notes: 1. This parameter is characterized and is not 100% tested.
2. AC measurement conditions:
RL (connects to VCC): 1.3 kΩ (2.5V, 5V), 10 kΩ (1.8V)
Input pulse voltages: 0.3 VCC to 0.7 VCC
Input rise and fall times: ≤ 50 ns
Input and output timing reference voltages: 0.5 VCC
5
0670O–SEEPR–7/04
Device
Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external
device. Data on the SDA pin may change only during SCL low time periods (see Figure 3 on
page 7). Data changes during SCL high periods will indicate a start or stop condition as
defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition that
must precede any other command (see Figure 4 on page 7).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a
read sequence, the stop command will place the EEPROM in a standby power mode (see Fig-
ure 4 on page 7).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowl-
edge that it has received each word.
STANDBY MODE: The AT24C256B features a low-power standby mode that is enabled upon
power-up and after the receipt of the stop bit and the completion of any internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire
part can be reset by following these steps:
1. Clock up to 9 cycles;
2. Look for SDA high in each cycle while SCL is high;
3. Create a start condition as SDA is high.
Figure 1. Bus Timing*
* SCL: Serial Clock, SDA: Serial Data I/O
6
AT24C256B
0670O–SEEPR–7/04
AT24C256B
Figure 2. Write Cycle Timing*
SCL
ACK
SDA
8th BIT
WORDn
(1)
wr
t
START
CONDITION
STOP
CONDITION
* SCL: Serial Clock, SDA: Serial Data I/O
Note:
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end
of the internal clear/write cycle.
Figure 3. Data Validity
Figure 4. Start and Stop Definition
7
0670O–SEEPR–7/04
Figure 5. Output Acknowledge
Device
Addressing
The 256K EEPROM requires an 8-bit device address word following a start condition to enable
the chip for a read or write operation (see Figure 6 on page 9). The device address word con-
sists of a mandatory one, zero sequence for the first four most significant bits as shown. This
is common to all 2-wire EEPROM devices.
The next three bits are the A2, A1, A0 device address bits to allow as many as eight devices
on the same bus. These bits must compare to their corresponding hardwired input pins. The
A2, A1 and A0 pins use an internal proprietary circuit that biases them to a logic low condition
if the pins are allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read operation is
initiated if this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is not
made, the device will return to a standby state.
DATA SECURITY: The AT24C256B has a hardware data protection scheme that allows the
user to write protect the whole memory when the WP pin is at VCC
.
Write
Operations
BYTE WRITE: A write operation requires two 8-bit data word addresses following the device
address word and acknowledgment. Upon receipt of this address, the EEPROM will again
respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit
data word, the EEPROM will output a zero. The addressing device, such as a microcontroller,
then must terminate the write sequence with a stop condition. At this time the EEPROM enters
an internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during
this write cycle and the EEPROM will not respond until the write is complete (see Figure 7 on
page 10).
PAGE WRITE: The 256K EEPROM is capable of 64-byte page writes.
A page write is initiated the same way as a byte write, but the microcontroller does not send a
stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges
receipt of the first data word, the microcontroller can transmit up to 63 more data words. The
EEPROM will respond with a zero after each data word received. The microcontroller must ter-
minate the page write sequence with a stop condition (see Figure 8 on page 10).
8
AT24C256B
0670O–SEEPR–7/04
AT24C256B
The data word address lower 6 bits are internally incremented following the receipt of each
data word. The higher data word address bits are not incremented, retaining the memory page
row location. When the word address, internally generated, reaches the page boundary, the
following byte is placed at the beginning of the same page. If more than 64 data words are
transmitted to the EEPROM, the data word address will “roll over” and previous data will be
overwritten. The address “roll over” during write is from the last byte of the current page to the
first byte of the same page.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a
start condition followed by the device address word. The read/write bit is representative of the
operation desired. Only if the internal write cycle has completed will the EEPROM respond
with a zero, allowing the read or write sequence to continue.
Read
Operations
Read operations are initiated the same way as write operations with the exception that the
read/write select bit in the device address word is set to one. There are three read operations:
current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last
address accessed during the last read or write operation, incremented by one. This address
stays valid between operations as long as the chip power is maintained. The address “roll
over” during read is from the last byte of the last memory page, to the first byte of the first
page.
Once the device address with the read/write select bit set to one is clocked in and acknowl-
edged by the EEPROM, the current address data word is serially clocked out. The
microcontroller does not respond with an input zero but does generate a following stop condi-
tion (see Figure 9 on page 10).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data
word address. Once the device address word and data word address are clocked in and
acknowledged by the EEPROM, the microcontroller must generate another start condition.
The microcontroller now initiates a current address read by sending a device address with the
read/write select bit high. The EEPROM acknowledges the device address and serially clocks
out the data word. The microcontroller does not respond with a zero but does generate a fol-
lowing stop condition (see Figure 10 on page 10).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a ran-
dom address read. After the microcontroller receives a data word, it responds with an
acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment
the data word address and serially clock out sequential data words. When the memory
address limit is reached, the data word address will “roll over” and the sequential read will con-
tinue. The sequential read operation is terminated when the microcontroller does not respond
with a zero but does generate a following stop condition (see Figure 11 on page 11).
Figure 6. Device Address
1
0
1
0
A2
A1
A0
R/W
LSB
MSB
9
0670O–SEEPR–7/04
Figure 7. Byte Write
Figure 8. Page Write
Notes: (* = DON’T CARE bit))
Figure 9. Current Address Read
Figure 10. Random Read
Notes: (* = DON’T CARE bit)
10
AT24C256B
0670O–SEEPR–7/04
AT24C256B
Figure 11. Sequential Read
11
0670O–SEEPR–7/04
AT24C256B Ordering Information
Ordering Code
Package
Operation Range
AT24C256B-10PI-2.7
AT24C256BN-10SI-2.7
AT24C256BU2-10UI-2.7
AT24C256B-10TI-2.7
AT24C256BY1-10YI-2.7
8P3
8S1
Industrial Temperature
8U2-1
8A2
(−40°C to 85°C)
AT24C256B-10PI-1.8
AT24C256BN-10SI-1.8
AT24C256BU2-10UI-1.8
AT24C256B-10TI-1.8
AT24C256BY1-10YI-1.8
8P3
8S1
Industrial Temperature
8U2-1
8A2
(−40°C to 85°C)
AT24C256BN-10SU-2.7
AT24C256BN-10SU-1.8
AT24C256B-10TU-2.7
AT24C256B-10TU-1.8
8S1
8S1
8A2
8A2
Lead-free/Halogen-free/
Industrial Temperature
(−40°C to 85°C)
Note:
For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables.
Package Type
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8P3
8S1
8S2
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)
8-ball, die Ball Grid Array Package (dBGA2)
8U2-1
8A2
8Y1
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
Options
Low-voltage (2.7V to 5.5V)
−2.7
−1.8
Low-voltage (1.8V to 3.6V)
12
AT24C256B
0670O–SEEPR–7/04
AT24C256B
Packaging Information
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
MIN
MAX
NOM
NOTE
SYMBOL
D1
A2 A
A
0.210
0.195
0.022
0.070
0.045
0.014
0.400
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
4 PLCS
0.310
0.250
0.325
0.280
b
E1
e
0.100 BSC
0.300 BSC
0.130
Side View
eA
L
4
2
0.115
0.150
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
B
R
13
0670O–SEEPR–7/04
8S1 – JEDEC SOIC
C
1
E
E1
L
N
Top View
End View
e
B
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.35
0.10
MAX
1.75
0.25
NOM
NOTE
SYMBOL
A1
A
–
–
A1
b
0.31
0.17
4.80
3.81
5.79
–
0.51
0.25
5.00
3.99
6.20
C
D
E1
E
e
–
–
D
–
–
Side View
1.27 BSC
L
0.40
0˚
–
–
1.27
8˚
Note:
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03
REV.
TITLE
DRAWING NO.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
8S1
B
R
Small Outline (JEDEC SOIC)
14
AT24C256B
0670O–SEEPR–7/04
AT24C256B
8U2-1 – dBGA2
D
A1 BALL PAD CORNER
1.
b
E
A1
A
A2
Top View
A1 BALL PAD CORNER
Side View
2
1
A
B
C
D
e
(e1)
d
(d1)
COMMON DIMENSIONS
(Unit of Measure = mm)
Bottom View
8 Solder Balls
SYMBOL
MAX
1.00
0.25
0.50
0.35
MIN
0.81
0.15
0.40
0.25
NOM
0.91
NOTE
A
A1
A2
b
0.20
0.45
0.30
1
D
2.35 BSC
3.73 BSC
0.75 BSC
0.74 REF
0.75 BSC
0.80 REF
1. Dimension 'b' is measured at the maximum solder ball diameter.
This drawing is for general information only.
E
e
e1
d
d1
6/24/03
TITLE
REV.
DRAWING NO.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8U2-1, 8-ball, 2.35 x 3.73 mm Body, 0.75 mm pitch,
Small Die Ball Grid Array Package (dBGA2)
R
PO8U2-1
A
15
0670O–SEEPR–7/04
8Y1 – MAP
PIN 1 INDEX AREA
A
1
3
4
2
PIN 1 INDEX AREA
E1
D1
D
L
8
6
5
7
b
e
A1
E
Bottom View
End View
Top View
COMMON DIMENSIONS
(Unit of Measure = mm)
A
SYMBOL
MIN
–
MAX
0.90
0.05
5.10
3.20
1.15
1.15
0.35
NOM
–
NOTE
A
A1
D
0.00
4.70
2.80
0.85
0.85
0.25
–
4.90
3.00
1.00
1.00
0.30
0.65 TYP
0.60
Side View
E
D1
E1
b
e
L
0.50
0.70
2/28/03
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8Y1, 8-lead (4.90 x 3.00 mm Body) MSOP Array Package
(MAP) Y1
8Y1
C
R
16
AT24C256B
0670O–SEEPR–7/04
AT24C256B
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
3.00
NOTE
SYMBOL
D
2.90
3.10
2, 5
A
b
E
6.40 BSC
4.40
E1
A
4.30
–
4.50
1.20
1.05
0.30
3, 5
4
–
A2
b
0.80
0.19
1.00
e
A2
–
D
e
0.65 BSC
0.60
L
0.45
0.75
Side View
L1
1.00 REF
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02
DRAWING NO.
TITLE
REV.
2325 Orchard Parkway
San Jose, CA 95131
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
B
8A2
R
17
0670O–SEEPR–7/04
Atmel Corporation
Atmel Operations
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Tel: 1(408) 441-0311
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Memory
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2325 Orchard Parkway
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Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
Regional Headquarters
Microcontrollers
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Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
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Tel: 1(719) 576-3300
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Japan
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Fax: 1(719) 540-1759
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Fax: (44) 1355-242-743
Literature Requests
www.atmel.com/literature
Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard
warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any
errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and
does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are
granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use
as critical components in life support devices or systems.
© Atmel Corporation 2004. All rights reserved. Atmel® and combinations thereof, are the registered trademarks, and dBGA2™ is the
trademark of Atmel Corporation or its subsidiaries. Other terms and product names may be the trademarks of others.
Printed on recycled paper.
0670O–SEEPR–7/04
xM
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