AT24C512BY4-10YU-1.8 [ATMEL]
Two-wire Serial EEPROM 512K (65,536 x 8) with Three Device Address Inputs; 两线串行EEPROM 512K （ 65,536 ×8）用三个器件地址输入
| 型号： | AT24C512BY4-10YU-1.8 |
| 厂家： | 
ATMEL |
| 描述： | Two-wire Serial EEPROM 512K (65,536 x 8) with Three Device Address Inputs |
| 文件： | 总18页 (文件大小：350K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Low-voltage and Standard-voltage Operation
– 1.8 (VCC = 1.8V to 3.6V)
• Internally Organized 65,536 x 8
• Two-wire Serial Interface
• Schmitt Triggers, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 1 MHz (3.6V), 400 kHz (1.8V) Compatibility
• Write Protect Pin for Hardware and Software Data Protection
• 128-byte Page Write Mode (Partial Page Writes Allowed)
• Self-timed Write Cycle (5 ms Max)
Two-wire Serial
EEPROM
• High Reliability
– Endurance: 1,000,000 Write Cycles
– Data Retention: 40 Years
• Lead-free/Halogen-free Devices Available
• 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead TSSOP,
8-lead LAP and 8-lead SAP Packages
• Die Sales: Wafer Form, Waffle Pack and Bumped Die
512K (65,536 x 8)
AT24C512B
with Three Device
Address Inputs
Description
The AT24C512B provides 524,288 bits of serial electrically erasable and programma-
ble read only memory (EEPROM) organized as 65,536 words of 8 bits each. The
device’s cascadable feature allows up to four devices to share a common two-wire
bus. The device is optimized for use in many industrial and commercial applications
where low-power and low-voltage operation are essential. The devices are available in
space-saving 8-pin PDIP, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead Leadless Array
(LAP), and 8-lead SAP packages. In addition, the entire family is available in a 1.8V
(1.8V to 3.6V) version.
Preliminary
8-lead PDIP
Table 1. Pin Configurations
8-lead TSSOP
Pin Name
A0–A2
SDA
Function
A0
A1
1
2
3
4
8
7
6
5
VCC
WP
A0
A1
1
2
3
4
8
7
6
5
VCC
WP
Address Inputs
Serial Data
A2
SCL
SDA
A2
SCL
SDA
GND
GND
SCL
Serial Clock Input
Write Protect
No Connect
8-lead SOIC
WP
NC
A0
A1
1
2
3
4
8
7
6
5
VCC
WP
A2
SCL
SDA
GND
8-lead Leadless Array
8-lead SAP
VCC
WP
8
7
6
5
1
2
3
4
A0
VCC
WP
8
7
6
5
1
2
3
4
A0
A1
A1
SCL
SDA
A2
SCL
SDA
A2
GND
GND
Bottom View
Bottom View
Rev. 5112A–SEEPR–8/05
Absolute Maximum Ratings*
Operating Temperature..................................–55°C to +125°C
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature.....................................–65°C to +150°C
Voltage on Any Pin
with Respect to Ground....................................–1.0V to +7.0V
Maximum Operating Voltage ............................................ 4.3V
DC Output Current........................................................ 3.0 mA
Figure 1. Block Diagram
2
AT24C512B [Preliminary]
5112A–SEEPR–8/05
AT24C512B [Preliminary]
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device
address inputs that are hardwired (directly to GND or to Vcc) for compatibility with other
AT24Cxx devices. When the pins are hardwired, as many as eight 512K devices may be
addressed on a single bus system. (Device addressing is discussed in detail under
“Device Addressing,” page 8.) A device is selected when a corresponding hardware and
software match is true. If these pins are left floating, the A2, A1, and A0 pins will be
internally pulled down to GND. However, due to capacitive coupling that may appear
during customer applications, Atmel recommends always connecting the address pins
to a known state. When using a pull-up resistor, Atmel recommends using 10kΩ or less.
WRITE PROTECT (WP): The write protect input, when connected to GND, allows nor-
mal write operations. When WP is connected directly to Vcc, all write operations to the
memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down
to GND. However, due to capacitive coupling that may appear during customer applica-
tions, Atmel recommends always connecting the WP pins to a known state. When using
a pull-up resistor, Atmel recommends using 10kΩ or less.
Memory Organization AT24C512B, 512K SERIAL EEPROM: The 512K is internally organized as 512 pages
of 128-bytes each. Random word addressing requires a 16-bit data word address.
3
5112A–SEEPR–8/05
Table 2. Pin Capacitance(1)
Applicable over recommended operating range from: TA = 25°C, f = 1.0 MHz, VCC = +1.8V to +3.6V
Symbol
CI/O
Test Condition
Max
8
Units
pF
Conditions
VI/O = 0V
VIN = 0V
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, SCL)
CIN
6
pF
Note:
1. This parameter is characterized and is not 100% tested.
Table 3. DC Characteristics
Applicable over recommended operating range from: TAI = −40°C to +85°C, VCC = +1.8V to +3.6V (unless otherwise noted)
Symbol
VCC1
ICC1
Parameter
Test Condition
Min
Typ
Max
3.6
2.0
3.0
1.0
3.0
3.0
Units
V
Supply Voltage
Supply Current
Supply Current
1.8
VCC = 3.6V
VCC = 3.6V
VCC = 1.8V
VCC = 3.6V
VIN = VCC or VSS
READ at 400 kHz
WRITE at 400 kHz
1.0
2.0
mA
mA
µA
ICC2
Standby Current
(1.8V option)
ISB1
VIN = VCC or VSS
ILI
Input Leakage Current
0.10
0.05
µA
µA
Output Leakage
Current
ILO
VOUT = VCC or VSS
3.0
VIL
Input Low Level(1)
Input High Level(1)
Output Low Level
Output Low Level
−0.6
VCC x 0.3
VCC + 0.5
0.4
V
V
V
V
VIH
VCC x 0.7
VOL2
VOL1
VCC = 3.0V
VCC = 1.8V
IOL = 2.1 mA
IOL = 0.15 mA
0.2
Note:
1. VIL min and VIH max are reference only and are not tested.
4
AT24C512B [Preliminary]
5112A–SEEPR–8/05
AT24C512B [Preliminary]
Table 4. AC Characteristics (Industrial Temperature)
Applicable over recommended operating range from TAI = −40°C to +85°C, VCC = +1.8V to +3.6V, CL = 100 pF (unless oth-
erwise noted). Test conditions are listed in Note 2.
1.8-volt
Max
2.5-volt
Max
3.6-volt
Max
Symbol
fSCL
Parameter
Min
Min
Min
Units
kHz
µs
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Clock Low to Data Out Valid
400
1000
1000
tLOW
1.3
0.6
0.4
0.4
0.4
0.4
tHIGH
tAA
µs
0.05
0.9
0.05
0.55
0.05
0.55
µs
Time the bus must be free before a
new transmission can start(1)
tBUF
1.3
0.5
0.5
µs
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
Start Hold Time
0.6
0.6
0
0.25
0.25
0
0.25
0.25
0
µs
µs
µs
ns
µs
ns
µs
ns
ms
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time(1)
Inputs Fall Time(1)
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
100
100
100
0.3
0.3
0.3
tF
300
100
100
tSU.STO
tDH
0.6
50
0.25
50
0.25
50
tWR
5
5
5
Write
Cycles
Endurance(1)
25°C, Page Mode, 3.3V
1,000,000
Notes: 1. This parameter is characterized and is not 100% tested.
2. AC measurement conditions:
RL (connects to VCC): 1.3 kΩ (2.5V, 3.6V), 10 kΩ (1.8V)
Input pulse voltages: 0.3 VCC to 0.7 VCC
Input rise and fall times: ≤ 50 ns
Input and output timing reference voltages: 0.5 VCC
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL low time periods (see
Figure 4 on page 7). Data changes during SCL high periods will indicate a start or stop
condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (see Figure 5 on page 7).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (see Figure 5 on page 7).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to
acknowledge that it has received each word.
5
5112A–SEEPR–8/05
STANDBY MODE: The AT24C512B features a low power standby mode which is
enabled: a) upon power-up and b) after the receipt of the STOP bit and the completion
of any internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-
wire part can be reset by following these steps:
(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then
(c) create a start condition as SDA is high.
Figure 2. Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)
Figure 3. Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)
SCL
SDA
ACK
8th BIT
WORDn
(1)
t
wr
START
STOP
CONDITION
CONDITION
Note:
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
6
AT24C512B [Preliminary]
5112A–SEEPR–8/05
AT24C512B [Preliminary]
Figure 4. Data Validity
Figure 5. Start and Stop Definition
Figure 6. Output Acknowledge
7
5112A–SEEPR–8/05
Device Addressing
The 512K EEPROM requires an 8-bit device address word following a start condition to
enable the chip for a read or write operation (see Figure 7 on page 9). The device
address word consists of a mandatory “1”, “0” sequence for the first four most significant
bits as shown. This is common to all two-wire EEPROM devices.
The 512K uses the three device address bits A2, A1, A0 to allow as many as eight
devices on the same bus. These bits must compare to their corresponding hardwired
input pins. The A2, A1 and A0 pins use an internal proprietary circuit that biases them to
a logic low condition if the pins are allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read opera-
tion is initiated if this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a “0”. If a compare is
not made, the device will return to a standby state.
DATA SECURITY: The AT24C512B has a hardware data protection scheme that allows
the user to Write Protect the whole memory when the WP pin is at VCC
.
Write Operations
BYTE WRITE: A write operation requires two 8-bit data word addresses following the
device address word and acknowledgment. Upon receipt of this address, the EEPROM
will again respond with a “0” and then clock in the first 8-bit data word. Following receipt
of the 8-bit data word, the EEPROM will output a “0”. The addressing device, such as a
microcontroller, then must terminate the write sequence with a stop condition. At this
time the EEPROM enters an internally-timed write cycle, tWR, to the nonvolatile memory.
All inputs are disabled during this write cycle and the EEPROM will not respond until the
write is complete (see Figure 8 on page 10).
PAGE WRITE: The 512K EEPROM is capable of 128-byte page writes.
A page write is initiated the same way as a byte write, but the microcontroller does not
send a stop condition after the first data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcontroller can transmit up to 127
more data words. The EEPROM will respond with a “0” after each data word received.
The microcontroller must terminate the page write sequence with a stop condition (see
Figure 9 on page 10).
The data word address lower 7 bits are internally incremented following the receipt of
each data word. The higher data word address bits are not incremented, retaining the
memory page row location. When the word address, internally generated, reaches the
page boundary, the following byte is placed at the beginning of the same page. If more
than 128 data words are transmitted to the EEPROM, the data word address will “roll
over” and previous data will be overwritten. The address roll over during write is from the
last byte of the current page to the first byte of the same page.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-
ing a start condition followed by the device address word. The Read/Write bit is
representative of the operation desired. Only if the internal write cycle has completed
will the EEPROM respond with a “0”, allowing the read or write sequence to continue.
8
AT24C512B [Preliminary]
5112A–SEEPR–8/05
AT24C512B [Preliminary]
Read Operations
Read operations are initiated the same way as write operations with the exception that
the Read/Write select bit in the device address word is set to “1”. There are three read
operations: current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the
last address accessed during the last read or write operation, incremented by “1”. This
address stays valid between operations as long as the chip power is maintained. The
address roll over during read is from the last byte of the last memory page, to the first
byte of the first page.
Once the device address with the Read/Write select bit set to “1” is clocked in and
acknowledged by the EEPROM, the current address data word is serially clocked out.
The microcontroller does not respond with an input “0” but does generate a following
stop condition (see Figure 10 on page 10).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the
data word address. Once the device address word and data word address are clocked
in and acknowledged by the EEPROM, the microcontroller must generate another start
condition. The microcontroller now initiates a current address read by sending a device
address with the Read/Write select bit high. The EEPROM acknowledges the device
address and serially clocks out the data word. The microcontroller does not respond
with a “0” but does generate a following stop condition (see Figure 11 on page 10).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or
a random address read. After the microcontroller receives a data word, it responds with
an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to
increment the data word address and serially clock out sequential data words. When the
memory address limit is reached, the data word address will roll over and the sequential
read will continue. The sequential read operation is terminated when the microcontroller
does not respond with a “0” but does generate a following stop condition (see Figure 12
on page 11).
Figure 7. Device Address
1
0
1
0
A2
A1
A0
R/W
LSB
MSB
9
5112A–SEEPR–8/05
Figure 8. Byte Write
Figure 9. Page Write
Figure 10. Current Address Read
Figure 11. Random Read
10
AT24C512B [Preliminary]
5112A–SEEPR–8/05
AT24C512B [Preliminary]
Figure 12. Sequential Read
11
5112A–SEEPR–8/05
Ordering Information
Ordering Code
Package
Operation Range
AT24C512BC1-10CU-1.8(1)
AT24C512B-10PU-1.8(1)
AT24C512BN-10SU-1.8(1)
AT24C512B-10TU-1.8(1)
AT24C512BY4-10YU-1.8(1)
8CN1
8P3
8S1
8A2
8Y4
Lead-free/Halogen-free/
Industrial Temperature
(–40°C to 85°C)
AT24C512B-W1.8-11(2)
Die Sale
(–40°C to 85°C)
Notes: 1. “U” designates Green package + RoHS compliant.
2. Available in waffle pack and wafer form; order as SL719 for wafer form. Bumped die available upon request. Please contact
Serial EEPROM marketing.
Package Type
8-lead, 0.300" Wide, Leadless Array Package (LAP)
8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP)
8-lead, 0.150” Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
8-lead, 6.00 mm x 4.90 mm Body, Dual Footprint, Non-leaded, Small Array Package (SAP)
Options
8CN1
8P3
8S1
8A2
8Y4
–1.8
Low-voltage (1.8V to 3.6V)
12
AT24C512B [Preliminary]
5112A–SEEPR–8/05
AT24C512B [Preliminary]
Packaging Information
8CN1 – LAP
Marked Pin1 Indentifier
E
A
D
A1
Top View
Side View
Pin1 Corner
L1
0.10 mm
TYP
8
7
1
e
COMMON DIMENSIONS
(Unit of Measure = mm)
2
3
MIN
0.94
0.30
0.36
7.90
4.90
MAX
1.14
0.38
0.46
8.10
5.10
NOM
1.04
NOTE
SYMBOL
A
6
5
A1
b
0.34
b
0.41
1
4
D
8.00
E
5.00
e1
L
e
1.27 BSC
0.60 REF
.0.67
e1
L
Bottom View
0.62
0.92
0.72
1.02
1
1
L1
0.97
Note: 1. Metal Pad Dimensions.
2. All exposed metal area shall have the following finished platings.
Ni: 0.0005 to 0.015 mm
Au: 0.0005 to 0.001 mm
11/8/04
DRAWING NO.
REV.
B
TITLE
1150 E.Cheyenne Mtn Blvd.
Colorado Springs, CO 80906
8CN1, 8-lead (8 x 5 x 1.04 mm Body), Lead Pitch 1.27 mm,
8CN1
R
Leadless Array Package (LAP)
13
5112A–SEEPR–8/05
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
MIN
–
MAX
0.210
0.195
0.022
0.070
0.045
0.014
0.400
–
NOM
–
NOTE
SYMBOL
D1
A2 A
A
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
–
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
4 PLCS
0.310
0.250
0.100 BSC
0.300 BSC
0.130
0.325
0.280
b
E1
e
Side View
eA
L
4
2
0.115
0.150
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
B
R
14
AT24C512B [Preliminary]
5112A–SEEPR–8/05
AT24C512B [Preliminary]
8S1 – JEDEC SOIC
C
1
E
E1
L
N
∅
Top View
End View
e
B
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.35
0.10
MAX
1.75
0.25
NOM
NOTE
SYMBOL
A1
A
–
–
A1
B
C
D
E1
E
0.31
0.17
4.80
3.81
5.79
–
0.51
0.25
5.00
3.99
6.20
–
–
D
–
–
Side View
e
1.27 BSC
L
0.40
0°
–
–
1.27
∅
8°
Note:
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03
REV.
TITLE
DRAWING NO.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
8S1
B
R
Small Outline (JEDEC SOIC)
15
5112A–SEEPR–8/05
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
3.00
NOTE
SYMBOL
D
2.90
3.10
2, 5
A
b
E
6.40 BSC
4.40
E1
A
4.30
–
4.50
1.20
1.05
0.30
3, 5
4
–
A2
b
0.80
0.19
1.00
e
A2
–
D
e
0.65 BSC
0.60
L
0.45
0.75
Side View
L1
1.00 REF
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02
DRAWING NO.
TITLE
REV.
2325 Orchard Parkway
San Jose, CA 95131
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
B
8A2
R
16
AT24C512B [Preliminary]
5112A–SEEPR–8/05
AT24C512B [Preliminary]
8Y4 – SAP
PIN 1 INDEX AREA
A
PIN 1 ID
D
E1
L
A1
E
b
e
e1
A
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
–
MAX
0.90
0.05
6.20
5.10
3.15
3.15
0.45
NOM
–
NOTE
A
A1
D
0.00
5.80
4.70
2.85
2.85
0.35
–
6.00
E
4.90
D1
E1
b
3.00
3.00
0.40
e
1.27 TYP
3.81 REF
0.60
e1
L
0.50
0.70
5/24/04
TITLE
DRAWING NO.
REV.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8Y4, 8-lead (6.00 x 4.90 mm Body) SOIC Array Package
(SAP) Y4
8Y4
A
R
17
5112A–SEEPR–8/05
Atmel Corporation
Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Memory
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
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2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
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Microcontrollers
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Room 1219
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Chuo-ku, Tokyo 104-0033
Japan
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Fax: 1(719) 540-1759
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Tel: (44) 1355-803-000
Fax: (44) 1355-242-743
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