AT24C64B-10PI-2.7 [ATMEL]
EEPROM, 8KX8, Serial, CMOS, PDIP8, 0.300 INCH, PLASTIC, MS-001BA, DIP-8;
| 型号： | AT24C64B-10PI-2.7 |
| 厂家： | 
ATMEL |
| 描述： | EEPROM, 8KX8, Serial, CMOS, PDIP8, 0.300 INCH, PLASTIC, MS-001BA, DIP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
| 文件： | 总17页 (文件大小：255K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7 to 5.5V)
– 1.8 (VCC = 1.8 to 5.5V)
• Low-power Devices (ISB = 6 µA at 5.5V) Available
• Internally Organized 8192 x 8
• 2-Wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bi-directional Data Transfer Protocol
• 400 kHz Clock Rate
• Write Protect Pin for Hardware Data Protection
• 32-Byte Page Write Mode (Partial Page Writes Allowed)
• Self-Timed Write Cycle (5 ms max)
• High Reliability
2-Wire
Serial EEPROM
64K (8192 x 8)
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• Lead-free/Halogen-free Devices Available
• 8-lead PDIP, 8-lead JEDEC SOIC and 8-lead TSSOP Packages
• Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers
AT24C64B
Description
The AT24C64B provides 65,536 bits of serial electrically erasable and programmable
read only memory (EEPROM) organized as 8192 words of 8 bits each. The device’s
cascadable feature allows up to 8 devices to share a common 2-wire bus. The device
is optimized for use in many industrial and commercial applications where low power
and low voltage operation are essential. The AT24C64B is available in space saving
8-lead PDIP, 8-lead JEDEC SOIC and 8-lead TSSOP packages and is accessed via a
2-wire serial interface. In addition, the entire family is available in 2.7V (2.7 to 5.5V)
and 1.8V (1.8 to 5.5V) versions.
8-lead SOIC
2-Wire, 32K
Pin Configurations
Serial E2PROM
Pin Name
A0 - A2
SDA
Function
A0
A1
1
2
3
4
8
7
6
5
VCC
WP
Address Inputs
Serial Data
A2
SCL
SDA
GND
SCL
Serial Clock Input
Write Protect
WP
8-lead TSSOP
8-lead PDIP
A0
A1
1
2
3
4
8
7
6
5
VCC
WP
A0
A1
1
2
3
4
8
7
6
5
VCC
WP
A2
SCL
SDA
A2
SCL
SDA
GND
GND
3350D–SEEPR–05/05
1
AT24C64B
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Operating Temperature...................................... -55 to +125°C
Storage Temperature......................................... -65 to +150°C
Voltage on Any Pin
with Respect to Ground....................................... -1.0 to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Block Diagram
2
3350D–SEEPR–05/05
AT24C64B
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs
that are hard wired or left not connected for hardware compatibility with other AT24CXX
devices. When the pins are hardwired, as many as eight 64K devices may be addressed
on a single bus system (device addressing is discussed in detail under the Device
Addressing section). If the pins are left floating, the A2, A1 and A0 pins will be internally
pulled down to GND if the capacitive coupling to the circuit board VCC plane is <3pF.
If coupling is >3pF, Atmel recommends connecting the address pins to GND.
WRITE PROTECT (WP): The write protect input, when connected to GND, allows nor-
mal write operations. When WP is connected high to VCC, all write operations to the
upper quandrant (16K bits) of memory are inhibited. If the pin is left floating, the WP pin
will be internally pulled down to GND if the capacitive coupling to the circuit board VCC
plane is <3pF. If coupling is >3pF, Atmel recommends connecting the pin to GND.
Memory Organization AT24C64B, 64K SERIAL EEPROM: The 64K is internally organized as 256 pages of
32 bytes each. Random word addressing requires a 13 bit data word address.
3
3350D–SEEPR–05/05
AT24C64B
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V
Symbol
CI/O
Test Condition
Max
8
Units
pF
Conditions
VI/O = 0V
VIN = 0V
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL)
CIN
6
pF
Note:
1. This parameter is characterized and is not 100% tested.
DC Characteristics
Applicable over recommended operating range from: TAI = -40 to +85°C, VCC = +1.8 to +5.5V (unless otherwise noted)
Symbol
VCC1
VCC2
VCC3
ICC1
Parameter
Test Condition
Min
1.8
2.7
4.5
Typ
Max
5.5
5.5
5.5
1.0
3.0
Units
V
Supply Voltage
Supply Voltage
Supply Voltage
Supply Current
Supply Current
Standby Current
V
V
VCC = 5.0V
VCC = 5.0V
READ at 400 kHz
WRITE at 400 kHz
0.4
2.0
mA
mA
ICC2
ISB1
ISB2
ISB3
ILI
VCC = 1.8V
VCC = 2.7V
VIN = VCC or VSS
VIN = VCC or VSS
VIN = VCC or VSS
1.0
2.0
6.0
3.0
3.0
µA
µA
µA
µA
µA
(1.8V option)
Standby Current
(2.7V option)
Standby Current
(5V option)
VCC = 4.5 - 5.5V
Input Leakage
Current
VIN = VCC or VSS
0.10
0.05
Output Leakage
Current
ILO
VOUT = VCC or VSS
VIL
Input Low Level(1)
Input High Level(1)
Output Low Level
Output Low Level
-0.6
VCC x 0.3
VCC + 0.5
0.4
V
V
V
V
VIH
VCC x 0.7
VOL2
VOL1
VCC = 3.0V
VCC = 1.8V
IOL = 2.1 mA
IOL = 0.15 mA
0.2
Note:
1. VIL min and VIH max are reference only and are not tested.
4
3350D–SEEPR–05/05
AT24C64B
AC Characteristics
Applicable over recommended operating range from TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted)
AT24C64B
1.8V – 3.6V
5.0V
Max
Symbol
fSCL
Parameter
Min
Max
Min
Units
kHz
µs
Clock Frequency, SCL
400
400
tLOW
tHIGH
tI
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time(1)
Clock Low to Data Out Valid
1.3
0.6
1.2
0.6
µs
100
0.9
50
ns
tAA
0.2
1.3
0.6
0.6
0
0.1
1.2
0.6
0.6
0
0.9
µs
tBUF
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
Time the bus must be free before a new transmission can start(2)
µs
Start Hold Time
µs
Start Set-up Time
µs
Data In Hold Time
µs
Data In Set-up Time
100
100
ns
Inputs Rise Time(2)
0.3
0.3
µs
tF
Inputs Fall Time(2)
300
300
ns
tSU.STO
tDH
Stop Set-up Time
0.6
0.6
50
µs
Data Out Hold Time
200
ns
tWR
Write Cycle Time
5
5
ms
Write
Cycles
Endurance(1) 5.0V, 25°C, Page Mode
1M
1M
Notes: 1. This parameter is characterized and is not 100% tested (TA = 25°C)
2. This parameter is characterized and is not 100% tested.
5
3350D–SEEPR–05/05
AT24C64B
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL high periods will indicate a start
or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (refer to Start and Stop Definition timing
diagram).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to
acknowledge that it has received each word.
STANDBY MODE: The AT24C64B features a low power standby mode which is
enabled: a) upon power-up and b) after the receipt of the Stop bit and the completion of
any internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-
wire part can be reset by following these steps:
(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then
(c) create a start condition as SDA is high.
6
3350D–SEEPR–05/05
AT24C64B
Bus Timing
SCL: Serial Clock, SDA: Serial Data I/O
Write Cycle Timing
SCL: Serial Clock, SDA: Serial Data I/O
SCL
SDA
ACK
8th BIT
WORDn
(1)
t
wr
START
STOP
CONDITION
CONDITION
Note:
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
7
3350D–SEEPR–05/05
AT24C64B
Data Validity
Start and Stop Definition
Output Acknowledge
8
3350D–SEEPR–05/05
AT24C64B
Device
Addressing
The 64K EEPROM requires an 8-bit device address word following a start condition to enable
the chip for a read or write operation (see Figure 1 on page 11). The device address word con-
sists of a mandatory one, zero sequence for the first four most significant bits as shown. This
is common to all 2-wire EEPROM devices.
The 64K uses the three device address bits A2, A1, A0 to allow as many as eight devices on
the same bus. These bits must compare to their corresponding hardwired input pins. The A2,
A1, and A0 pins use an internal proprietary circuit that biases them to a logic low condition if
the pins are allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read operation is
initiated if this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is not
made, the device will return to standby state.
NOISE PROTECTION: Special internal circuitry placed on the SDA and SCL pins prevent
small noise spikes from activating the device. A low-VCC detector (5-volt option) resets the
device to prevent data corruption in a noisy environment.
DATA SECURITY: The AT24C64B has a hardware data protection scheme that allows the
user to write protect the upper quadrant (16K bits) of memory when the WP pin is at VCC
.
Write
Operations
BYTE WRITE: A write operation requires two 8-bit data word addresses following the device
address word and acknowledgment. Upon receipt of this address, the EEPROM will again
respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit
data word, the EEPROM will output a zero and the addressing device, such as a microcontrol-
ler, must terminate the write sequence with a stop condition. At this time the EEPROM enters
an internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during
this write cycle and the EEPROM will not respond until the write is complete (see Figure 2 on
page 11).
PAGE WRITE: The 64K EEPROM is capable of 32-byte page writes.
A page write is initiated the same way as a byte write, but the microcontroller does not send a
stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges
receipt of the first data word, the microcontroller can transmit up to 31 more data words. The
EEPROM will respond with a zero after each data word received. The microcontroller must ter-
minate the page write sequence with a stop condition (see Figure 3 on page 11).
The data word address lower 5 bits are internally incremented following the receipt of each
data word. The higher data word address bits are not incremented, retaining the memory page
row location. When the word address, internally generated, reaches the page boundary, the
following byte is placed at the beginning of the same page. If more than 32 data words are
transmitted to the EEPROM, the data word address will “roll over” and previous data will be
overwritten.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a
start condition followed by the device address word. The read/write bit is representative of the
operation desired. Only if the internal write cycle has completed will the EEPROM respond
with a zero, allowing the read or write sequence to continue.
9
3350D–SEEPR–05/05
AT24C64B
Read Operations
Read operations are initiated the same way as write operations with the exception that
the read/write select bit in the device address word is set to one. There are three read
operations: current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the
last address accessed during the last read or write operation, incremented by one. This
address stays valid between operations as long as the chip power is maintained. The
address “roll over” during read is from the last byte of the last memory page, to the first
byte of the first page. The address “roll over” during write is from the last byte of the cur-
rent page to the first byte of the same page.
Once the device address with the read/write select bit set to one is clocked in and
acknowledged by the EEPROM, the current address data word is serially clocked out.
The microcontroller does not respond with an input zero but does generate a following
stop condition (see Figure 4 on page 12).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the
data word address. Once the device address word and data word address are clocked
in and acknowledged by the EEPROM, the microcontroller must generate another start
condition. The microcontroller now initiates a current address read by sending a device
address with the read/write select bit high. The EEPROM acknowledges the device
address and serially clocks out the data word. The microcontroller does not respond
with a zero but does generate a following stop condition (see Figure 5 on page 12).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or
a random address read. After the microcontroller receives a data word, it responds with
an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to
increment the data word address and serially clock out sequential data words. When the
memory address limit is reached, the data word address will “roll over” and the sequen-
tial read will continue. The sequential read operation is terminated when the
microcontroller does not respond with a zero but does generate a following stop condi-
tion (see Figure 6 on page 12).
10
3350D–SEEPR–05/05
AT24C64B
Figure 1. Device Address
Figure 2. Byte Write
Figure 3. Page Write
Note:
1. * = DON’T CARE bits
11
3350D–SEEPR–05/05
AT24C64B
Figure 4. Current Address Read
Figure 5. Random Read
Note:
1. * = DON’T CARE bits
Figure 6. Sequential Read
12
3350D–SEEPR–05/05
AT24C64B
AT24C64B Ordering Information(1)
Ordering Code
Package
8P3
Operation Range
AT24C64B-10PI-2.7
AT24C64BN-10SI-2.7
AT24C64B-10TI-2.7
Industrial Temperature
8S1
8A2
(-40°C to 85°C)
AT24C64B-10PI-1.8
AT24C64BN-10SI-1.8
AT24C64B-10TI-1.8
8P3
8S1
8A2
Industrial Temperature
(-40°C to 85°C)
AT24C64B-10PU-2.7(2)
AT24C64B-10PU-1.8(2)
AT24C64BN-10SU-2.7(2)
AT24C64BN-10SU-1.8(2)
AT24C64B-10TU-2.7(2)
AT24C64B-10TU-1.8(2)
8P3
8P3
8S1
8S1
8A2
8A2
Lead-free/Halogen-free
Industrial Temperature
(-40°C to 85°C)
AT24C64B-W2.7-11(3)
AT24C64B-W1.8-11(3)
Die Sale
Die Sale
Industrial Temperature
(-40°C to 85°C)
Notes: 1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables.
2. “U” designates Green Package & RoHS compliant.
3. Available in waffle pack and wafer form; order as SL719 for wafer form. Bumped die available upon request. Please contact
Serial EEPROM Marketing.
Package Type
8P3
8S1
8A2
8-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150” Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8-lead, 4.4 mm Body, Plastic, Thin Shrink Small Outline Package (TSSOP)
Options
-2.7
-1.8
Low Voltage (2.7V to 5.5V)
Low Voltage (1.8V to 5.5V)
13
3350D–SEEPR–05/05
AT24C64B
Packaging Information
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
MIN
MAX
NOM
NOTE
SYMBOL
D1
A2 A
A
0.210
0.195
0.022
0.070
0.045
0.014
0.400
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
4 PLCS
0.310
0.250
0.325
0.280
b
E1
e
0.100 BSC
0.300 BSC
0.130
Side View
eA
L
4
2
0.115
0.150
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
B
R
14
3350D–SEEPR–05/05
AT24C64B
8S1 – JEDEC SOIC
C
1
E
E1
L
N
Ø
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.35
0.10
MAX
1.75
0.25
NOM
NOTE
SYMBOL
A1
A
–
–
A1
b
C
D
E1
E
e
0.31
0.17
4.80
3.81
5.79
–
0.51
0.25
5.05
3.99
6.20
–
–
D
–
–
SIDE VIEW
1.27 BSC
L
0.40
0˚
–
–
1.27
8˚
θ
Note:
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
3/17/05
TITLE
DRAWING NO.
8S1
REV.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
C
Small Outline (JEDEC SOIC)
R
15
3350D–SEEPR–05/05
AT24C64B
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
3.00
NOTE
SYMBOL
D
2.90
3.10
2, 5
A
b
E
6.40 BSC
4.40
E1
A
4.30
–
4.50
1.20
1.05
0.30
3, 5
4
–
A2
b
0.80
0.19
1.00
e
A2
–
D
e
0.65 BSC
0.60
L
0.45
0.75
Side View
L1
1.00 REF
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02
DRAWING NO.
TITLE
REV.
2325 Orchard Parkway
San Jose, CA 95131
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
B
8A2
R
16
3350D–SEEPR–05/05
Atmel Corporation
Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Memory
RF/Automotive
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Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
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San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
Regional Headquarters
Microcontrollers
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San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
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Tel: 1(719) 576-3300
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Tel: 1(719) 576-3300
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Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Fax: 1(719) 540-1759
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Tel: (44) 1355-803-000
Fax: (44) 1355-242-743
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3350D–SEEPR–05/05
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