AT25640AN-10SA-5.0C [ATMEL]
EEPROM, 8KX8, Serial, CMOS, PDSO8, 0.150 INCH, PLASTIC, MS-012AA, SOIC-8;
| 型号： | AT25640AN-10SA-5.0C |
| 厂家： | 
ATMEL |
| 描述： | EEPROM, 8KX8, Serial, CMOS, PDSO8, 0.150 INCH, PLASTIC, MS-012AA, SOIC-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
| 文件： | 总19页 (文件大小：401K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Serial Peripheral Interface (SPI) Compatible
• Supports SPI Modes 0 (0,0) and 3 (1,1)
– Data Sheet Describes Mode 0 Operation
• Medium-voltage and Standard-voltage Operation
– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
• 5.0 MHz Clock Rate (5V)
• 32-byte Page Mode
• Block Write Protection
– Protect 1/4, 1/2, or Entire Array
• Write Protect (WP) Pin and Write Disable Instructions for both Hardware and Software
Data Protection
• Self-timed Write Cycle (2 ms [5V] typical)
• High Reliability
SPI Serial
Automotive
EEPROMs
– Endurance: One Million Write Cycles
– Data Retention: 100 Years
8K (1024 x 8)
16K (2048 x 8)
32K (4096 x 8)
64K (8192 x 8)
• 8-lead PDIP and 8-lead JEDEC SOIC Packages
Description
The AT25080A/160A/320A/640A provides 8192/16384/32768/65536 bits of serial
electrically-erasable programmable read-only memory (EEPROM) organized as
1024/2048/4096/8192 words of 8 bits each. The device is optimized for use in many
automotive applications where low-power and low-voltage operation are essential.
The AT25080A/160A/320A/640A is available in space saving 8-lead PDIP and 8-lead
JEDEC SOIC packages.
AT25080A
AT25160A
AT25320A
AT25640A
The AT25080A/160A/320A/640A is enabled through the Chip Select pin (CS) and
accessed via a three-wire interface consisting of Serial Data Input (SI), Serial Data
Output (SO), and Serial Clock (SCK). All programming cycles are completely self-
timed, and no separate erase cycle is required before write.
Block write protection is enabled by programming the status register with one of four
blocks of write protection. Separate program enable and program disable instructions
are provided for additional data protection. Hardware data protection is provided via
the WP pin to protect against inadvertent write attempts to the status register. The
HOLD pin may be used to suspend any serial communication without resetting the
serial sequence.
8-lead PDIP
Table 1. Pin Configuration
Pin Name
CS
Function
CS
SO
1
8
7
6
5
VCC
HOLD
SCK
SI
Chip Select
2
3
4
SCK
SI
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
WP
GND
SO
GND
VCC
WP
8-lead SOIC
Power Supply
Write Protect
Suspends Serial Input
No Connect
CS
SO
1
8
7
6
5
VCC
HOLD
SCK
SI
2
3
4
HOLD
NC
WP
GND
DC
Don’t Connect
3401D–SEEPR–1/05
Absolute Maximum Ratings*
Operating Temperature......................................−40°C to +125°C
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature .........................................−65°C to +150°C
Voltage on Any Pin
with Respect to Ground........................................ −1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Figure 1. Block Diagram
2
AT25080A/160A/320A/640A
3401D–SEEPR–1/05
AT25080A/160A/320A/640A
Table 2. Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).
Symbol
COUT
CIN
Test Conditions
Max
8
Units
pF
Conditions
VOUT = 0V
VIN = 0V
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF
Note:
Table 3. DC Characteristics(1)
Applicable over recommended operating range from: TA = −40°C to +125°C, VCC = +2.7V to +5.5V
1. This parameter is characterized and is not 100% tested.
Symbol
VCC1
VCC2
ICC1
Parameter
Test Condition
Min
2.7
4.5
Typ
Max
5.5
5.5
6.0
3.0
7.0
Units
V
Supply Voltage
Supply Voltage
Supply Current
Supply Current
Supply Current
V
VCC = 5.0V at 5 MHz, SO = Open, Read
VCC = 5.0V at 1 MHz
mA
mA
mA
ICC2
ICC3
VCC = 5.0V at 5 MHz, SO = Open,
Read, Write
ISB1
ISB2
IIL
Standby Current
Standby Current
Input Leakage
VCC = 2.7V, CS = VCC
VCC = 5.0V, CS = VCC
VIN = 0V to VCC
0.2
2.0
10.0(2)
13.0(2)
µA
µA
µA
µA
V
−3.0
−3.0
IOL
Output Leakage
Input Low-voltage
Input High-voltage
Output Low-voltage
Output High-voltage
VIN = 0V to VCC
3.0
(1)
VIL
−0.6
VCC x 0.3
VCC + 0.5
0.4
(1)
VIH
VCC x 0.7
V
VOL1
VOH1
IOL = 3.0 mA
2.7V ≤ VCC ≤ 5.5V
V
IOH = −1.6 mA
VCC − 0.8
V
Note:
1. VIL min and VIH max are reference only and are not tested.
2. Worst case measured at 125°C
3
3401D–SEEPR–1/05
Table 4. AC Characteristics
Applicable over recommended operating range from TA = −40°C to +125°C, VCC = As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol
Parameter
Voltage
Min
Max
Units
fSCK
SCK Clock Frequency
4.5–5.5
2.7–5.5
0
0
5.0
3.0
MHz
tRI
Input Rise Time
Input Fall Time
SCK High Time
4.5–5.5
2.7–5.5
2
2
µs
µs
ns
tFI
4.5–5.5
2.7–5.5
2
2
tWH
4.5–5.5
2.7–5.5
40
133
tWL
tCS
tCSS
tCSH
tSU
tH
SCK Low Time
CS High Time
4.5–5.5
2.7–5.5
40
ns
ns
ns
ns
ns
ns
133
4.5–5.5
2.7–5.5
80
250
CS Setup Time
CS Hold Time
4.5–5.5
2.7–5.5
80
250
4.5–5.5
2.7–5.5
80
250
Data In Setup Time
Data In Hold Time
Hold Setup Time
Hold Hold Time
Output Valid
4.5–5.5
2.7–5.5
5
50
4.5–5.5
2.7–5.5
20
50
tHD
tCD
tV
4.5–5.5
2.7–5.5
40
100
4.5–5.5
2.7 - 5.5
40
ns
ns
200
4.5 - 5.5
2.7–5.5
0
0
40
133
tHO
tLZ
Output Hold Time
4.5–5.5
2.7–5.5
0
0
ns
ns
Hold to Output Low Z
4.5–5.5
2.7–5.5
0
0
40
100
tHZ
Hold to Output High Z
Output Disable Time
4.5–5.5
2.7–5.5
80
ns
ns
100
tDIS
4.5–5.5
2.7–5.5
80
250
tWC
Write Cycle Time
4.5–5.5
2.7–5.5
5
5
ms
Endurance(1)
5.0V, 25°C, Page Mode
1M
Write Cycles
Note:
1. This parameter is characterized and is not 100% tested.
4
AT25080A/160A/320A/640A
3401D–SEEPR–1/05
AT25080A/160A/320A/640A
Serial Interface
Description
MASTER: The device that generates the serial clock.
SLAVE: Because the Serial Clock pin (SCK) is always an input, the
AT25080A/160A/320A/640A always operates as a slave.
TRANSMITTER/RECEIVER: The AT25080A/160A/320A/640A has separate pins designated
for data transmission (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be
received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the
AT25080A/160A/320A/640A, and the serial output pin (SO) will remain in a high impedance
state until the falling edge of CS is detected again. This will reinitialize the serial
communication.
CHIP SELECT: The AT25080A/160A/320A/640A is selected when the CS pin is low. When
the device is not selected, data will not be accepted via the SI pin, and the serial output pin
(SO) will remain in a high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS pin to select the
AT25080A/160A/320A/640A. When the device is selected and a serial sequence is underway,
HOLD can be used to pause the serial communication with the master device without resetting
the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low.
To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK
may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the
high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when
held high. When the WP pin is brought low and WPEN bit is “1”, all write operations to the sta-
tus register are inhibited. WP going low while CS is still low will interrupt a write to the status
register. If the internal write cycle has already been initiated, WP going low will have no effect
on any write operation to the status register. The WP pin function is blocked when the WPEN
bit in the status register is “0”. This will allow the user to install the AT25080A/
160A/320A/640A in a system with the WP pin tied to ground and still be able to write to the
status register. All WP pin functions are enabled when the WPEN bit is set to “1”.
5
3401D–SEEPR–1/05
Figure 2. SPI Serial Interface
AT25080A/160A/320A/640A
6
AT25080A/160A/320A/640A
3401D–SEEPR–1/05
AT25080A/160A/320A/640A
Functional
Description
The AT25080A/160A/320A/640A is designed to interface directly with the synchronous serial
peripheral interface (SPI) of the 6805 and 68HC11 series of microcontrollers.
The AT25080A/160A/320A/640A utilizes an 8-bit instruction register. The list of instructions
and their operation codes are contained in Table 5. All instructions, addresses, and data are
transferred with the MSB first and start with a high-to-low CS transition.
Table 5. Instruction Set for the AT25080A/160A/320A/640A
Instruction Name
WREN
Instruction Format
0000 X110
Operation
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Memory Array
Write Data to Memory Array
WRDI
0000 X100
RDSR
0000 X101
WRSR
0000 X001
READ
0000 X011
WRITE
0000 X010
WRITE ENABLE (WREN): The device will power-up in the write disable state when VCC is
applied. All programming instructions must therefore be preceded by a Write Enable
instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable
instruction disables all programming modes. The WRDI instruction is independent of the sta-
tus of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to
the status register. The READY/BUSY and Write Enable status of the device can be deter-
mined by the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of
protection employed. These bits are set by using the WRSR instruction.
Table 6. Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WPEN
X
X
X
BP1
BP0
WEN
RDY
Table 7. Read Status Register Bit Definition
Bit
Definition
Bit 0 (RDY)
Bit 0 = 0 (RDY) indicates the device is ready. Bit 0 = 1 indicates the write cycle is in
progress.
Bit 1 (WEN)
Bit 1= 0 indicates the device is not write-enabled. Bit 1 = 1 indicates the device is
write-enabled.
Bit 2 (BP0)
Bit 3 (BP1)
See Table 8 on page 8.
See Table 8 on page 8.
Bits 4–6 are “0”s when device is not in an internal write cycle.
Bit 7 (WPEN) See Table 9 on page 8.
Bits 0–7 are “1”s during an internal write cycle.
7
3401D–SEEPR–1/05
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of
four levels of protection. The AT25080A/160A/320A/640A is divided into four array segments.
One-quarter, one-half, or all of the memory segments can be protected. Any of the data within
any selected segment will therefore be read-only. The block write protection levels and corre-
sponding status register control bits are shown in Table 8.
The three bits BP0, BP1, and WPEN are nonvolatile cells that have the same properties and
functions as the regular memory cells (e.g., WREN, tWC, RDSR).
Table 8. Block Write Protect Bits
Status
Register Bits
Array Addresses Protected
Level
0
BP1
BP0
AT25080A
AT25160A
AT25320A
AT25640A
0
0
None
None
None
None
1(1/4)
0300
−03FF
0600
−07FF
0C00
−0FFF
1800
−1FFF
0
1
1
1
0
1
2(1/2)
3(All)
0200
−03FF
0400
−07FF
0800
−0FFF
1000
−1FFF
0000
−03FF
0000
−07FF
0000
−0FFF
0000
−1FFF
The WRSR instruction also allows the user to enable or disable the write protect (WP) pin
through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled
when the WP pin is low and the WPEN bit is “1”. Hardware write protection is disabled when
either the WP pin is high or the WPEN bit is “0”. When the device is hardware write-protected,
writes to the status register, including the block protect bits and the WPEN bit, and the block-
protected sections in the memory array are disabled. Writes are only allowed to sections of the
memory that are not block-protected.
NOTE: When the WPEN bit is hardware write-protected, it cannot be changed back to “0” as
long as the WP pin is held low.
Table 9. WPEN Operation
Protected
Blocks
Unprotected
Blocks
Status
Register
WPEN
WP
X
WEN
0
0
1
1
X
X
0
1
0
1
0
1
Protected
Protected
Protected
Protected
Protected
Protected
Protected
Writable
Protected
Writable
Protected
Writable
Protected
Writable
X
Low
Low
High
High
Protected
Protected
Protected
Writable
8
AT25080A/160A/320A/640A
3401D–SEEPR–1/05
AT25080A/160A/320A/640A
READ SEQUENCE (READ): Reading the AT25080A/160A/320A/640A via the serial output
(SO) pin requires the following sequence. After the CS line is pulled low to select a device, the
READ op-code is transmitted via the SI line followed by the byte address to be read (A15–A0;
see Table 10). Upon completion, any data on the SI line will be ignored. The data (D7–D0) at
the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS
line should be driven high after the data comes out. The read sequence can be continued
since the byte address is automatically incremented and data will continue to be shifted out.
When the highest address is reached, the address counter will roll over to the lowest address,
allowing the entire memory to be read in one continuous read cycle.
WRITE SEQUENCE (WRITE): In order to program the AT25080A/160A/320A/640A, two sep-
arate instructions must be executed. First, the device must be write-enabled via the WREN
instruction. Then a write (WRITE) instruction may be executed. Also, the address of the mem-
ory location(s) to be programmed must be outside the protected address field location
selected by the block write protection level. During an internal write cycle, all commands will
be ignored except the RDSR instruction.
A write instruction requires the following sequence. After the CS line is pulled low to select the
device, the WRITE op-code is transmitted via the SI line followed by the byte address (A15–
A0) and the data (D7–D0) to be programmed (see Table 10). Programming will start after the
CS pin is brought high. The low-to-high transition of the CS pin must occur during the SCK
low-time immediately after clocking in the D0 (LSB) data bit.
The READY/BUSY status of the device can be determined by initiating a read status register
(RDSR) instruction. If Bit 0 = 1, the write cycle is still in progress. If Bit 0 = 0, the write cycle
has ended. Only the RDSR instruction is enabled during the write programming cycle.
The AT25080A/160A/320A/640A is capable of a 32-byte page write operation. After each byte
of data is received, the five low-order address bits are internally incremented by one; the high-
order bits of the address will remain constant. If more than 32 bytes of data are transmitted,
the address counter will roll over and the previously written data will be overwritten. The
AT25080A/160A/320A/640A is automatically returned to the write disable state at the comple-
tion of a write cycle.
NOTE: If the device is not write-enabled (WREN), the device will ignore the write instruction
and will return to the standby state when CS is brought high. A new CS falling edge is required
to reinitiate the serial communication.
Table 10. Address Key
Address
AT25080A
AT25160A
AT25320A
AT25640A
AN
A9–A0
A10–A0
A11–A0
A12–A0
Don’t
Care Bits
A15–A10
A15–A11
A15–A12
A15–A13
9
3401D–SEEPR–1/05
Timing Diagrams
Figure 3. Synchronous Data Timing (for Mode 0)
tCS
VIH
CS
VIL
tCSH
tCSS
VIH
tWH
tWL
SCK
VIL
tSU
VIH
tH
SI
VALID IN
VIL
tHO
tDIS
tV
VOH
VOL
HI-Z
HI-Z
SO
Figure 4. WREN Timing
Figure 5. WRDI Timing
10
AT25080A/160A/320A/640A
3401D–SEEPR–1/05
AT25080A/160A/320A/640A
Figure 6. RDSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
SI
INSTRUCTION
DATA OUT
HIGH IMPEDANCE
7
6
5
4
3
2
1
0
SO
MSB
Figure 7. WRSR Timing
CS
0
1
2
3
4
5
6
7
8
9
6
10
11
12
13
14
15
SCK
DATA IN
INSTRUCTION
SI
7
5
4
3
2
1
0
HIGH IMPEDANCE
SO
11
3401D–SEEPR–1/05
Figure 8. READ Timing
CS
0
1
2
3
4
5
6
7
8
9
10 11 20 21 22 23 24 25 26 27 28 29 30 31
SCK
SI
BYTE ADDRESS
...
INSTRUCTION
15 14 13
3
2
1
0
DATA OUT
HIGH IMPEDANCE
7
6
5
4
3
2
1
0
SO
MSB
Figure 9. WRITE Timing
CS
0
1
2
3
4
5
6
7
8
9 10 11 20 21 22 23 24 25 26 27 28 29 30 31
SCK
BYTE ADDRESS
DATA IN
...
INSTRUCTION
15 14 13
3
2
1
0
SI
7
6
5
4
3
2
1
0
HIGH IMPEDANCE
SO
Figure 10. HOLD Timing
CS
tCD
tCD
SCK
tHD
tHD
HOLD
tHZ
SO
tLZ
12
AT25080A/160A/320A/640A
3401D–SEEPR–1/05
AT25080A/160A/320A/640A
AT25080A Ordering Information
Ordering Code
Package
Operation Range
AT25080A-10PA-5.0C
AT25080AN-10SA-5.0C
8P3
8S1
Automotive
(−40°C to 125°C)
AT25080A-10PA-2.7C
AT25080AN-10SA-2.7C
8P3
8S1
Automotive
(−40°C to 125°C)
Package Type
8P3
8S1
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
Options
−5.0
−2.7
Standard Device (4.5V to 5.5V)
Low Voltage (2.7V to 5.5V)
13
3401D–SEEPR–1/05
AT25160A Ordering Information
Ordering Code
Package
Operation Range
AT25160A-10PA-5.0C
AT25160AN-10SA-5.0C
8P3
8S1
Automotive
(−40°C to 125°C)
AT25160A-10PA-2.7C
AT25160AN-10SA-2.7C
8P3
8S1
Automotive
(−40°C to 125°C)
Package Type
8P3
8S1
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
Options
−5.0
−2.7
Standard Device (4.5V to 5.5V)
Low Voltage (2.7V to 5.5V)
14
AT25080A/160A/320A/640A
3401D–SEEPR–1/05
AT25080A/160A/320A/640A
AT25320A Ordering Information
Ordering Code
Package
Operation Range
AT25320A-10PA-5.0C
AT25320AN-10SA-5.0C
8P3
8S1
Automotive
(−40°C to 125°C)
AT25320A-10PA-2.7C
AT25320AN-10SA-2.7C
8P3
8S1
Automotive
(−40°C to 125°C)
Package Type
8P3
8S1
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
Options
−5.0
−2.7
Standard Device (4.5V to 5.5V)
Low Voltage (2.7V to 5.5V)
15
3401D–SEEPR–1/05
AT25640A Ordering Information
Ordering Code
Package
Operation Range
AT25640A-10PA-5.0C
AT25640AN-10SA-5.0C
8P3
8S1
Automotive
(−40°C to 125°C)
AT25640A-10PA-2.7C
AT25640AN-10SA-2.7C
8P3
8S1
Automotive
(−40°C to 125°C)
Package Type
8P3
8S1
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
Options
−5.0
−2.7
Standard Device (4.5V to 5.5V)
Low Voltage (2.7V to 5.5V)
16
AT25080A/160A/320A/640A
3401D–SEEPR–1/05
AT25080A/160A/320A/640A
Packaging Information
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
MIN
–
MAX
0.210
0.195
0.022
0.070
0.045
0.014
0.400
–
NOM
–
NOTE
SYMBOL
D1
A2 A
A
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
–
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
4 PLCS
0.310
0.250
0.100 BSC
0.300 BSC
0.130
0.325
0.280
b
E1
e
Side View
eA
L
4
2
0.115
0.150
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
B
R
17
3401D–SEEPR–1/05
8S1 – JEDEC SOIC
C
1
E
E1
L
N
∅
Top View
End View
e
B
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.35
0.10
MAX
1.75
0.25
NOM
NOTE
SYMBOL
A1
A
–
–
A1
b
0.31
0.17
4.80
3.81
5.79
–
0.51
0.25
5.00
3.99
6.20
C
D
E1
E
–
–
D
–
–
Side View
e
1.27 BSC
L
0.40
0°
–
–
1.27
∅
8°
Note:
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03
REV.
TITLE
DRAWING NO.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
8S1
B
R
Small Outline (JEDEC SOIC)
18
AT25080A/160A/320A/640A
3401D–SEEPR–1/05
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3401D–SEEPR–1/05
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