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AT28C010E-20PI [ATMEL]

1 Megabit 128K x 8 Paged CMOS E2PROM; 1兆位128K ×8分页CMOS E2PROM
AT28C010E-20PI
型号： AT28C010E-20PI
厂家： ATMEL    ATMEL
描述：

1 Megabit 128K x 8 Paged CMOS E2PROM
1兆位128K ×8分页CMOS E2PROM

可编程只读存储器
文件： 总11页 (文件大小：574K)
中文：  中文翻译
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AT28C010 Com/Ind  
Features  
Fast Read Access Time - 120 ns  
Automatic Page Write Operation  
•
•
Internal Address and Data Latches for 128-Bytes  
Internal Control Timer  
Fast Write Cycle Time  
•
Page Write Cycle Time - 10 ms Maximum  
1 to 128-Byte Page Write Operation  
Low Power Dissipation  
•
40 mA Active Current  
1 Megabit  
(128K x 8)  
Paged  
200 µA CMOS Standby Current  
Hardware and Software Data Protection  
DATA Polling for End of Write Detection  
•
•
•
High Reliability CMOS Technology  
Endurance: 104 or 105 Cycles  
Data Retention: 10 Years  
Single 5V ± 10% Supply  
CMOS and TTL Compatible Inputs and Outputs  
JEDEC Approved Byte-Wide Pinout  
Commercial and Industrial Temperature Ranges  
•
CMOS  
•
E2PROM  
•
•
Description  
The AT28C010 is a high-performance Electrically Erasable and Programmable Read  
Only Memory. Its 1 megabit of memory is organized as 131,072 words by 8 bits.  
Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers  
access times to 120 ns with power dissipation of just 220 mW. When the device is  
deselected, the CMOS standby current is less than 200 µA.  
Commercial  
and  
Industrial  
(continued)  
Pin Configurations  
TSOP  
Top View  
Pin Name  
A0 - A16  
CE  
Function  
Addresses  
AT28C010 Com/Ind  
Chip Enable  
Output Enable  
Write Enable  
OE  
WE  
Data  
Inputs/Outputs  
I/O0 - I/O7  
NC  
DC  
No Connect  
Don’t Connect  
PLCC  
PDIP  
Top View  
Top View  
Note: PLCC package pin 1  
is a DON’T CONNECT.  
0353C  
2-231  
Description (Continued)  
The AT28C010 is accessed like a Static RAM for the read  
or write cycle without the need for external components.  
The device contains a 128-byte page register to allow writ-  
ing of up to 128-bytes simultaneously. During a write cy-  
cle, the address and 1 to 128-bytes of data are internally  
latched, freeing the address and data bus for other opera-  
tions. Following the initiation of a write cycle, the device  
will automatically write the latched data using an internal  
control timer. The end of a write cycle can be detected by  
DATA POLLING of I/O7. Once the end of a write cycle has  
been detected a new access for a read or write can begin.  
Atmel’s 28C010 has additional features to ensure high  
quality and manufacturability. The device utilizes internal  
error correction for extended endurance and improved  
data retention characteristics. An optional software data  
protection mechanism is available to guard against inad-  
vertent writes. The device also includes an extra 128-  
2
bytes of E PROM for device identification or tracking.  
Block Diagram  
Absolute Maximum Ratings*  
*NOTICE: Stresses beyond those listed under “Absolute Maxi-  
mum Ratings” may cause permanent damage to the device.  
This is a stress rating only and functional operation of the  
device at these or any other conditions beyond those indi-  
cated in the operational sections of this specification is not  
implied. Exposure to absolute maximum rating conditions  
for extended periods may affect device reliability.  
Temperature Under Bias................. -55°C to +125°C  
Storage Temperature...................... -65°C to +150°C  
All Input Voltages  
(including NC Pins)  
with Respect to Ground ................... -0.6V to +6.25V  
All Output Voltages  
with Respect to Ground .............-0.6V to V + 0.6V  
CC  
Voltage on OE and A9  
with Respect to Ground ................... -0.6V to +13.5V  
2-232 AT28C010 Com/Ind  
AT28C010 Com/Ind  
Device Operation  
READ: The AT28C010 is accessed like a Static RAM.  
When CE and OE are low and WE is high, the data stored  
at the memory location determined by the address pins is  
asserted on the outputs. The outputs are put in the high  
impedance state when either CE or OE is high. This dual-  
line control gives designers flexibility in preventing bus  
contention in their system.  
DATA PROTECTION: If precautions are not taken, inad-  
vertent writes may occur during transitions of the host sys-  
tem power supply. Atmel has incorporated both hardware  
and software features that will protect the memory against  
inadvertent writes.  
HARDWARE PROTECTION: Hardware features protect  
against inadvertent writes to the AT28C010 in the follow-  
BYTE WRITE: A low pulse on the WE or CE input with CE  
or WE low (respectively) and OE high initiates a write cy-  
cle. The address is latched on the falling edge of CE or  
WE, whichever occurs last. The data is latched by the first  
rising edge of CE or WE. Once a byte write has been  
started it will automatically time itself to completion. Once  
a programming operation has been initiated and for the  
ing ways: (a) V sense - if V is below 3.8V (typical) the  
CC  
CC  
write function is inhibited; (b) V power-on delay - once  
CC  
V
has reached 3.8V the device will automatically time  
CC  
out 5 ms (typical) before allowing a write: (c) write inhibit -  
holding any one of OE low, CE high or WE high inhibits  
write cycles; (d) noise filter - pulses of less than 15 ns (typi-  
cal) on the WE or CE inputs will not initiate a write cycle.  
duration of t , a read operation will effectively be a poll-  
ing operation.  
WC  
SOFTWARE DATA PROTECTION: A software controlled  
data protection feature has been implemented on the  
AT28C010. When enabled, the software data protection  
(SDP), will prevent inadvertent writes. The SDP feature  
may be enabled or disabled by the user; the AT28C010 is  
shipped from Atmel with SDP disabled.  
PAGE WRITE: The page write operation of the AT28C010  
allows 1 to 128-bytes of data to be written into the device  
during a single internal programming period. A page write  
operation is initiated in the same manner as a byte write;  
the first byte written can then be followed by 1 to 127 ad-  
ditional bytes. Each successive byte must be written within  
SDP is enabled by the host system issuing a series of  
three write commands; three specific bytes of data are  
written to three specific addresses (refer to Software Data  
Protection Algorithm). After writing the 3-byte command  
150 µs (t  
) of the previous byte. If the t  
limit is ex-  
BLC  
BLC  
ceeded the AT28C010 will cease accepting data and com-  
mence the internal programming operation. All bytes dur-  
ing a page write operation must reside on the same page  
as defined by the state of the A7 - A16 inputs. For each  
WE high to low transition during the page write operation,  
A7 - A16 must be the same.  
sequence and after t  
the entire AT28C010 will be pro-  
WC  
tected against inadvertent write operations. It should be  
noted, that once protected the host may still perform a  
byte or page write to the AT28C010. This is done by pre-  
ceding the data to be written by the same 3-byte command  
sequence used to enable SDP.  
The A0 to A6 inputs are used to specify which bytes within  
the page are to be written. The bytes may be loaded in any  
order and may be altered within the same load period.  
Only bytes which are specified for writing will be written;  
unnecessary cycling of other bytes within the page does  
not occur.  
Once set, SDP will remain active unless the disable com-  
mand sequence is issued. Power transitions do not dis-  
able SDP and SDP will protect the AT28C010 during  
power-up and power-down conditions. All command se-  
quences must conform to the page write timing specifica-  
tions. The data in the enable and disable command se-  
quences is not written to the device and the memory ad-  
dresses used in the sequence may be written with data in  
either a byte or page write operation.  
DATA POLLING: The AT28C010 features DATA Polling  
to indicate the end of a write cycle. During a byte or page  
write cycle an attempted read of the last byte written will  
result in the complement of the written data to be pre-  
sented on I/O7. Once the write cycle has been completed,  
true data is valid on all outputs, and the next write cycle  
may begin. DATA Polling may begin at anytime during the  
write cycle.  
After setting SDP, any attempt to write to the device with-  
out the 3-byte command sequence will start the internal  
write timers. No data will be written to the device; however,  
for the duration of t , read operations will effectively be  
WC  
TOGGLE BIT: In addition to DATA Polling the AT28C010  
provides another method for determining the end of a write  
cycle. During the write operation, successive attempts to  
read data from the device will result in I/O6 toggling be-  
tween one and zero. Once the write has completed, I/O6  
will stop toggling and valid data will be read. Reading the  
toggle bit may begin at any time during the write cycle.  
polling operations.  
(continued)  
2-233  
Device Operation (Continued)  
DEVICE IDENTIFICATION: An extra 128-bytes of  
E PROM memory are available to the user for device  
identification. By raising A9 to 12V ± 0.5V and using ad-  
dress locations 1FF80H to 1FFFFH the bytes may be writ-  
ten to or read from in the same manner as the regular  
memory array.  
OPTIONAL CHIP ERASE MODE: The entire device can  
be erased using a 6-byte software code. Please see Soft-  
ware Chip Erase application note for details.  
2
DC and AC Operating Range  
AT28C010-12  
AT28C010-15  
0°C - 70°C  
-40°C - 85°C  
5V ± 10%  
AT28C010-20  
0°C - 70°C  
-40°C - 85°C  
5V ± 10%  
Com.  
Ind.  
0°C - 70°C  
-40°C - 85°C  
5V ± 10%  
Operating  
Temperature (Case)  
V
Power Supply  
CC  
Operating Modes  
Mode  
CE  
OE  
WE  
I/O  
Read  
V
V
V
V
D
D
IL  
IL  
IH  
OUT  
IN  
(2)  
Write  
V
V
IL  
IH  
IL  
(1)  
Standby/Write Inhibit  
Write Inhibit  
V
X
X
High Z  
IH  
X
X
V
IH  
Write Inhibit  
X
X
V
X
IL  
Output Disable  
V
X
High Z  
IH  
Notes: 1. X can be VIL or VIH.  
2. Refer to AC Programming Waveforms.  
DC Characteristics  
Symbol  
Parameter  
Condition  
Min  
Max  
Units  
µA  
µA  
µA  
mA  
mA  
V
I
I
I
I
I
Input Load Current  
Output Leakage Current  
V
V
= 0V to V + 1V  
10  
10  
200  
3
LI  
IN  
CC  
= 0V to V  
CC  
LO  
I/O  
V
V
V
Standby Current CMOS  
Standby Current TTL  
Active Current  
CE = V - 0.3V to V + 1V  
CC CC  
SB1  
SB2  
CC  
CC  
CC  
CC  
CE = 2.0V to V + 1V  
CC  
f = 5 MHz; I  
= 0 mA  
40  
0.8  
OUT  
V
V
V
V
V
Input Low Voltage  
IL  
Input High Voltage  
2.0  
V
IH  
Output Low Voltage  
Output High Voltage  
Output High Voltage CMOS  
I
I
I
= 2.1 mA  
.45  
V
OL  
OH1  
OH2  
OL  
OH  
OH  
= -400 µA  
= -100 µA; V = 4.5V  
2.4  
4.2  
V
V
CC  
2-234 AT28C010 Com/Ind  
AT28C010 Com/Ind  
AC Read Characteristics  
AT28C010-12  
AT28C010-15  
AT28C010-20  
Min  
Max  
120  
120  
50  
Min  
Max  
150  
150  
55  
Min  
Max  
200  
200  
55  
Symbol  
Parameter  
Units  
ns  
t
t
t
t
Address to Output Delay  
CE to Output Delay  
OE to Output Delay  
CE or OE to Output Float  
ACC  
(1)  
ns  
CE  
OE  
DF  
(2)  
0
0
0
0
0
0
ns  
(3, 4)  
50  
55  
55  
ns  
Output Hold from OE, CE or  
Address, whichever  
occurred first  
t
0
0
0
ns  
OH  
AC Read Waveforms (1, 2, 3, 4)  
Notes: 1. CE may be delayed up to tACC - tCE after the address  
transition without impact on tACC  
3. tDF is specified from OE or CE whichever occurs first  
(CL = 5 pF).  
.
2. OE may be delayed up to tCE - tOE after the falling  
edge of CE without impact on tCE or by tACC - tOE  
4. This parameter is characterized and is not 100% tested.  
after an address change without impact on tACC  
.
Output Test Load  
Input Test Waveforms and  
Measurement Level  
t , t < 5 ns  
R
F
Pin Capacitance (f = 1 MHz, T = 25°C) (1)  
Typ  
Max  
10  
Units  
pF  
Conditions  
C
C
4
8
V
V
= 0V  
IN  
IN  
12  
pF  
= 0V  
OUT  
OUT  
Note: 1. This parameter is characterized and is not 100% tested.  
2-235  
AC Write Characteristics  
Symbol  
Parameter  
Min  
0
Max  
Units  
ns  
t
t
t
t
t
t
t
, t  
Address, OE Set-up Time  
Address Hold Time  
AS OES  
50  
0
ns  
AH  
CS  
CH  
WP  
DS  
Chip Select Set-up Time  
Chip Select Hold Time  
Write Pulse Width (WE or CE)  
Data Set-up Time  
ns  
0
ns  
100  
50  
0
ns  
ns  
, t  
Data, OE Hold Time  
ns  
DH OEH  
AC Write Waveforms  
WE Controlled  
CE Controlled  
2-236 AT28C010 Com/Ind  
AT28C010 Com/Ind  
Page Mode Characteristics  
Symbol  
Parameter  
Min  
Max  
Units  
ms  
ns  
t
t
t
t
t
t
t
t
Write Cycle Time  
Address Set-up Time  
Address Hold Time  
Data Set-up Time  
Data Hold Time  
10  
WC  
0
50  
50  
0
AS  
ns  
AH  
ns  
DS  
ns  
DH  
Write Pulse Width  
Byte Load Cycle Time  
Write Pulse Width High  
100  
ns  
WP  
BLC  
WPH  
150  
µs  
50  
ns  
Page Mode Write Waveforms (1, 2)  
Notes: 1. A7 through A16 must specify the page address during each high to low transition of WE (or CE).  
2. OE must be high only when WE and CE are both low.  
Chip Erase Waveforms  
tS = 5 µsec (min.)  
tW = tH = 10 msec (min.)  
VH = 12.0V ± 0.5V  
2-237  
Software Data  
Software Data  
Protection Enable Algorithm (1)  
Protection Disable Algorithm (1)  
LOAD DATA AA  
LOAD DATA AA  
TO  
ADDRESS 5555  
TO  
ADDRESS 5555  
LOAD DATA 55  
TO  
ADDRESS 2AAA  
LOAD DATA 55  
TO  
ADDRESS 2AAA  
LOAD DATA 80  
TO  
ADDRESS 5555  
LOAD DATA A0  
TO  
ADDRESS 5555  
(2)  
WRITES ENABLED  
LOAD DATA AA  
TO  
ADDRESS 5555  
LOAD DATA XX  
TO  
ANY ADDRESS (4)  
LOAD DATA 55  
TO  
ADDRESS 2AAA  
LOAD LAST BYTE  
TO  
LAST ADDRESS  
ENTER DATA  
PROTECT STATE  
LOAD DATA 20  
TO  
Notes:  
ADDRESS 5555  
EXIT DATA  
1. Data Format: I/O7 - I/O0 (Hex);  
Address Format: A14 - A0 (Hex).  
2. Write Protect state will be activated at end of write even if no  
other data is loaded.  
(3)  
PROTECT STATE  
LOAD DATA XX  
TO  
ANY ADDRESS (4)  
3. Write Protect state will be deactivated at end of write period  
even if no other data is loaded.  
4. 1 to 128-bytes of data are loaded.  
LOAD LAST BYTE  
TO  
LAST ADDRESS  
Software Protected Program Cycle Waveform (1, 2, 3)  
Notes: 1. A0 - A14 must conform to the addressing sequence  
for the first 3-bytes as shown above.  
3. OE must be high only when WE and CE are both low.  
2. After the command sequence has been issued and a  
page write operation follows, the page address inputs  
(A7 - A16) must be the same for each high to low  
transition of WE (or CE).  
2-238 AT28C010 Com/Ind  
AT28C010 Com/Ind  
Data Polling Characteristics(1)  
Symbol  
Parameter  
Min  
10  
Typ  
Max  
Units  
ns  
t
t
t
t
Data Hold Time  
OE Hold Time  
OE to Output Delay  
DH  
10  
ns  
OEH  
OE  
(2)  
ns  
Write Recovery Time  
0
ns  
WR  
Notes: 1. These parameters are characterized and not 100% tested.  
2. See AC Read Characteristics.  
Data Polling Waveforms  
Toggle Bit Characteristics (1)  
Symbol  
Parameter  
Min  
10  
Typ  
Max  
Units  
ns  
t
t
t
t
t
Data Hold Time  
OE Hold Time  
OE to Output Delay  
OE High Pulse  
DH  
10  
ns  
OEH  
OE  
(2)  
ns  
150  
0
ns  
OEHP  
WR  
Write Recovery Time  
ns  
Notes: 1. These parameters are characterized and not 100% tested.  
2. See AC Read Characteristics.  
Toggle Bit Waveforms  
3. Any address location may be used but the address  
should not vary.  
Notes: 1. Toggling either OE or CE or both OE and CE will  
operate toggle bit.  
2. Beginning and ending state of I/O6 will vary.  
2-239  
Ordering Information (1)  
t
I
(mA)  
ACC  
CC  
Ordering Code  
Package  
Operation Range  
Active Standby  
(ns)  
120  
40  
40  
40  
40  
40  
40  
40  
0.2  
0.2  
0.2  
0.2  
0.2  
0.2  
0.2  
AT28C010(E)-12JC  
AT28C010(E)-12PC  
AT28C010(E)-12TC  
32J  
32P6  
32T  
Commercial  
(0° to 70°C)  
AT28C010(E)-12JI  
AT28C010(E)-12PI  
AT28C010(E)-12TI  
32J  
32P6  
32T  
Industrial  
(-40° to 85°C)  
150  
200  
AT28C010(E)-15JC  
AT28C010(E)-15PC  
AT28C010(E)-15TC  
32J  
32P6  
32T  
Commercial  
(0° to 70°C)  
AT28C010(E)-15JI  
AT28C010(E)-15PI  
AT28C010(E)-15TI  
32J  
32P6  
32T  
Industrial  
(-40° to 85°C)  
AT28C010(E)-20JC  
AT28C010(E)-20PC  
AT28C010(E)-20TC  
32J  
32P6  
32T  
Commercial  
(0° to 70°C)  
AT28C010(E)-20JI  
AT28C010(E)-20PI  
AT28C010(E)-20TI  
32J  
32P6  
32T  
Industrial  
(-40° to 85°C)  
AT28C010-W  
DIE  
Commercial  
(0° to 70°C)  
Note: 1. See Valid Part Number table below.  
Valid Part Numbers  
The following table lists standard Atmel products that can be ordered.  
Device Numbers  
AT28C010  
Speed  
Package and Temperature Combinations  
JC, JI, PC, PI, TC, TI  
JC, JI, PC, PI, TC, TI  
JC, JI, PC, PI, TC, TI  
JC, JI, PC, PI, TC, TI  
JC, JI, PC, PI, TC, TI  
JC, JI, PC, PI, TC, TI  
W
12  
12  
15  
15  
20  
20  
-
AT28C010E  
AT28C010  
AT28C010E  
AT28C010  
AT28C010E  
AT28C010  
2-240 AT28C010 Com/Ind  
AT28C010 Com/Ind  
Package Type  
32 Lead, Plastic J-Leaded Chip Carrier (PLCC)  
32J  
32P6  
32T  
W
32 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)  
32 Lead, Plastic Thin Small Outline Package (TSOP)  
DIE  
Options  
Blank  
E
Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms  
High Endurance Option: Endurance = 100K Write Cycles  
2-241  

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