AT28C040-20BI [ATMEL]
4-Megabit 512K x 8 Paged E2PROM; 4兆位512K ×8分页E2PROM
| 型号： | AT28C040-20BI |
| 厂家： | 
ATMEL |
| 描述： | 4-Megabit 512K x 8 Paged E2PROM |
| 文件： | 总12页 (文件大小：335K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Read Access Time - 200 ns
• Automatic Page Write Operation
– Internal Address and Data Latches for 256 Bytes
– Internal Control Timer
• Fast Write Cycle Time
– Page Write Cycle Time - 10 ms Maximum
– 1 to 256 Byte Page Write Operation
• Low Power Dissipation
– 80 mA Active Current
• Hardware and Software Data Protection
• DATA Polling for End of Write Detection
• High Reliability CMOS Technology
– Endurance: 10,000 Cycles
– Data Retention: 10 Years
• Single 5V ± 10% Supply
4-Megabit
(512K x 8)
Paged E2PROM
• CMOS and TTL Compatible Inputs and Outputs
• JEDEC Approved Byte-Wide Pinout
AT28C040
Description
The AT28C040 is a high-performance electrically erasable and programmable read
only memory (E2PROM). Its 4 megabits of memory is organized as 524,288 words by
8 bits. Manufactured with Atmel's advanced nonvolatile CMOS technology, the device
offers access times to 200 ns with power dissipation of just 440 mW.
(continued)
Pin Configurations
Pin Name
A0 - A18
CE
Function
Addresses
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
OE
WE
I/O0 - I/O7
NC
AT28C040 4-
Megabit (512K x
8) Paged
E2PROM
SIDE BRAZE,
FLATPACK
Top View
LCC
Top View
Rev. 0542B–04/98
The AT28C040 is accessed like a static RAM for the read
or write cycle without the need for external components.
The device contains a 256-byte page register to allow writ-
ing of up to 256 bytes simultaneously. During a write cycle,
the address and 1 to 256 bytes of data are internally
latched, freeing the address and data bus for other opera-
tions. Following the initiation of a write cycle, the device will
automatically write the latched data using an internal con-
trol timer. The end of a write cycle can be detected by
DATA POLLING of I/O7. Once the end of a write cycle has
been detected, a new access for a read or write can begin.
Atmel's AT28C040 has additional features to ensure high
quality and manufacturability. The device utilizes internal
error correction for extended endurance and improved data
retention characteristics. An optional software data protec-
tion mechanism is available to guard against inadvertent
writes. The device also includes an extra 256 bytes of
E2PROM for device identification or tracking.
Block Diagram
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on OE and A9
with Respect to Ground...................................-0.6V to +13.5V
AT28C040
2
AT28C040
Device Operation
READ: The AT28C040 is accessed like a static RAM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state when either CE or OE is high. This dual-
line control gives designers flexibility in preventing bus con-
tention in their systems.
and software features that will protect the memory against
inadvertent writes.
HARDWARE PROTECTION: Hardware features protect
against inadvertent writes to the AT28C040 in the following
ways: (a) VCC sense - if VCC is below 3.8V (typical) the write
function is inhibited; (b) VCC power-on delay - once VCC has
reached 3.8V the device will automatically time out 5 ms
(typical) before allowing a write: (c) write inhibit - holding
any one of OE low, CE high or WE high inhibits write
cycles; (d) noise filter - pulses of less than 15 ns (typical)
on the WE or CE inputs will not initiate a write cycle.
BYTE WRITE: A low pulse on the WE or CE input with CE
or WE low (respectively) and OE high initiates a write cycle.
The address is latched on the falling edge of CE or WE,
whichever occurs last. The data is latched by the first rising
edge of CE or WE. Once a byte write has been started, it
will automatically time itself to completion. Once a pro-
gramming operation has been initiated and for the duration
of tWC, a read operation will effectively be a polling opera-
tion.
SOFTWARE DATA PROTECTION: A software controlled
data protection feature has been implemented on the
AT28C040. When enabled, the software data protection
(SDP), will prevent inadvertent writes. The SDP feature
may be enabled or disabled by the user; the AT28C040 is
shipped from Atmel with SDP disabled.
PAGE WRITE: The page write operation of the AT28C040
allows 1 to 256 bytes of data to be written into the device
during a single internal programming period. A page write
operation is initiated in the same manner as a byte write;
the first byte written can then be followed by 1 to 255 addi-
tional bytes. Each successive byte must be written within
150 µs (tBLC) of the previous byte. If the tBLC limit is
exceeded, the AT28C040 will cease accepting data and
commence the internal programming operation. All bytes
during a page write operation must reside on the same
page as defined by the state of the A8 - A18 inputs. For
each WE high to low transition during the page write opera-
tion, A8 - A18 must be the same.
SDP is enabled when the host system issues a series of
three write commands; three specific bytes of data are writ-
ten to three specific addresses (refer to Software Data Pro-
tection Algorithm). After writing the 3-byte command
sequence and after tWC, the entire AT28C040 will be pro-
tected against inadvertent write operations. It should be
noted that once protected, the host can still perform a byte
or page write to the AT28C040. To do so, the same 3-byte
command sequence used to enable SDP must precede the
data to be written.
Once set, SDP will remain active unless the disable com-
mand sequence is issued. Power transitions do not disable
SDP, and SDP will protect the AT28C040 during power-up
and power-down conditions. All command sequences must
conform to the page write timing specifications. The data in
the enable and disable command sequences is not written
to the device, and the memory addresses used in the
sequence may be written with data in either a byte or page
write operation.
The A0 to A7 inputs specify which bytes within the page are
to be written. The bytes may be loaded in any order and
may be altered within the same load period. Only bytes
which are specified for writing will be written; unnecessary
cycling of other bytes within the page does not occur.
DATA POLLING: The AT28C040 features DATA Polling to
indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will
result in the complement of the written data to be presented
on I/O7. Once the write cycle has been completed, true
data is valid on all outputs, and the next write cycle may
begin. DATA Polling may begin at anytime during the write
cycle.
After setting SDP, any attempt to write to the device without
the 3-byte command sequence will start the internal write
timers. No data will be written to the device; however, for
the duration of tWC, read operations will effectively be poll-
ing operations.
DEVICE IDENTIFICATION: An extra 256 bytes of
E2PROM memory are available to the user for device iden-
tification. By raising A9 to 12V ± 0.5V and using address
locations 7FF80H to 7FFFFH, the bytes may be written to
or read from in the same manner as the regular memory
array.
TOGGLE BIT: In addition to DATA Polling, the AT28C040
provides another method for determining the end of a write
cycle. During the write operation, successive attempts to
read data from the device will result in I/O6 toggling
between one and zero. Once the write has completed, I/O6
will stop toggling and valid data will be read. Reading the
toggle bit may begin at any time during the write cycle.
OPTIONAL CHIP ERASE MODE: The entire device can
be erased using a 6-byte software erase code. Please see
Software Chip Erase application note for details.
DATA PROTECTION: If precautions are not taken, inad-
vertent writes may occur during transitions of the host sys-
tem power supply. Atmel has incorporated both hardware
3
DC and AC Operating Range
AT28C040-20
Operation
AT28C040-25
Operation
Read
Program
0°C - 70°C
-40°C - 85°C
-40°C - 85°C
5V ± 10%
Read
Program
0°C - 70°C
-40°C - 85°C
-40°C - 85°C
5V ± 10%
Commercial
Operating
0°C - 70°C
-40°C - 85°C
-55°C - 125°C
5V ± 10%
0°C - 70°C
-40°C - 85°C
-55°C - 125°C
5V ± 10%
Temperature
(Case)
Industrial
Extended
VCC Power Supply
Operating Modes
Mode
CE
VIL
VIL
VIH
X
OE
VIL
VIH
X(1)
X
WE
VIH
VIL
X
I/O
DOUT
DIN
Read
Write(2)
Standby/Write Inhibit
Write Inhibit
Write Inhibit
Output Disable
High Z
VIH
X
X
VIL
VIH
X
X
High Z
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
DC Characteristics
Symbol Parameter
Condition
Min
Max
10
10
3
Units
µA
µA
mA
mA
mA
V
ILI
Input Load Current
VIN = 0V to VCC + 1V
VI/O = 0V to VCC
ILO
Output Leakage Current
VCC Standby Current CMOS
VCC Standby Current TTL
VCC Active Current
ISB1
ISB2
ICC
CE = VCC - 0.3V to VCC + 1V
CE = 2.0V to VCC + 1V
f = 5 MHz; IOUT = 0 mA
3
80
0.8
VIL
Input Low Voltage
VIH
VOL
VOH1
VOH2
Input High Voltage
2.0
V
Output Low Voltage
IOL = 2.1 mA
0.45
V
Output High Voltage
Output High Voltage CMOS
IOH = -400 µA
2.4
4.2
V
IOH = -100 µA; VCC = 4.5V
V
AT28C040
4
AT28C040
AC Read Characteristics
AT28C040-20
AT28C040-25
Symbol Parameter
Min
Max
200
200
55
Min
Max
250
250
55
Units
ns
tACC
Address to Output Delay
(1)
tCE
tOE
tDF
CE to Output Delay
ns
(2)
OE to Output Delay
0
0
0
0
0
0
ns
(3)(4)
CE or OE to Output Float
55
55
ns
tOH
Output Hold from OE, CE or Address, whichever occurred first
ns
AC Read Waveforms(1)(2)(3)(4)
Note:
1. CE May be delayed up to tACC - tCE after the address transition wihtout impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC
.
.
3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement Level
Output Test Load
tR, tF < 5 ns
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Typ
4
Max
10
Units
Conditions
VIN = 0V
CIN
pF
pF
COUT
8
12
VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
5
AC Write Characteristics
Symbol Parameter
Min
0
Max
Units
ns
t
AS, tOES
Address, OE Set-up Time
Address Hold Time
tAH
tCS
tCH
tWP
tDS
50
0
ns
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
ns
0
ns
100
50
0
ns
ns
t
DH, tOEH Data, OE Hold Time
ns
AC Write Waveforms
WE Controlled
CE Controlled
AT28C040
6
AT28C040
Page Mode Characteristics
Symbol Parameter
Min
Max
Units
ms
ns
tWC
tAS
Write Cycle Time
10
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
0
50
50
0
tAH
ns
tDS
ns
tDH
ns
tWP
tBLC
tWPH
Write Pulse Width
Byte Load Cycle Time
Write Pulse Width High
100
ns
150
µs
50
ns
Page Mode Write Waveforms(1)(2)
Notes: 1. A8 through A18 must specify the page address during each high to low transition of WE (or CE).
2. OE must be high only when WE and CE are both low.
7
Software Data
Software Data
Protection Enable Algorithm(1)
Protection Disable Algorithm(1)
LOAD DATA AA
TO
LOAD DATA AA
TO
ADDRESS 5555
ADDRESS 5555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS 2AAA
ADDRESS 2AAA
LOAD DATA A0
LOAD DATA 80
TO
ADDRESS 5555
TO
WRITES
ADDRESS 5555
ENABLED(2)
LOAD DATA XX
TO
LOAD DATA AA
TO
ADDRESS 5555
ANY ADDRESS (4)
LOAD LAST BYTE
TO
LOAD DATA 55
TO
ENTER DATA
LAST ADDRESS
PROTECT STATE
ADDRESS 2AAA
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
LOAD DATA 20
Address Format: A14 - A0 (Hex).
TO
EXIT DATA
2. Write Protect state will be activated at end of write
even if no other data is loaded.
ADDRESS 5555
PROTECT STATE(3)
3. Write Protect state will be deactivated at end of write
period even if no other data is loaded.
LOAD DATA XX
TO
4. 1 to 25 bytes of data are loaded.
ANY ADDRESS (4)
LOAD LAST BYTE
TO
LAST ADDRESS
Software Protected Program Cycle Waveform(1)(2)(3)
Notes: 1. A0 - A14 must conform to the addressing sequence for the first 3 bytes as shown above.
2. After the command sequence has been issued and a page write operation follows, the page address inputs (A8 - A18) must
be the same for each high to low transition of WE (or CE).
3. OE must be high only when WE and CE are both low.
AT28C040
8
AT28C040
Data Polling Characteristics(1)
Symbol Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
OE Hold Time
10
ns
OE to Output Delay(2)
Write Recovery Time
ns
tWR
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
Data Polling Waveforms
Toggle Bit Characteristics(1)
Symbol Parameter
Min
Typ
Max
Units
ns
tDH
Data Hold Time
10
10
tOEH
tOE
tOEHP
tWR
OE Hold Time
ns
OE to Output Delay(2)
ns
OE High Pulse
150
0
ns
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
Toggle Bit Waveforms(1)(2)(3)
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
9
Ordering Information(1)
I
CC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
200
80
3
AT28C040-20BC
AT28C040-20FC
AT28C040-20LC
32B
32F
44L
Commercial
(0° to 70°C)
80
80
80
80
80
3
3
3
3
3
AT28C040-20BI
AT28C040-20FI
AT28C040-20LI
32B
32F
44L
Industrial
(-40° to 85°C)
AT28C040-20BI SL703
AT28C040-20FI SL703
AT28C040-20LI SL703
32B
32F
44L
Extended
(See DC and AC Operating
Range Table)
250
AT28C040-25BC
AT28C040-25FC
AT28C040-25LC
32B
32F
44L
Commercial
(0° to 70°C)
AT28C040-25BI
AT28C040-25FI
AT28C040-25LI
32B
32F
44L
Industrial
(-40° to 85°C)
AT28C040-25BI SL703
AT28C040-25FI SL703
AT28C040-25LI SL703
32B
32F
44L
Extended
(See DC and AC Operating
Range Table)
Note:
1. See Valid Part Numbers on next page.
AT28C040
10
AT28C040
Valid Part Numbers
The following table lists standard Atmel products that can be ordered.
Device Numbers
AT28C040
Speed
20
Package and Temperature Combinations
BC, BI, FC, FI, LC, LI, BI SL703, FI SL703, LI SL703
BC, BI, FC, FI, LC, LI, BI SL703, FI SL703, LI SL703
AT28C040
25
Package Type
32B
32F
44L
32-Lead, 0.600" Wide, Ceramic Side Braze Dual Inline (Side Braze)
32-Lead, Non-Windowed, Ceramic Bottom-Brazed Flat Package (Flatpack)
44-Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC)
Options
Blank
Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms
11
Packaging Information
32B, 32-Lead, 0.600” Wide, Ceramic Side Braze
Dual Inline (Side Braze)
32F, 32-Lead, Non-Windowed, Ceramic Bottom-
Brazed Flat Package (Flatpack)
Dimensions in Inches and (Millimeters)
Dimension in Inches and (Millimeters)
JEDEC OUTLINE MO-115
PIN #1 ID
.370(9.40)
.270(6.86)
.019(.482)
.015(.381)
.829(21.1)
.811(20.6)
.050(1.27) BSC
.045(1.14) MAX
.488(12.4)
.472(12.0)
.120(3.05)
.098(2.49)
.006(.152)
.004(.101)
.408(10.4)
.355(9.02)
.045(1.14)
.026(.660)
.072(1.82)
.030(0.76)
44L, 44-Pad, Non-Windowed, Ceramic Leadless
Chip Carrier (LCC)
Dimensions in Inches and (Millimeters)*
MIL-STD-1835 C-5
*Ceramic lid standard unless specified.
AT28C040
12
相关型号：
AT28C040-20BJ
EEPROM, 512KX8, 200ns, Parallel, CMOS, CDIP32, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-32
ATMEL
AT28C040-20BJSL703
EEPROM, 512KX8, 200ns, Parallel, CMOS, CDIP32, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-32
ATMEL
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