AT28HC256F-12UM/883 [ATMEL]
256 32K x 8 High Speed Parallel EEPROMs; 256 32K ×8高速并行的EEPROM
| 型号： | AT28HC256F-12UM/883 |
| 厂家： | 
ATMEL |
| 描述： | 256 32K x 8 High Speed Parallel EEPROMs |
| 文件： | 总16页 (文件大小：448K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Fast Read Access Time - 70 ns
• Automatic Page Write Operation
– Internal Address and Data Latches for 64 Bytes
– Internal Control Timer
• Fast Write Cycle Times
– Page Write Cycle Time: 3 ms or 10 ms Maximum
– 1 to 64-Byte Page Write Operation
• Low Power Dissipation
– 80 mA Active Current
– 3 mA Standby Current
256 (32K x 8)
High Speed
Parallel
• Hardware and Software Data Protection
• DATA Polling for End of Write Detection
• High Reliability CMOS Technology
– Endurance: 104 or 105 Cycles
– Data Retention: 10 Years
• Single 5V ± 10% Supply
• CMOS and TTL Compatible Inputs and Outputs
• JEDEC Approved Byte-Wide Pinout
• Full Military, Commercial, and Industrial Temperature Ranges
EEPROMs
AT28HC256
Description
The AT28HC256 is a high-performance Electrically Erasable and Programmable
Read Only Memory. Its 256K of memory is organized as 32,768 words by 8 bits. Man-
ufactured with Atmel’s advanced nonvolatile CMOS technology, the AT28HC256
(continued)
Pin Configurations
TSOP
Top View
Pin Name
A0 - A14
CE
Function
Addresses
OE
A11
A9
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE
2
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
3
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A8
4
OE
A13
WE
VCC
A14
A12
A7
5
6
WE
7
8
I/O0 - I/O7
NC
9
10
11
12
13
14
A6
A5
DC
Don’t Connect
A4
A1
A3
A2
LCC, PLCC
Top View
CERDIP, PDIP, FLATPACK
Top View
PGA
Top View
A14
A12
A7
1
2
3
4
5
6
7
8
9
28 VCC
27 WE
26 A13
25 A8
A6
A5
A4
A3
A2
5
6
7
8
9
29 A8
28 A9
27 A11
26 NC
25 OE
24 A10
23 CE
22 I/O7
21 I/O6
A6
A5
24 A9
A4
23 A11
22 OE
21 A10
20 CE
19 I/O7
18 I/O6
17 I/O5
16 I/O4
15 I/O3
A3
A2
A1 10
A0 11
A1
A0 10
I/O0 11
I/O1 12
I/O2 13
GND 14
NC 12
I/O0 13
Rev. 0007G–10/98
Note: PLCC package pins 1 and
17 are DON’T CONNECT.
1
offers access times to 70 ns with power dissipation of just
440 mW. When the AT28HC256 is deselected, the standby
current is less than 5 mA.
polling of I/O7. Once the end of a write cycle has been
detected a new access for a read or write can begin.
Atmel’s 28HC256 has additional features to ensure high
quality and manufacturability. The device utilizes internal
error correction for extended endurance and improved data
retention characteristics. An optional software data protec-
tion mechanism is available to guard against inadvertent
writes. The device also includes an extra 64 bytes of
EEPROM for device identification or tracking.
The AT28HC256 is accessed like a Static RAM for the read
or write cycle without the need for external components.
The device contains a 64-byte page register to allow writing
of up to 64 bytes simultaneously. During a write cycle, the
address and 1 to 64 bytes of data are internally latched,
freeing the addresses and data bus for other operations.
Following the initiation of a write cycle, the device will auto-
matically write the latched data using an internal control
timer. The end of a write cycle can be detected by DATA
Block Diagram
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on OE and A9
with Respect to Ground...................................-0.6V to +13.5V
AT28HC256
2
AT28HC256
occur during transition of the host system power supply.
Atmel has incorporated both hardware and software fea-
tures that will protect the memory against inadvertent
writes.
Device Operation
READ: The AT28HC256 is accessed like a Static RAM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state when either CE or OE is high. This dual-
line control gives designers flexibility in preventing bus con-
tention in their system.
HARDWARE PROTECTION: Hardware features protect
against inadvertent writes to the AT28HC256 in the follow-
ing ways: (a) VCC sense—if VCC is below 3.8V (typical) the
write function is inhibited; (b) VCC power-on delay—once
VCC has reached 3.8V the device will automatically time out
5 ms typical) before allowing a write; (c) write inhibit—hold-
ing any one of OE low, CE high or WE high inhibits write
cycles; and (d) noise filter—pulses of less than 15 ns (typi-
cal) on the WE or CE inputs will not initiate a write cycle.
BYTE WRITE: A low pulse on the WE or CE input with CE
or WE low (respectively) and OE high initiates a write cycle.
The address is latched on the falling edge of CE or WE,
whichever occurs last. The data is latched by the first rising
edge of CE or WE. Once a byte write has been started it
will automatically time itself to completion. Once a pro-
gramming operation has been initiated and for the duration
of tWC, a read operation will effectively be a polling opera-
tion.
SOFTWARE DATA PROTECTION: A software controlled
data protection feature has been implemented on the
AT28HC256. When enabled, the software data protection
(SDP), will prevent inadvertent writes. The SDP feature
may be enabled or disabled by the user; the AT28HC256 is
shipped from Atmel with SDP disabled.
PAGE WRITE: The page write operation of the
AT28HC256 allows 1 to 64 bytes of data to be written into
the device during a single internal programming period. A
page write operation is initiated in the same manner as a
byte write; the first byte written can then be followed by 1 to
63 additional bytes. Each successive byte must be written
within 150 µs (tBLC) of the previous byte. If the tBLC limit is
exceeded the AT28C256 will cease accepting data and
commence the internal programming operation. All bytes
during a page write operation must reside on the same
page as defined by the state of the A6 - A14 inputs. That is,
for each WE high to low transition during the page write
operation, A6 - A14 must be the same.
SDP is enabled by the host system issuing a series of three
write commands; three specific bytes of data are written to
three specific addresses (refer to Software Data Protection
Algorithm). After writing the 3-byte command sequence
and after tWC the entire AT28HC256 will be protected
against inadvertent write operations. It should be noted,
that once protected the host may still perform a byte or
page write to the AT28HC256. This is done by preceding
the data to be written by the same 3-byte command
sequence.
Once set, SDP will remain active unless the disable com-
mand sequence is issued. Power transitions do not disable
SDP and SDP will protect the AT28HC256 during power-up
and power-down conditions. All command sequences must
conform to the page write timing specifications. It should
also be noted that the data in the enable and disable com-
mand sequences is not written to the device and the mem-
ory addresses used in the sequence may be written with
data in either a byte or page write operation.
The A0 to A5 inputs are used to specify which bytes within
the page are to be written. The bytes may be loaded in any
order and may be altered within the same load period. Only
bytes which are specified for writing will be written; unnec-
essary cycling of other bytes within the page does not
occur.
DATA POLLING: The AT28HC256 features DATA Polling
to indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will
result in the complement of the written data to be presented
on I/O7. Once the write cycle has been completed, true
data is valid on all outputs, and the next write cycle may
begin. DATA Polling may begin at anytime during the write
cycle.
After setting SDP, any attempt to write to the device without
the three byte command sequence will start the internal
write timers. No data will be written to the device; however,
for the duration of tWC, read operations will effectively be
polling operations.
DEVICE IDENTIFICATION: An extra 64 bytes of EEPROM
memory are available to the user for device identification.
By raising A9 to 12V ± 0.5V and using address locations
7FC0H to 7FFFH the additional bytes may be written to or
read from in the same manner as the regular memory
array.
TOGGLE BIT: In addition to DATA Polling the AT28HC256
provides another method for determining the end of a write
cycle. During the write operation, successive attempts to
read data from the device will result in I/O6 toggling
between one and zero. Once the write has completed, I/O6
will stop toggling and valid data will be read. Testing the
toggle bit may begin at any time during the write cycle.
OPTIONAL CHIP ERASE MODE: The entire device can
be erased using a 6-byte software code. Please see Soft-
ware Chip Erase application note for details.
DATA PROTECTION: If precautions are not taken, inad-
vertent writes to any 5-volt-only nonvolatile memory may
3
DC and AC Operating Range
AT28HC256-70
0°C - 70°C
AT28HC256-90
0°C - 70°C
AT28HC256-12
0°C - 70°C
Com.
Operating
Temperature (Case)
Ind.
-40°C - 85°C
-40°C - 85°C
-55°C - 125°C
5V ± 10%
-40°C - 85°C
-55°C - 125°C
5V ± 10%
Mil.
VCC Power Supply
5V ± 10%
Operating Modes
Mode
CE
VIL
VIL
VIH
X
OE
VIL
VIH
X(1)
X
WE
VIH
VIL
X
I/O
DOUT
DIN
Read
Write(2)
Standby/Write Inhibit
Write Inhibit
Write Inhibit
Output Disable
High Z
VIH
X
X
VIL
VIH
X
X
High Z
High Z
(3)
Chip Erase
VIL
VH
VIL
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
DC Characteristics
Symbol
Parameter
Condition
Min
Max
10
Units
ILI
Input Load Current
Output Leakage Current
VIN = 0V to VCC + 1V
VI/O = 0V to VCC
µA
µA
mA
mA
µA
mA
V
ILO
10
AT28HC256-90, -12
AT28HC256-70
3
ISB1
VCC Standby Current TTL
CE = 2.0V to VCC + 1V
60
ISB2
ICC
VCC Standby Current CMOS
VCC Active Current
CE = -3.0V to VCC + 1V AT28HC256-90, -12
f = 5 MHz; IOUT = 0 mA
300
80
VIL
Input Low Voltage
0.8
VIH
VOL
VOH
Input High Voltage
2.0
2.4
V
Output Low Voltage
Output High Voltage
IOL = 6.0 mA
IOH = -4 mA
0.45
V
V
AT28HC256
4
AT28HC256
AC Read Characteristics
AT28HC256-70
AT28C256-90
AT28HC256-12
Symbol
tACC
Parameter
Address to Output Delay
CE to Output Delay
Min
Max
70
Min
Max
Min
Max
120
120
50
Units
ns
90
90
40
40
(1)
tCE
tOE
tDF
70
ns
(2)
OE to Output Delay
0
0
35
0
0
0
0
ns
(3)(4)
CE or OE to Output Float
35
50
ns
Output Hold from OE, CE or Address,
whichever occurred first
tOH
0
0
0
ns
AC Read Waveforms(1)(2)(3)(4)
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC
.
.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement Level
Output Test Load
tR, tF < 5 ns
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
Typ
4
Max
6
Units
pF
Conditions
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
5
AC Write Characteristics
Symbol
Parameter
Min
0
Max
Units
ns
t
AS, tOES
Address, OE Set-up Time
Address Hold Time
tAH
tCS
tCH
tWP
tDS
50
0
ns
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
ns
0
ns
100
50
0
ns
ns
t
DH, tOEH
Data, OE Hold Time
ns
tDV
Time to Data Valid
NR(1)
Note:
1. NR = No Restriction.
AC Write Waveforms
WE Controlled
CE Controlled
AT28HC256
6
AT28HC256
Page Mode Write Characteristics
Symbol
Parameter
Min
Typ
5
Max
10
Units
ms
ms
ns
AT28HC256
tWC
Write Cycle Time
AT28HC256F
2
3.0
tAS
Address Set-up Time
Address Hold Time
Data Set-up Time
0
50
50
0
tAH
ns
tDS
ns
tDH
Data Hold Time
ns
tWP
tBLC
tWPH
Write Pulse Width
Byte Load Cycle Time
Write Pulse Width High
100
ns
150
µs
50
ns
Page Mode Write Waveforms(1)(2)
Notes: 1. A6 through A14 must specify the same page address during each high to low transition of WE (or CE).
2. OE must be high only when WE and CE are both low.
Chip Erase Waveforms
tS = tH = 5 µsec (min.)
tW = 10 msec (min.)
VH = 12.0V ± 0.5V
7
Software Data Protection
Enable Algorithm(1)
Software Data Protection
Disable Algorithm(1)
LOAD DATA AA
TO
LOAD DATA AA
TO
ADDRESS 5555
ADDRESS 5555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS 2AAA
ADDRESS 2AAA
LOAD DATA A0
TO
LOAD DATA 80
TO
ADDRESS 5555
ADDRESS 5555
WRITES ENABLED(2)
LOAD DATA XX
TO
ANY ADDRESS(4)
LOAD DATA AA
TO
ADDRESS 5555
LOAD LAST BYTE
TO
LOAD DATA 55
TO
LAST ADDRESS
ADDRESS 2AAA
ENTER DATA
PROTECT STATE
LOAD DATA 20
TO
Notes for software program code:
ADDRESS 5555
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
EXIT DATA
PROTECT STATE(3)
LOAD DATA XX
TO
ANY ADDRESS(4)
2. Write Protect state will be activated at end of
write even if no other data is loaded.
3. Write Protect state will be deactivated at end of
write period even if no other data is loaded.
LOAD LAST BYTE
TO
4. 1 to 64 bytes of data are loaded.
LAST ADDRESS
Software Protected Write Cycle Waveforms(1)(2)
Notes: 1. A6 through A14 must specify the same page address during each high to low transition of WE (or CE) after the software
code has been entered.
2. OE must be high only when WE and CE are both low.
AT28HC256
8
AT28HC256
Data Polling Characteristics(1)
Symbol
Parameter
Min
0
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
OE Hold Time
0
ns
OE to Output Delay(2)
Write Recovery Time
ns
tWR
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
Data Polling Waveforms
Toggle Bit Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
OE Hold Time
tOEH
tOE
tOEHP
tWR
10
ns
OE to Output Delay(2)
ns
OE High Pulse
150
0
ns
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
Toggle Bit Waveforms
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
9
AT28HC256
10
AT28HC256
Ordering Information(1)
I
Active
80
CC (mA)
tACC
(ns)
Standby
Ordering Code
Package
Operation Range
70
60
0.3
0.3
AT28HC256(E,F)-70JC
AT28HC256(E,F)-70PC
32J
Commercial
28P6
(0°C to 70°C)
AT28HC256(E,F)-70JI
AT28HC256(E,F)-70PI
32J
Industrial
28P6
(-40°C to 85°C)
90
80
AT28HC256(E,F)-90JC
AT28HC256(E,F)-90PC
32J
Commercial
28P6
(0°C to 70°C)
AT28HC256(E,F)-90JI
AT28HC256(E,F)-90PI
32J
Industrial
28P6
(-40°C to 85°C)
80
80
80
80
0.3
0.3
0.3
0.3
AT28HC256(E,F)-90DM/883
AT28HC256(E,F)-90FM/883
AT28HC256(E,F)-90LM/883
AT28HC256(E,F)-90UM/883
28D6
28F
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
32L
28U
120
AT28HC256(E,F)-12JC
AT28HC256(E,F)-12PC
AT28HC256(E,F)-12SC
AT28HC256(E,F)-12TC
32J
Commercial
28P6
28S
28T
(0°C to 70°C)
AT28HC256(E,F)-12JI
AT28HC256(E,F)-12PI
AT28HC256(E,F)-12SI
AT28HC256(E,F)-12TI
32J
Industrial
28P6
28S
28T
(-40°C to 85°C)
AT28HC256(E,F)-12DM/883
AT28HC256(E,F)-12FM/883
AT28HC256(E,F)-12LM/883
AT28HC256(E,F)-12UM/883
28D6
28F
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
32L
28U
Package Type
28D6
28-Lead, 0.600" Wide, Non-Windowed, Ceramic Dual Inline Package (Cerdip)
28-Lead, Non-Windowed, Ceramic Bottom-Brazed Flat Package (Flatpack)
32-Lead, Plastic J-Leaded Chip Carrier (PLCC)
32-Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC)
28-Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
28-Lead, 0.300" Wide Plastic Gull Wing Small Outline (SOIC)
28-Lead, Plastic Thin Small Outline Package (TSOP)
28-Pin, Ceramic Pin Grid Array (PGA)
28F
32J
32L
28P6
28S
28T
28U
W
Die
Options
Blank
Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms
High Endurance Option: Endurance = 100K Write Cycles
Fast Write Option: Write Time = 3 ms
E
F
11
Ordering Information(1) (Continued)
I
Active
80
CC (mA)
tACC
(ns)
Standby
Ordering Code
Package
Operation Range
90
0.3
0.3
0.3
0.3
5962-88634 03 UX
5962-88634 03 XX
5962-88634 03 YX
5962-88634 03 ZX
28U
28D6
32L
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
28F
80
80
80
5962-88634 04 UX
5962-88634 04 XX
5962-88634 04 YX
5962-88634 04 ZX
28U
28D6
32L
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
28F
120
5962-88634 01 UX
5962-88634 01 XX
5962-88634 01 YX
5962-88634 01 ZX
28U
28D6
32L
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
28F
5962-88634 02 UX
5962-88634 02 XX
5962-88634 02 YX
5962-88634 02 ZX
28U
28D6
32L
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
28F
Note:
1. See Valid Part Numbers table on next page.
Package Type
28D6
28-Lead, 0.600" Wide, Non-Windowed, Ceramic Dual Inline Package (Cerdip)
28-Lead, Non-Windowed, Ceramic Bottom-Brazed Flat Package (Flatpack)
32-Lead, Plastic J-Leaded Chip Carrier (PLCC)
32-Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC)
28-Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
28-Lead, 0.300" Wide Plastic Gull Wing Small Outline (SOIC)
28-Lead, Plastic Thin Small Outline Package (TSOP)
28-Pin, Ceramic Pin Grid Array (PGA)
28F
32J
32L
28P6
28S
28T
28U
W
Die
Options
Blank
Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms
High Endurance Option: Endurance = 100K Write Cycles
Fast Write Option: Write Time = 3 ms
E
F
AT28HC256
12
AT28HC256
Ordering Information Note
Previous data sheets included the low power suffixes L, LE and LF on the At28HC256 for 120 ns and 90 ns speeds.
The low power parameters are now standard; therefore, the L, LE and LF suffixes are no longer required.
Valid Part Numbers
The following table lists standard Atmel products that can be ordered:
Device Numbers
AT28HC256
Speed
70
Package and Temperature Combinations
JC, JI, PC, PI
AT28HC256
90
JC, JI, PC, PI, TC, TI, DM/883, FM/883, UM/883
JC, JI, PC, PI, TC, TI, DM/883, FM/883, UM/883
JC, JI, PC, PI, TC, TI, DM/883, FM/883, UM/883
JC, JI, PC, PI, TC, TI, DM/883, FM/883, UM/883
JC, JI, PC, PI, TC, TI, DM/883, FM/883, UM/883
JC, JI, PC, PI, TC, TI, DM/883, FM/883, UM/883
AT28HC256E
AT28HC256F
AT28HC256
90
90
12
AT28HC256E
AT28HC256F
12
12
Die Products
Reference Section: Parallel EEPROM Die Products
13
Packaging Information
28D6, 28-Lead, 0.600" Wide, Non-Windowed,
28F, 28-Lead, Non-Windowed, Ceramic Bottom-
Ceramic Dual Inline Package (Cerdip)
Dimensions in Inches and (Millimeters)
MIL-STD-1835 D-10 CONFIG A
Brazed Flat Package (Flatpack)
Dimensions in Inches and (Millimeters)
MIL-STD-1835 F-12 CONFIG B
1.49(37.9)
1.44(36.6)
PIN
1
.370(9.40)
PIN #1 ID
.250(6.35)
.019(.483)
.015(.381)
.610(15.5)
.510(13.0)
.050(1.27) BSC
.728(18.5)
.712(18.1)
.098(2.49)
MAX
1.300(33.02) REF
.045(1.14) MAX
.005(.127)
MIN
.225(5.72)
MAX
.416(10.6)
.384(9.75)
SEATING
PLANE
.200(5.08)
.060(1.52)
.015(.381)
.023(.584)
.014(.356)
.125(3.18)
.006(.152)
.004(.102)
.119(3.02)
.087(2.21)
.065(1.65)
.045(1.14)
.110(2.79)
.090(2.29)
.620(15.7)
.590(15.0)
.077(1.96)
.043(1.09)
0
15
REF
.045(1.14)
.026(.660)
.286(7.26)
.274(6.96)
.015(.381)
.008(.203)
.700(17.8) MAX
32J, 32-Lead, Plastic J-Leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-016 AE
32L, 32-Pad, Non-Windowed, Ceramic Leadless
Chip Carrier (LCC)
Dimensions in Inches and (Millimeters)*
MIL-STD-1835 C-12
.025(.635) X 30° - 45°
.045(1.14) X 45° PIN NO. 1
.012(.305)
IDENTIFY
.008(.203)
.530(13.5)
.553(14.0)
.490(12.4)
.547(13.9)
.032(.813)
.021(.533)
.013(.330)
.595(15.1)
.026(.660)
.585(14.9)
.030(.762)
.015(3.81)
.095(2.41)
.060(1.52)
.140(3.56)
.120(3.05)
.050(1.27) TYP
.300(7.62) REF
.430(10.9)
.390(9.90)
AT CONTACT
POINTS
.022(.559) X 45° MAX (3X)
.453(11.5)
.447(11.4)
.495(12.6)
.485(12.3)
*Controlling dimension: millimeters
AT28HC256
14
AT28HC256
Packaging Information
28P6, 28-Lead, 0.600" Wide, Plastic Dual Inline
Package (PDIP)
28S, 28-Lead, 0.300" Wide, Plastic Gull Wing Small
Outline (SOIC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-011 AB
Dimensions in Inches and (Millimeters)
1.47(37.3)
1.44(36.6)
PIN
1
.566(14.4)
.530(13.5)
.090(2.29)
MAX
1.300(33.02) REF
.220(5.59)
MAX
.005(.127)
MIN
SEATING
PLANE
.065(1.65)
.015(.381)
.022(.559)
.014(.356)
.161(4.09)
.125(3.18)
.065(1.65)
.041(1.04)
.110(2.79)
.090(2.29)
.630(16.0)
.590(15.0)
0
15
REF
.012(.305)
.008(.203)
.690(17.5)
.610(15.5)
28T, 28-Lead, Plastic Thin Small Outline Package
(TSOP)
28U, 28-Pin, Ceramic Pin Grid Array (PGA)
Dimensions in Inches and (Millimeters)
Dimensions in Millimeters and (Inches)*
INDEX
MARK
AREA
13.7 (0.539)
13.1 (0.516)
11.9 (0.469)
11.7 (0.461)
0.27 (0.011)
0.18 (0.007)
0.55 (0.022)
BSC
7.15 (0.281)
REF
8.10 (0.319)
7.90 (0.311)
1.25 (0.049)
1.05 (0.041)
0.20 (0.008)
0.10 (0.004)
0
REF
5
0.20 (0.008)
0.15 (0.006)
0.70 (0.028)
0.30 (0.012)
*Controlling dimension: millimeters
15
Atmel Headquarters
Atmel Operations
Corporate Headquarters
2325 Orchard Parkway
San Jose, CA 95131
TEL (408) 441-0311
FAX (408) 487-2600
Atmel Colorado Springs
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL (719) 576-3300
FAX (719) 540-1759
Europe
Atmel U.K., Ltd.
Atmel Rousset
Zone Industrielle
Coliseum Business Centre
Riverside Way
Camberley, Surrey GU15 3YL
England
13106 Rousset Cedex, France
TEL (33) 4 42 53 60 00
FAX (33) 4 42 53 60 01
TEL (44) 1276-686677
FAX (44) 1276-686697
Asia
Atmel Asia, Ltd.
Room 1219
Chinachem Golden Plaza
77 Mody Road
Tsimshatsui East
Kowloon, Hong Kong
TEL (852) 27219778
FAX (852) 27221369
Japan
Atmel Japan K.K.
Tonetsu Shinkawa Bldg., 9F
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
TEL (81) 3-3523-3551
FAX (81) 3-3523-7581
Fax-on-Demand
North America:
1-(800) 292-8635
International:
1-(408) 441-0732
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
BBS
1-(408) 436-4309
© Atmel Corporation 1998.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-
ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s website. The Company assumes no responsibility for
any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without
notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual prop-
erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are
not authorized for use as critical components in life support devices or systems.
®
™
Marks bearing and/or are registered trademarks and trademarks of Atmel Corporation.
Terms and product names in this document may be trademarks of others.
Printed on recycled paper.
0007G–05/98/xM
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