AT28LV010-20TI [ATMEL]
1 Megabit 128K x 8 Low Voltage Paged CMOS E2PROM; 1兆位128K ×8低压分页CMOS E2PROM型号: | AT28LV010-20TI |
厂家: | ATMEL |
描述: | 1 Megabit 128K x 8 Low Voltage Paged CMOS E2PROM |
文件: | 总9页 (文件大小:501K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
AT28LV010
Features
Single 3.3V ± 10% Supply
Fast Read Access Time - 200 ns
Automatic Page Write Operation
•
•
•
Internal Address and Data Latches for 128-Bytes
Internal Control Timer
Fast Write Cycle Time
•
Page Write Cycle Time - 10 ms Maximum
1 to 128-Byte Page Write Operation
Low Power Dissipation
•
15 mA Active Current
1 Megabit
20 µA CMOS Standby Current
Hardware and Software Data Protection
DATA Polling for End of Write Detection
High Reliability CMOS Technology
Endurance: 100,000K Cycles
Data Retention: 10 Years
JEDEC Approved Byte-Wide Pinout
•
•
(128K x 8)
•
Low Voltage
Paged CMOS
E2PROM
•
Commercial and Industrial Temperature Ranges
•
Description
The AT28LV010 is a high-performance 3-volt only Electrically Erasable and Program-
mable Read Only Memory. Its 1 megabit of memory is organized as 131,072 words
by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the
device offers access times to 200 ns with power dissipation of just 54 mW. When the
device is deselected, the CMOS standby current is less than 20 µA.
(continued)
Pin Configurations
Pin Name
A0 - A16
CE
Function
PDIP
Top View
Addresses
Chip Enable
Output Enable
Write Enable
AT28LV010
OE
WE
Data
Inputs/Outputs
I/O0 - I/O7
NC
DC
No Connect
Don’t Connect
PLCC
Top View
TSOP
Top View
0395A
2-155
Description (Continued)
The AT28LV010 is accessed like a Static RAM for the
read or write cycle without the need for external compo-
nents. The device contains a 128-byte page register to al-
low writing of up to 128-bytes simultaneously. During a
write cycle, the address and 1 to 128-bytes of data are
internally latched, freeing the address and data bus for
other operations. Following the initiation of a write cycle,
the device will automatically write the latched data using
an internal control timer. The end of a write cycle can be
detected by DATA polling of I/O7. Once the end of a write
cycle has been detected a new access for a read or write
can begin.
Atmel’s 28LV010 has additional features to ensure high
quality and manufacturability. The device utilizes internal
error correction for extended endurance and improved
data retention characteristics. Software data protection is
implemented to guard against inadvertent writes. The de-
2
vice also includes an extra 128-bytes of E PROM for de-
vice identification or tracking.
Block Diagram
Absolute Maximum Ratings*
*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Temperature Under Bias................. -55°C to +125°C
Storage Temperature...................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground .............-0.6V to V + 0.6V
CC
Voltage on OE and A9
with Respect to Ground ................... -0.6V to +13.5V
2-156
AT28LV010
AT28LV010
Device Operation
READ: The AT28LV010 is accessed like a Static RAM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state when either CE or OE is high. This dual-
line control gives designers flexibility in preventing bus
contention in their system.
TOGGLE BIT: In addition to DATA Polling the AT28LV010
provides another method for determining the end of a write
cycle. During the write operation, successive attempts to
read data from the device will result in I/O6 toggling be-
tween one and zero. Once the write has completed, I/O6
will stop toggling and valid data will be read. Reading the
toggle bit may begin at any time during the write cycle.
WRITE: The write operation of the AT28LV010 allows 1 to
128-bytes of data to be written into the device during a
single internal programming period. Each write operation
must be preceded by the software data protection (SDP)
command sequence. This sequence is a series of three
unique write command operations that enable the internal
write circuitry. The command sequence and the data to be
written must conform to the software protected write cycle
timing. Addresses are latched on the falling edge of WE or
CE, whichever occurs last and data is latched on the rising
edge of WE or CE, whichever occurs first. Each succes-
DATA PROTECTION: If precautions are not taken, inad-
vertent writes may occur during transitions of the host sys-
tem power supply. Atmel has incorporated both hardware
and software features that will protect the memory against
inadvertent writes.
HARDWARE PROTECTION: Hardware features protect
against inadvertent writes to the AT28LV010 in the follow-
ing ways: (a) V power-on delay - once V has reached
CC
CC
2.0V (typical) the device will automatically time out 5 ms
(typical) before allowing a write: (b) write inhibit - holding
any one of OE low, CE high or WE high inhibits write cy-
cles; (c) noise filter - pulses of less than 15 ns (typical) on
the WE or CE inputs will not initiate a write cycle.
sive byte must be written within 150 µs (t
) of the pre-
BLC
vious byte. If the t
limit is exceeded the AT28LV010 will
BLC
cease accepting data and commence the interal program-
ming operation. If more than one data byte is to be written
during a single programming operation, they must reside
on the same page as defined by the state of the A7 - A16
inputs. For each WE high to low transition during the page
write operation, A7 - A16 must be the same.
SOFTWARE DATA PROTECTION: The AT28LV010 in-
corporates the industry standard software data protection
2
(SDP) function. Unlike standard 5-volt only E PROM’s,
the AT28LV010 has SDP enabled at all times. Therefore,
all write operations must be preceded by the SDP com-
mand sequence.
The A0 to A6 inputs are used to specify which bytes within
the page are to be written. The bytes may be loaded in any
order and may be altered within the same load period.
Only bytes which are specified for writing will be written;
unnecessary cycling of other bytes within the page does
not occur.
The data in the 3-byte command sequence is not written
to the device; the addresses in the command sequence
can be utilized just like any other location in the device.
Any attempt to write to the device without the 3-byte se-
quence will start the internal timers. No data will be written
to the device. However, for the duration of t , read op-
WC
DATA POLLING: The AT28LV010 features DATA Polling
to indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will
result in the complement of the written data to be pre-
sented on I/O7. Once the write cycle has been completed,
true data is valid on all outputs, and the next write cycle
may begin. DATA Polling may begin at anytime during the
write cycle.
erations will effectively be polling operations.
2-157
DC and AC Operating Range
AT28LV010-20
0°C - 70°C
AT28LV010-25
0°C - 70°C
Com.
Ind.
Operating
Temperature (Case)
-40°C - 85°C
3.3V ± 5%
-40°C - 85°C
3.3V ± 10%
V
Power Supply
CC
Operating Modes
Mode
CE
OE
WE
I/O
Read
V
V
V
V
D
D
IL
IL
IH
IL
IH
OUT
IN
(2)
Write
V
V
IH
IL
(1)
Standby/Write Inhibit
Write Inhibit
V
X
X
High Z
X
X
V
IH
Write Inhibit
X
X
V
X
IL
Output Disable
V
X
High Z
IH
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
DC Characteristics
Symbol
Parameter
Condition
Min
Max
1
Units
µA
µA
µA
µA
mA
V
I
LI
Input Load Current
Output Leakage Current
V
V
= 0V to V
CC
IN
I
LO
= 0V to V
CC
1
I/O
Com.
Ind.
20
50
15
0.8
I
I
V
Standby Current CMOS
CE = V - 0.3V to V + 1V
CC CC
SB
CC
V
Active Current
f = 5 MHz; I
= 0 mA; V = 3.6V
CC
CC
CC
OUT
V
V
V
V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
IL
2.0
2.4
V
IH
I
I
= 1.6 mA; V = 3.0V
.45
V
OL
OH
OL
CC
= -100 µA; V = 3.0V
V
OH
CC
2-158
AT28LV010
AT28LV010
AC Read Characteristics
AT28LV010-20
AT28LV010-25
Min
Max
Min
Max
250
250
100
60
Symbol
Parameter
Units
ns
t
t
t
t
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
200
200
80
ACC
(1)
ns
CE
OE
DF
(2)
0
0
0
0
ns
(3, 4)
55
ns
Output Hold from OE, CE or
Address, whichever occurred
first
t
0
0
ns
OH
AC Read Waveforms (1, 2, 3, 4)
Notes: 1. CE may be delayed up to tACC - tCE after the address
transition without impact on tACC
3. tDF is specified from OE or CE whichever occurs first
(CL = 5pF).
.
2. OE may be delayed up to tCE - tOE after the falling
edge of CE without impact on tCE or by tACC - tOE
4. This parameter is characterized and is not 100% tested.
after an address change without impact on tACC
.
Output Test Load
Input Test Waveforms and
Measurement Level
t , t < 5 ns
R
F
Pin Capacitance (f = 1 MHz, T = 25°C) (1)
Typ
Max
6
Units
pF
Conditions
C
C
4
8
V
V
= 0V
IN
IN
12
pF
= 0V
OUT
OUT
Note: 1. This parameter is characterized and is not 100% tested.
2-159
AC Write Characteristics (1)
Symbol
Parameter
Min
0
Max
Units
ns
t
t
t
t
t
t
t
, t
Address, OE Set-up Time
Address Hold Time
AS OES
100
0
ns
AH
CS
CH
WP
DS
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
ns
0
ns
200
100
10
ns
ns
, t
Data, OE Hold Time
ns
DH OEH
Note: 1. All write operations must be preceded by the SDP command sequence.
AC Write Waveforms
WE Controlled
CE Controlled
2-160
AT28LV010
AT28LV010
Software Protected Write Characteristics
Symbol
Parameter
Min
Max
Units
ms
ns
t
t
t
t
t
t
t
t
Write Cycle Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
10
WC
0
AS
100
100
10
ns
AH
ns
DS
ns
DH
Write Pulse Width
Byte Load Cycle Time
Write Pulse Width High
200
ns
WP
BLC
WPH
150
µs
100
ns
Programming Algorithm
LOAD DATA AA
TO
ADDRESS 5555
Notes:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Data protect state will be re-activated at the end of program
LOAD DATA 55
TO
ADDRESS 2AAA
cycle.
3. 1 to 128-bytes of data are loaded.
LOAD DATA A0
TO
ADDRESS 5555
WRITES ENABLED (2)
LOAD DATA XX
TO
ANY ADDRESS (3)
LOAD LAST BYTE
TO
LAST ADDRESS (3)
ENTER DATA
PROTECT STATE
Software Protected Program Cycle Waveforms (1, 2, 3)
Notes: 1. A0 - A14 must conform to the addressing sequence for the first 3-bytes as shown above.
2. After the command sequence has been issued and a page write operation follows, the page address inputs (A7 - A16)
must be the same for each high to low transition of WE (or CE).
3. OE must be high only when WE and CE are both low.
2-161
Data Polling Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
t
t
t
t
Data Hold Time
OE Hold Time
OE to Output Delay
DH
10
ns
OEH
OE
(2)
ns
Write Recovery Time
0
ns
WR
Notes: 1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
Data Polling Waveforms
Toggle Bit Characteristics (1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
t
t
t
t
t
Data Hold Time
OE Hold Time
OE to Output Delay
OE High Pulse
DH
10
ns
OEH
OE
(2)
ns
150
0
ns
OEHP
WR
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
Toggle Bit Waveforms
3. Any address location may be used but the
address should not vary.
Notes: 1. Toggling either OE or CE or both OE and CE will
operate toggle bit.
2. Beginning and ending state of I/O6 will vary.
2-162
AT28LV010
AT28LV010
Ordering Information (1)
t
I
(mA)
ACC
CC
Ordering Code
Package
Operation Range
Active Standby
(ns)
200
15
15
15
15
0.2
0.2
0.2
0.2
AT28LV010-20JC
AT28LV010-20PC
AT28LV010-20TC
32J
32P6
32T
Commercial
(0° to 70°C)
AT28LV010-20JI
AT28LV010-20PI
AT28LV010-20TI
32J
32P6
32T
Industrial
(-40° to 85°C)
250
AT28LV010-25JC
AT28LV010-25PC
AT28LV010-25TC
32J
32P6
32T
Commercial
(0° to 70°C)
AT28LV010-25JI
AT28LV010-25PI
AT28LV010-25TI
32J
32P6
32T
Industrial
(-40° to 85°C)
Note: 1. See Valid Part Number table below.
Valid Part Numbers
The following table lists standard Atmel products that can be ordered.
Device Numbers
AT28LV010
Speed
Package and Temperature Combinations
JC, JI, PC, PI, TC, TI
20
25
AT28LV010
JC, JI, PC, PI, TC, TI
Package Type
32J
32 Lead, Plastic J-Leaded Chip Carrier (PLCC)
32P6
32T
32 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
32 Lead, Plastic Thin Small Outline Package (TSOP)
2-163
相关型号:
©2020 ICPDF网 联系我们和版权申明