AT29C010A-12JIT/R [ATMEL]
Flash, 128KX8, 120ns, PQCC32, PLASTIC, LCC-32;
| 型号： | AT29C010A-12JIT/R |
| 厂家： | 
ATMEL |
| 描述： | Flash, 128KX8, 120ns, PQCC32, PLASTIC, LCC-32 闪存 |
| 文件： | 总18页 (文件大小：214K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Fast Read Access Time – 70 ns
• 5-volt Only Reprogramming
• Sector Program Operation
– Single Cycle Reprogram (Erase and Program)
– 1024 Sectors (128 Bytes/sector)
– Internal Address and Data Latches for 128 Bytes
• Two 8K Bytes Boot Blocks with Lockout
• Internal Program Control and Timer
• Hardware and Software Data Protection
• Fast Sector Program Cycle Time – 10 ms
• DATA Polling for End of Program Detection
• Low Power Dissipation
1-Megabit
(128K x 8)
– 50 mA Active Current
– 100 µA CMOS Standby Current
5-volt Only
Flash Memory
• Typical Endurance > 10,000 Cycles
• Single 5V ±ꢀ10% Supply
• CMOS and TTL Compatible Inputs and Outputs
• Commercial and Industrial Temperature Ranges
Description
AT29C010A
The AT29C010A is a 5-volt-only in-system Flash programmable and erasable read
only memory (PEROM). Its 1 megabit of memory is organized as 131,072 words by
8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device
offers access times to 70 ns with power dissipation of just 275 mW over the commer-
cial temperature range. When the device is deselected, the CMOS standby current is
DIP Top View
Pin Configurations
Pin Name
A0 - A16
CE
Function
NC
A16
A15
A12
A7
1
2
3
4
5
6
7
8
9
32 VCC
31 WE
30 NC
29 A14
28 A13
27 A8
Addresses
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
A6
OE
A5
26 A9
A4
25 A11
24 OE
23 A10
22 CE
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
WE
A3
A2 10
A1 11
I/O0 - I/O7
NC
A0 12
I/O0 13
I/O1 14
I/O2 15
GND 16
TSOP Top View
Type 1
PLCC Top View
A11
A9
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
2
A10
CE
A8
3
A13
A14
NC
WE
VCC
NC
A16
A15
A12
A7
4
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
5
A7
A6
A5
A4
A3
5
6
7
8
9
29 A14
6
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 I/O7
7
8
9
10
11
12
13
14
15
16
A2 10
A1 11
A0 12
I/O0 13
A6
A1
A5
A2
Rev. 0394E–FLASH–11/02
A4
A3
1
less than 100ꢀµA. The device endurance is such that any sector can typically be written
to in excess of 10,000 times.
To allow for simple in-system reprogrammability, the AT29C010A does not require high
input voltages for programming. Five-volt-only commands determine the operation of
the device. Reading data out of the device is similar to reading from an EPROM. Repro-
gramming the AT29C010A is performed on a sector basis; 128 bytes of data are loaded
into the device and then simultaneously programmed.
During a reprogram cycle, the address locations and 128 bytes of data are internally
latched, freeing the address and data bus for other operations. Following the initiation of
a program cycle, the device will automatically erase the sector and then program the
latched data using an internal control timer. The end of a program cycle can be detected
by DATA polling of I/O7. Once the end of a program cycle has been detected, a new
access for a read or program can begin.
Block Diagram
Device Operation
READ: The AT29C010A is accessed like an EPROM. When CE and OE are low and
WE is high, the data stored at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high impedance state whenever CE
or OE is high. This dual-line control gives designers flexibility in preventing bus
contention.
BYTE LOAD: Byte loads are used to enter the 128 bytes of a sector to be programmed
or the software codes for data protection. A byte load is performed by applying a low
pulse on the WE or CE input with CE or WE low (respectively) and OE high. The
address is latched on the falling edge of CE or WE, whichever occurs last. The data is
latched by the first rising edge of CE or WE.
PROGRAM: The device is reprogrammed on a sector basis. If a byte of data within a
sector is to be changed, data for the entire sector must be loaded into the device. The
data in any byte that is not loaded during the programming of its sector will be indetermi-
nate. Once the bytes of a sector are loaded into the device, they are simultaneously
programmed during the internal programming period. After the first data byte has been
loaded into the device, successive bytes are entered in the same manner. Each new
byte to be programmed must have its high to low transition on WE (or CE) within 150 ꢁs
of the low to high transition of WE (or CE) of the preceding byte. If a high to low transi-
tion is not detected within 150 ꢁs of the last low to high transition, the load period will
end and the internal programming period will start. A7 to A16 specify the sector address.
2
AT29C010A
0394E–FLASH–11/02
AT29C010A
The sector address must be valid during each high to low transition of WE (or CE). A0 to
A6 specify the byte address within the sector. The bytes may be loaded in any order;
sequential loading is not required. Once a programming operation has been initiated,
and for the duration of tWC, a read operation will effectively be a polling operation.
SOFTWARE DATA PROTECTION: A software controlled data protection feature is
available on the AT29C010A. Once the software protection is enabled a software algo-
rithm must be issued to the device before a program may be performed. The software
protection feature may be enabled or disabled by the user; when shipped from Atmel,
the software data protection feature is disabled. To enable the software data protection,
a series of three program commands to specific addresses with specific data must be
performed. After the software data protection is enabled the same three program com-
mands must begin each program cycle in order for the programs to occur. All software
program commands must obey the sector program timing specifications. Once set, the
software data protection feature remains active unless its disable command is issued.
Power transitions will not reset the software data protection feature, however the soft-
ware feature will guard against inadvertent program cycles during power transitions.
Once set, software data protection will remain active unless the disable command
sequence is issued.
After setting SDP, any attempt to write to the device without the 3-byte command
sequence will start the internal write timers. No data will be written to the device; how-
ever, for the duration of tWC, a read operation will effectively be a polling operation.
After the software data protection’s 3-byte command code is given, a byte load is per-
formed by applying a low pulse on the WE or CE input with CE or WE low (respectively)
and OE high. The address is latched on the falling edge of CE or WE, whichever occurs
last. The data is latched by the first rising edge of CE or WE. The 128 bytes of data must
be loaded into each sector by the same procedure as outlined in the program section
under device operation.
HARDWARE DATA PROTECTION: Hardware features protect against inadvertent pro-
grams to the AT29C010A in the following ways: (a) VCC sense – if VCC is below 3.8V
(typical), the program function is inhibited; (b) VCC power on delay – once VCC has
reached the VCC sense level, the device will automatically time out 5 ms (typical) before
programming; (c) Program inhibit – holding any one of OE low, CE high or WE high
inhibits program cycles; and (d) Noise filter—pulses of less than 15 ns (typical) on the
WE or CE inputs will not initiate a program cycle.
PRODUCT IDENTIFICATION: The product identification mode identifies the device and
manufacturer as Atmel. It may be accessed by hardware or software operation. The
hardware operation mode can be used by an external programmer to identify the correct
programming algorithm for the Atmel product. In addition, users may wish to use the
software product identification mode to identify the part (i.e. using the device code), and
have the system software use the appropriate sector size for program operations. In this
manner, the user can have a common board design for 256K to 4-megabit densities
and, with each density’s sector size in a memory map, have the system software apply
the appropriate sector size.
For details, see Operating Modes (for hardware operation) or Software Product Identifi-
cation. The manufacturer and device code is the same for both modes.
DATA POLLING: The AT29C010A features DATA polling to indicate the end of a pro-
gram cycle. During a program cycle an attempted read of the last byte loaded will result
in the complement of the loaded data on I/O7. Once the program cycle has been com-
pleted, true data is valid on all outputs and the next cycle may begin. DATA polling may
begin at any time during the program cycle.
3
0394E–FLASH–11/02
TOGGLE BIT: In addition to DATA polling the AT29C010A provides another method
for determining the end of a program or erase cycle. During a program or erase opera-
tion, successive attempts to read data from the device will result in I/O6 toggling
between one and zero. Once the program cycle has completed, I/O6 will stop toggling
and valid data will be read. Examining the toggle bit may begin at any time during a pro-
gram cycle.
OPTIONAL CHIP ERASE MODE: The entire device can be erased by using a 6-byte
software code. Please see Software Chip Erase application note for details.
BOOT BLOCK PROGRAMMING LOCKOUT: The AT29C010A has two designated
memory blocks that have a programming lockout feature. This feature prevents pro-
gramming of data in the designated block once the feature has been enabled. Each of
these blocks consists of 8K bytes; the programming lockout feature can be set indepen-
dently for either block. While the lockout feature does not have to be activated, it can be
activated for either or both blocks.
These two 8K memory sections are referred to as boot blocks. Secure code which will
bring up a system can be contained in a boot block. The AT29C010A blocks are located
in the first 8K bytes of memory and the last 8K bytes of memory. The boot block pro-
gramming lockout feature can therefore support systems that boot from the lower
addresses of memory or the higher addresses. Once the programming lockout feature
has been activated, the data in that block can no longer be erased or programmed; data
in other memory locations can still be changed through the regular programming meth-
ods. To activate the lockout feature, a series of seven program commands to specific
addresses with specific data must be performed. Please see Boot Block Lockout Fea-
ture Enable Algorithm.
If the boot block lockout feature has been activated on either block, the chip erase func-
tion will be disabled.
BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine
whether programming of either boot block section is locked out. See Software Product
Identification Entry and Exit sections. When the device is in the software product identifi-
cation mode, a read from location 00002 will show if programming the lower address
boot block is locked out while reading location 1FFF2 will do so for the upper boot block.
If the data is FE, the corresponding block can be programmed; if the data is FF, the pro-
gram lockout feature has been activated and the corresponding block cannot be pro-
grammed. The software product identification exit mode should be used to return to
standard operation.
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Temperature Under Bias................................ -55LC to +125LC
Storage Temperature..................................... -65LC to +150LC
All Input Voltages (including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on OE
with Respect to Ground...................................-0.6V to +13.5V
4
AT29C010A
0394E–FLASH–11/02
AT29C010A
DC and AC Operating Range
AT29C010A-70
AT29C010A-90
0LC - 70LC
AT29C010A-12
0LC - 70LC
AT29C010A-15
0LC - 70LC
Operating
Temperature (Case)
Com.
Ind.
0LC - 70LC
-40LC - 85LC
5VꢀMꢀ10%
-40LC - 85LC
5VꢀM 10%
-40LC - 85LC
5VꢀM 10%
VCC Power Supply
5VꢀMꢀ5%
Note:
Not recommended for New Designs.
Operating Modes
Mode
CE
VIL
VIL
VIL
VIH
X
OE
VIL
VIH
VIH
X(1)
X
WE
VIH
VIL
VIL
X
Ai
Ai
Ai
Ai
X
I/O
Read
DOUT
DIN
Program(2)
5V Chip Erase
Standby/Write Inhibit
Program Inhibit
Program Inhibit
Output Disable
Product Identification
Hardware
High Z
VIH
X
X
VIL
VIH
X
X
High Z
VIL
VIL
VIH
A1 - A16 = VIL, A9 = VH,(3) A0 = VIL
A1 - A16 = VIL, A9 = VH,(3) A0 = VIH
A0 = VIL
Manufacturer Code(4)
Device Code(4)
Software(5)
Manufacturer Code(4)
Device Code(4)
A0 = VIH
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V M 0.5V.
4. Manufacturer Code: 1F, Device Code: D5.
5. See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol
Parameter
Condition
Min
Max
10
Units
ꢁA
ꢁA
ꢁA
ꢁA
ꢁA
mA
mA
V
ILI
Input Load Current
Output Leakage Current
VCC Standby Current CMOS
VIN = 0V to VCC
VI/O = 0V to VCC
CE = VCC - 0.3V to VCC
ILO
10
ISB1
0° - 40°C
Com.
30
100
300
3
Ind.
ISB2
ICC
VCC Standby Current TTL
VCC Active Current
CE = 2.0V to VCC
f = 5 MHz; IOUT = 0 mA
50
VIL
Input Low Voltage
0.8
VIH
Input High Voltage
2.0
V
VOL
VOH1
VOH2
Output Low Voltage
Output High Voltage
Output High Voltage CMOS
IOL = 2.1 mA
0.45
V
IOH = -400 µA
2.4
4.2
V
IOH = -100 µA; VCC = 4.5V
V
5
0394E–FLASH–11/02
AC Read Characteristics
AT29C010A-70
AT29C010A-90
AT29C010A-12
AT29C010A-15
Symbol
Parameter
Min
Max
70
Min
Max
90
Min
Max
120
120
50
Min
Max
150
150
70
Units
ns
tACC
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
(1)
tCE
70
90
ns
(2)
tOE
0
0
0
35
0
0
0
40
0
0
0
0
0
0
ns
(3)(4)
tDF
25
25
30
40
ns
tOH
Output Hold from OE, CE or
ns
Address, whichever occurred first
Note:
Not recommended for New Designs.
AC Read Waveforms(1)(2)(3)(4)
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC
.
.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
6
AT29C010A
0394E–FLASH–11/02
AT29C010A
Input Test Waveforms and Measurement Level
tR, tF < 5 ns
Output Test Load
70 ns
90/120/150 ns
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
Typ
4
Max
6
Units
pF
Conditions
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. This parameter is canharacterized and is not 100% tested.
7
0394E–FLASH–11/02
AC Byte Load Characteristics
Symbol
Parameter
Min
0
Max
Units
ns
t
AS, tOES
Address, OE Set-up Time
Address Hold Time
tAH
tCS
tCH
tWP
tDS
50
0
ns
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
ns
0
ns
90
35
0
ns
ns
t
DH, tOEH
Data, OE Hold Time
Write Pulse Width High
ns
tWPH
100
ns
AC Byte Load Waveforms
WE Controlled
CE Controlled
8
AT29C010A
0394E–FLASH–11/02
AT29C010A
Program Cycle Characteristics
Symbol
Parameter
Min
Max
Units
ms
ns
tWC
Write Cycle Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
10
tAS
0
tAH
50
35
0
ns
tDS
ns
tDH
ns
tWP
Write Pulse Width
Byte Load Cycle Time
Write Pulse Width High
90
ns
tBLC
tWPH
150
ꢁs
100
ns
Program Cycle Waveforms(1)(2)(3)
Notes: 1. A7 through A16 must specify the sector address during each high to low transition of WE (or CE).
2. OE must be high when WE and CE are both low.
3. All bytes that are not loaded within the sector being programmed will be indeterminate.
9
0394E–FLASH–11/02
Software Data Protection Enable
Algorithm(1)
Software Data Protection Disable
Algorithm(1)
LOAD DATA AA
TO
LOAD DATA AA
TO
ADDRESS 5555
ADDRESS 5555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS 2AAA
ADDRESS 2AAA
LOAD DATA A0
TO
LOAD DATA 80
TO
ADDRESS 5555
WRITES ENABLED
ADDRESS 5555
LOAD DATA
TO
PAGE (128 BYTES)(4)
LOAD DATA AA
TO
ENTER DATA
PROTECT STATE(2)
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
Notes: 1. Data Format: I/O7 - I/O0 (Hex); Address Format:
A14 - A0 (Hex).
LOAD DATA 20
TO
2. Data Protect state will be activated at end of pro-
gram cycle.
3. Data Protect state will be deactivated at end of pro-
gram period.
ADDRESS 5555
EXIT DATA
PROTECT STATE(3)
4. 128 bytes of data MUST BE loaded.
LOAD DATA
TO
PAGE (128 BYTES)(4)
Software Protected Program Cycle Waveform(1)(2)(3)
Notes: 1. A7 through A16 must specify the sector address during each high to low transition of WE (or CE) after the software code
has been entered.
2. OE must be high when WE and CE are both low.
3. All bytes that are not loaded within the sector being programmed will be indeterminate.
10
AT29C010A
0394E–FLASH–11/02
AT29C010A
Data Polling Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
OE Hold Time
10
ns
OE to Output Delay(2)
Write Recovery Time
ns
tWR
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
Toggle Bit Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
OE Hold Time
tOEH
tOE
tOEHP
tWR
10
ns
OE to Output Delay(2)
ns
OE High Pulse
150
0
ns
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms(1)(2)(3)
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
11
0394E–FLASH–11/02
Software Product Identification
Entry(1)
Boot Block Lockout Feature Enable
Algorithm(1)
LOAD DATA AA
TO
LOAD DATA AA
TO
ADDRESS 5555
ADDRESS 5555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS 2AAA
ADDRESS 2AAA
LOAD DATA 90
TO
LOAD DATA 80
TO
ADDRESS 5555
ADDRESS 5555
LOAD DATA AA
TO
PAUSE 10 mS
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(5)
ADDRESS 5555
LOAD DATA 55
TO
Software Product Identification Exit(1)
ADDRESS 2AAA
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 40
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 00
TO
LOAD DATA FF
TO
ADDRESS 00000H(2)
ADDRESS 1FFFFH(3)
LOAD DATA F0
TO
ADDRESS 5555
PAUSE 20 mS
PAUSE 20 mS
PAUSE 10 mS
EXIT PRODUCT
IDENTIFICATION
MODE(4)
Notes: 1. Data Format: I/O7 - I/O0 (Hex); Address Format:
A14 - A0 (Hex).
2. Lockout feature set on lower address boot block.
3. Lockout feature set on higher address boot block.
Notes: 1. Data Format: I/O7 - I/O0 (Hex); Address Format:
A14 - A0 (Hex).
2. A1 - A15 = VIL.
Manufacturer Code is read for A0 = VIL; Device
Code is read for A0 = VIH.
3. The device does not remain in identification mode
if powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code is 1F. The Device Code is D5.
12
AT29C010A
0394E–FLASH–11/02
AT29C010A
NORMALIZED SUPPLY CURRENT
vs.TEMPERATURE
1.4
1.3
1.2
1.1
1.0
0.9
0.8
N
O
R
M
A
L
I
Z
E
D
I
C
C
-55
-25
5
35
65
95
125
TEMPERATURE (C)
NORMALIZED SUPPLY CURRENT
vs. ADDRESS FREQUENCY
1.1
1.0
0.9
0.8
0.7
N
O
R
M
A
L
I
Z
E
D
V
CC = 5V
T = 25C
I
C
C
0
1
2
3
4
5
6
7
FREQUENCY (MHz)
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
1.2
1.0
N
O
R
M
A
L
I
Z
E
D
0.8
0.6
I
C
C
4.50
4.75
5.00
5.25
5.50
SUPPLY VOLTAGE (V)
13
0394E–FLASH–11/02
Ordering Information
I
Active
50
CC (mA)
tACC
(ns)
Standby
Ordering Code
Package
Operation Range
70
0.1
0.1
0.3
0.1
0.3
0.1
0.3
AT29C010A-70JC
AT29C010A-70PC
AT29C010A-70TC
32J
Commercial
32P6
32T
(0L to 70LC)
90
50
50
50
50
50
50
AT29C010A-90JC
AT29C010A-90PC
AT29C010A-90TC
32J
Commercial
32P6
32T
(0L to 70LC)
AT29C010A-90JI
AT29C010A-90PI
AT29C010A-90TI
32J
Industrial
32P6
32T
(-40L to 85LC)
120
150
AT29C010A-12JC
AT29C010A-12PC
AT29C010A-12TC
32J
Commercial
32P6
32T
(0L to 70LC)
AT29C010A-12JI
AT29C010A-12PI
AT29C010A-12TI
32J
Industrial
32P6
32T
(-40L to 85LC)
AT29C010A-15JC
AT29C010A-15PC
AT29C010A-15TC
32J
Commercial
32P6
32T
(0L to 70LC)
AT29C010A-15JI
AT29C010A-15PI
AT29C010A-15TI
32J
Industrial
32P6
32T
(-40L to 85LC)
Note:
Not recommended for New Designs.
Package Type
32J
32-lead, Plastic J-leaded Chip Carrier (PLCC)
32-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
32-lead, Thin Small Outline Package (TSOP)
32P6
32T
14
AT29C010A
0394E–FLASH–11/02
AT29C010A
Packaging Information
32J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
IDENTIFIER
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
E2
E1
E
B1
B
e
A2
A1
D1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
3.175
1.524
0.381
12.319
11.354
9.906
14.859
13.894
12.471
0.660
0.330
MAX
3.556
2.413
–
NOM
NOTE
SYMBOL
A
–
D2
A1
A2
D
–
–
–
12.573
D1
D2
E
–
11.506 Note 2
10.922
–
Notes:
1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
–
15.113
E1
E2
B
–
14.046 Note 2
13.487
–
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
32J
B
R
15
0394E–FLASH–11/02
32P6 – PDIP
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
COMMON DIMENSIONS
(Unit of Measure = mm)
0º ~ 15º REF
C
MIN
–
MAX
4.826
–
NOM
NOTE
SYMBOL
A
–
eB
A1
D
0.381
41.783
15.240
13.462
0.356
1.041
3.048
0.203
15.494
–
–
42.291 Note 1
15.875
E
–
E1
B
–
13.970 Note 1
0.559
–
B1
L
–
1.651
Note:
1. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
–
3.556
C
–
–
0.381
eB
e
17.526
2.540 TYP
09/28/01
DRAWING NO. REV.
32P6
TITLE
2325 Orchard Parkway
San Jose, CA 95131
32P6, 32-lead (0.600"/15.24 mm Wide) Plastic Dual
Inline Package (PDIP)
B
R
16
AT29C010A
0394E–FLASH–11/02
AT29C010A
32T – TSOP
PIN 1
0º ~ 8º
c
Pin 1 Identifier
D1
D
L
b
L1
e
A2
E
GAGE PLANE
A
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
–
MAX
1.20
0.15
1.05
20.20
NOM
–
NOTE
SYMBOL
A
A1
A2
D
0.05
0.95
19.80
18.30
7.90
0.50
–
1.00
Notes:
1. This package conforms to JEDEC reference MO-142, Variation BD.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
20.00
18.40
8.00
D1
E
18.50 Note 2
8.10
0.70
Note 2
L
0.60
L1
b
0.25 BASIC
0.22
0.17
0.10
0.27
0.21
c
–
e
0.50 BASIC
10/18/01
DRAWING NO. REV.
32T
TITLE
2325 Orchard Parkway
San Jose, CA 95131
32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline
Package, Type I (TSOP)
B
R
17
0394E–FLASH–11/02
Atmel Headquarters
Atmel Operations
Corporate Headquarters
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 487-2600
Memory
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
TEL (49) 71-31-67-0
FAX (49) 71-31-67-2340
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 436-4314
Europe
Microcontrollers
Atmel Sarl
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 436-4314
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Colorado Springs, CO 80906
TEL 1(719) 576-3300
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
FAX 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
TEL (41) 26-426-5555
FAX (41) 26-426-5500
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BP 70602
44306 Nantes Cedex 3, France
TEL (33) 2-40-18-18-18
FAX (33) 2-40-18-19-60
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BP 123
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TEL (33) 4-76-58-30-00
FAX (33) 4-76-58-34-80
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Maxwell Building
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TEL (44) 1355-803-000
FAX (44) 1355-242-743
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
© Atmel Corporation 2002.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.
ATMEL® is the registered trademark of Atmel.
Other terms and product names may be the trademarks of others.
Printed on recycled paper.
0394E–FLASH–11/02
xM
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