AT29C010A [ATMEL]
1 Megabit 128K x 8 5-volt Only CMOS Flash Memory; 1兆位128K ×8 5伏只有CMOS闪存
| 型号： | AT29C010A |
| 厂家： | 
ATMEL |
| 描述： | 1 Megabit 128K x 8 5-volt Only CMOS Flash Memory |
| 文件： | 总12页 (文件大小：731K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AT29C010A
Features
Fast Read Access Time - 70 ns
5-Volt-Only Reprogramming
Sector Program Operation
•
•
•
Single Cycle Reprogram (Erase and Program)
1024 Sectors (128 bytes/sector)
Internal Address and Data Latches for 128-Bytes
Two 8 KB Boot Blocks with Lockout
Internal Program Control and Timer
Hardware and Software Data Protection
Fast Sector Program Cycle Time - 10 ms
DATA Polling for End of Program Detection
Low Power Dissipation
•
•
•
1 Megabit
(128K x 8)
5-volt Only
CMOS Flash
Memory
•
•
•
50 mA Active Current
100 µA CMOS Standby Current
Typical Endurance > 10,000 Cycles
Single 5V ±10% Supply
CMOS and TTL Compatible Inputs and Outputs
•
•
•
Commercial and Industrial Temperature Ranges
•
Description
The AT29C010A is a 5-volt-only in-system Flash programmable and erasable read
only memory (PEROM). Its 1 megabit of memory is organized as 131,072 words by 8
bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device
offers access times to 70 ns with power dissipation of just 275 mW over the commer-
cial temperature range. When the device is deselected, the CMOS standby current is
less than 100 µA. The device endurance is such that any sector can typically be writ-
ten to in excess of 10,000 times.
To allow for simple in-system reprogrammability, the AT29C010A does not require
high input voltages for programming. Five-volt-only commands determine the opera-
AT29C010A
(continued)
Pin Configurations
DIP Top View
Pin Name Function
A0 - A16
CE
Addresses
Chip Enable
Output Enable
Write Enable
OE
WE
I/O0 - I/O7 Data Inputs/Outputs
NC
No Connect
PLCC Top View
TSOP Top View
Type 1
0394B
4-129
Description (Continued)
tion of the device. Reading data out of the device is similar
to reading from an EPROM. Reprogramming the
AT29C010A is performed on a sector basis; 128-bytes of
data are loaded into the device and then simultaneously
programmed.
and data bus for other operations. Following the initiation
of a program cycle, the device will automatically erase the
sector and then program the latched data using an internal
control timer. The end of a program cycle can be detected
by DATA polling of I/O7. Once the end of a program cycle
has been detected, a new access for a read or program
can begin.
During a reprogram cycle, the address locations and 128-
bytes of data are internally latched, freeing the address
Block Diagram
Device Operation
be loaded in any order; sequential loading is not required.
Once a programming operation has been initiated, and for
READ: The AT29C010A is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-
line control gives designers flexibility in preventing bus
contention.
the duration of t , a read operation will effectively be a
WC
polling operation.
SOFTWARE DATA PROTECTION: A software control-
led data protection feature is available on the AT29C010A.
Once the software protection is enabled a software algo-
rithm must be issued to the device before a program may
be performed. The software protection feature may be en-
abled or disabled by the user; when shipped from Atmel,
the software data protection feature is disabled. To enable
the software data protection, a series of three program
commands to specific addresses with specific data must
be performed. After the software data protection is en-
abled the same three program commands must begin
each program cycle in order for the programs to occur. All
software program commands must obey the sector pro-
gram timing specifications. Once set, the software data
protection feature remains active unless its disable com-
mand is issued. Power transitions will not reset the soft-
ware data protection feature, however the software fea-
ture will guard against inadvertent program cycles during
power transitions.
BYTE LOAD: Byte loads are used to enter the 128-
bytes of a sector to be programmed or the software codes
for data protection. A byte load is performed by applying a
low pulse on the WE or CE input with CE or WE low (re-
spectively) and OE high. The address is latched on the
falling edge of CE or WE, whichever occurs last. The data
is latched by the first rising edge of CE or WE.
PROGRAM: The device is reprogrammed on a sector
basis. If a byte of data within a sector is to be changed,
data for the entire sector must be loaded into the device.
The data in any byte that is not loaded during the program-
ming of its sector will be indeterminate. Once the bytes of
a sector are loaded into the device, they are simultane-
ously programmed during the internal programming pe-
riod. After the first data byte has been loaded into the de-
vice, successive bytes are entered in the same manner.
Each new byte to be programmed must have its high to
low transition on WE (or CE) within 150 µs of the low to
high transition of WE (or CE) of the preceding byte. If a
high to low transition is not detected within 150 µs of the
last low to high transition, the load period will end and the
internal programming period will start. A7 to A16 specify
the sector address. The sector address must be valid dur-
ing each high to low transition of WE (or CE). A0 to A6
specify the byte address within the sector. The bytes may
Once set, software data protection will remain active un-
less the disable command sequence is issued.
After setting SDP, any attempt to write to the device with-
out the 3-byte command sequence will start the internal
write timers. No data will be written to the device; however,
for the duration of t , a read operation will effectively be
WC
a polling operation.
(continued)
4-130
AT29C010A
AT29C010A
Device Operation (Continued)
result in the complement of the loaded data on I/O7. Once
the program cycle has been completed, true data is valid
on all outputs and the next cycle may begin. DATA polling
may begin at any time during the program cycle.
After the software data protection’s 3-byte command code
is given, a byte load is performed by applying a low pulse
on the WE or CE input with CE or WE low (respectively)
and OE high. The address is latched on the falling edge of
CE or WE, whichever occurs last. The data is latched by
the first rising edge of CE or WE. The 128-bytes of data
must be loaded into each sector by the same procedure as
outlined in the program section under device operation.
TOGGLE BIT: In addition to DATA polling the
AT29C010A provides another method for determining the
end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from
the device will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will
stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT29C010A
in the following ways: (a) V sense— if V is below 3.8V
CC
CC
(typical), the program function is inhibited. (b) V power
CC
on delay— once V
has reached the V
sense level,
CC
CC
OPTIONAL CHIP ERASE MODE: The entire device
can be erased by using a 6-byte software code. Please
see Software Chip Erase application note for details.
the device will automatically time out 5 ms (typical) before
programming. (c) Program inhibit— holding any one of OE
low, CE high or WE high inhibits program cycles. (d) Noise
filter— pulses of less than 15 ns (typical) on the WE or CE
inputs will not initiate a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The
AT29C010A has two designated memory blocks that have
a programming lockout feature. This feature prevents pro-
gramming of data in the designated block once the feature
has been enabled. Each of these blocks consists of 8K
bytes; the programming lockout feature can be set inde-
pendently for either block. While the lockout feature does
not have to be activated, it can be activated for either or
both blocks.
PRODUCT IDENTIFICATION: The product identifica-
tion mode identifies the device and manufacturer as At-
mel. It may be accessed by hardware or software opera-
tion. The hardware operation mode can be used by an ex-
ternal programmer to identify the correct programming al-
gorithm for the Atmel product. In addition, users may wish
to use the software product identification mode to identify
the part (i.e. using the device code), and have the system
software use the appropriate sector size for program op-
erations. In this manner, the user can have a common
board design for 256K to 4-megabit densities and, with
each density’s sector size in a memory map, have the sys-
tem software apply the appropriate sector size.
These two 8K memory sections are referred to as boot
blocks. Secure code which will bring up a system can be
contained in a boot block. The AT29C010A blocks are lo-
cated in the first 8K bytes of memory and the last 8K bytes
of memory. The boot block programming lockout feature
can therefore support systems that boot from the lower
addresses of memory or the higher addresses. Once the
programming lockout feature has been activated, the data
in that block can no longer be erased or programmed;
data in other memory locations can still be changed
through the regular programming methods. To activate the
lockout feature, a series of seven program commands to
specific addresses with specific data must be performed.
Please see Boot Block Lockout Feature Enable Algorithm.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING: The AT29C010A features DATA poll-
ing to indicate the end of a program cycle. During a pro-
gram cycle an attempted read of the last byte loaded will
Absolute Maximum Ratings*
If the boot block lockout feature has been activated on
either block, the chip erase function will be disabled.
Temperature Under Bias................. -55°C to +125°C
Storage Temperature...................... -65°C to +150°C
(continued)
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
All Output Voltages
with Respect to Ground .............-0.6V to V + 0.6V
CC
Voltage on OE
with Respect to Ground ................... -0.6V to +13.5V
4-131
Device Operation (Continued)
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine whether programming of
either boot block section is locked out. See Software Prod-
uct Identification Entry and Exit sections. When the device
is in the software product identification mode, a read from
location 00002 will show if programming the lower address
boot block is locked out while reading location FFFF2 will
do so for the upper boot block. If the data is FE, the corre-
sponding block can be programmed; if the data is FF, the
program lockout feature has been activated and the corre-
sponding block cannot be programmed. The software
product identification exit mode should be used to return to
standard operation.
DC and AC Operating Range
AT29C010A-70
AT29C010A-90
0°C - 70°C
AT29C010A-12
0°C - 70°C
AT29C010A-15
0°C - 70°C
Com.
Ind.
0°C - 70°C
5V ± 5%
Operating
Temperature (Case)
-40°C - 85°C
5V ± 10%
-40°C - 85°C
5V ± 10%
-40°C - 85°C
5V ± 10%
V
CC
Power Supply
Operating Modes
Mode
CE
OE
WE
Ai
Ai
Ai
Ai
X
I/O
Read
V
V
V
V
V
IH
D
D
IL
IL
IL
IH
IL
IH
IH
OUT
IN
(2)
Program
V
V
V
V
IL
IL
5V Chip Erase
(1)
Standby/Write Inhibit
Program Inhibit
V
X
X
High Z
X
X
V
IH
Program Inhibit
X
X
V
X
IL
Output Disable
V
X
High Z
IH
Product Identification
A1 - A16 = VIL, A9 = VH, (3)
A0 = VIL
(4)
(4)
Manufacturer Code
Hardware
V
V
IL
V
IH
IL
A1 - A16 = VIL, A9 = VH, (3)
A0 = VIH
(4)
Device Code
A0 = VIL
A0 = VIH
Manufacturer Code
(5)
Software
(4)
Device Code
Notes: 1. X can be VIL or VIH.
4. Manufacturer Code: 1F, Device Code: D5
5. See details under Software Product Identification Entry/Exit.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
DC Characteristics
Symbol
Parameter
Condition
Min
Max
10
Units
µA
µA
µA
µA
mA
mA
V
I
LI
Input Load Current
Output Leakage Current
V
V
= 0V to V
CC
IN
I
LO
= 0V to V
CC
10
I/O
Com.
Ind.
100
300
3
I
V
Standby Current CMOS
CE = V - 0.3V to V
CC CC
SB1
CC
I
I
V
V
Standby Current TTL
Active Current
CE = 2.0V to V
CC
SB2
CC
CC
f = 5 MHz; I
= 0 mA
50
CC
OUT
V
V
V
V
V
Input Low Voltage
0.8
IL
Input High Voltage
2.0
V
IH
Output Low Voltage
Output High Voltage
Output High Voltage CMOS
I
= 2.1 mA
.45
V
OL
OH1
OH2
OL
OH
OH
I
I
= -400 µA
= -100 µA; V = 4.5V
2.4
4.2
V
V
CC
4-132
AT29C010A
AT29C010A
AC Read Characteristics
AT29C010A-70 AT29C010A-90 AT29C010A-12 AT29C010A-15
Min
Max
70
70
35
25
Min
Max
90
90
40
25
Min
Max
120
120
50
Min
Max
150
150
70
Symbol Parameter
Units
ns
t
t
t
t
Address to Output Delay
CE to Output Delay
ACC
(1)
ns
CE
OE
DF
(2)
OE to Output Delay
0
0
0
0
0
0
0
0
ns
(3, 4)
CE or OE to Output Float
30
40
ns
Output Hold from OE,
CE or Address,
t
0
0
0
0
ns
OH
whichever occurred first
AC Read Waveforms (1, 2, 3, 4)
Notes: 1. CE may be delayed up to tACC - tCE after the address
transition without impact on tACC
3. tDF is specified from OE or CE whichever occurs first
(CL = 5 pF).
.
2. OE may be delayed up to tCE - tOE after the falling
edge of CE without impact on tCE or by tACC - tOE
4. This parameter is characterized and is not 100% tested.
after an address change without impact on tACC
.
Output Test Load
Input Test Waveforms and
Measurement Level
70 ns
90/120/150 ns
t , t < 5 ns
R
F
Pin Capacitance (f = 1 MHz, T = 25°C) (1)
Typ
Max
6
Units
pF
Conditions
C
C
4
8
V
V
= 0V
IN
IN
12
pF
= 0V
OUT
OUT
Note: 1. This parameter is characterized and is not 100% tested.
4-133
AC Byte Load Characteristics
Symbol
Parameter
Min
0
Max
Units
ns
t
t
t
t
t
t
t
t
, t
Address, OE Set-up Time
Address Hold Time
AS OES
50
0
ns
AH
CS
CH
WP
DS
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
ns
0
ns
90
35
0
ns
ns
, t
Data, OE Hold Time
Write Pulse Width High
ns
DH OEH
100
ns
WPH
AC Byte Load Waveforms
WE Controlled
CE Controlled
4-134
AT29C010A
AT29C010A
Program Cycle Characteristics
Symbol
Parameter
Min
Max
Units
ms
ns
t
t
t
t
t
t
t
t
Write Cycle Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
10
WC
0
AS
50
35
0
ns
AH
ns
DS
ns
DH
Write Pulse Width
Byte Load Cycle Time
Write Pulse Width High
90
ns
WP
BLC
WPH
150
µs
100
ns
Program Cycle Waveforms (1, 2, 3)
3. All bytes that are not loaded within the sector being
Notes: 1. A7 through A16 must specify the sector address
during each high to low transition of WE (or CE).
2. OE must be high when WE and CE are both low.
programmed will be indeterminate.
4-135
Software Data
Software Data
Protection Disable Algorithm (1)
Protection Enable Algorithm (1)
LOAD DATA AA
TO
LOAD DATA AA
TO
ADDRESS 5555
ADDRESS 5555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS 2AAA
ADDRESS 2AAA
LOAD DATA 80
TO
LOAD DATA A0
TO
ADDRESS 5555
ADDRESS 5555
WRITES ENABLED
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA
TO
SECTOR (128 BYTES)
(4)
ENTER DATA
(2)
PROTECT STATE
LOAD DATA 55
TO
ADDRESS 2AAA
Notes for software program code:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
LOAD DATA 20
TO
ADDRESS 5555
2. Data Protect state will be activated at end of program cycle.
3. Data Protect state will be deactivated at end of
program period.
EXIT DATA
(3)
PROTECT STATE
4. 128-bytes of data MUST BE loaded.
LOAD DATA
TO
(4)
SECTOR (128 BYTES)
Software Protected Program Cycle Waveform (1, 2, 3)
Notes: 1. A7 through A16 must specify the sector address
during each high to low transition of WE (or CE)
after the software code has been entered.
2. OE must be high when WE and CE are both low.
3. All bytes that are not loaded within the sector being
programmed will be indeterminate.
4-136
AT29C010A
AT29C010A
Data Polling Characteristics (1)
Symbol
Parameter
Min
10
Typ
Max
Units
t
t
t
t
Data Hold Time
OE Hold Time
OE to Output Delay
ns
ns
ns
ns
DH
10
OEH
OE
(2)
Write Recovery Time
0
WR
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
Toggle Bit Characteristics (1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
t
t
t
t
t
Data Hold Time
OE Hold Time
OE to Output Delay
OE High Pulse
DH
10
ns
OEH
OE
(2)
ns
150
0
ns
OEHP
WR
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms (1, 2, 3)
3. Any address location may be used but the address
should not vary.
Notes: 1. Toggling either OE or CE or both OE and CE will
operate toggle bit.
2. Beginning and ending state of I/O6 will vary.
4-137
Software Product
Boot Block Lockout
Identification Entry (1)
Feature Enable Algorithm (1)
LOAD DATA AA
TO
LOAD DATA AA
TO
ADDRESS 5555
ADDRESS 5555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS 2AAA
ADDRESS 2AAA
LOAD DATA 90
TO
LOAD DATA 80
TO
ADDRESS 5555
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
PAUSE 10 mS
ENTER PRODUCT
IDENTIFICATION
(2, 3, 5)
MODE
LOAD DATA 55
TO
ADDRESS 2AAA
Software Product
LOAD DATA 40
TO
ADDRESS 5555
Identification Exit (1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 00
TO
LOAD DATA FF
TO
LOAD DATA 55
TO
ADDRESS 00000 (2)
ADDRESS FFFFF (3)
ADDRESS 2AAA
PAUSE 10 mS
PAUSE 10 mS
LOAD DATA F0
TO
ADDRESS 5555
Notes for boot block lockout feature enable:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Lockout feature set on lower address boot block.
3. Lockout feature set on higher address boot block.
PAUSE 10 mS
EXIT PRODUCT
IDENTIFICATION
(4)
MODE
Notes for software product identification:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A16 = VIL.
Manufacture Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 1F
Device Code: D5
4-138
AT29C010A
AT29C010A
4-139
t
I
(mA)
ACC
CC
Ordering Code
Package
Operation Range
(ns)
Active
Standby
70
50
0.1
0.1
0.3
0.1
0.3
0.1
0.3
AT29C010A-70JC
AT29C010A-70PC
AT29C010A-70TC
32J
32P6
32T
Commercial
(0° to 70°C)
90
50
50
50
50
50
50
AT29C010A-90JC
AT29C010A-90PC
AT29C010A-90TC
32J
32P6
32T
Commercial
(0° to 70°C)
AT29C010A-90JI
AT29C010A-90PI
AT29C010A-90TI
32J
32P6
32T
Industrial
(-40° to 85°C)
120
150
AT29C010A-12JC
AT29C010A-12PC
AT29C010A-12TC
32J
32P6
32T
Commercial
(0° to 70°C)
AT29C010A-12JI
AT29C010A-12PI
AT29C010A-12TI
32J
32P6
32T
Industrial
(-40° to 85°C)
AT29C010A-15JC
AT29C010A-15PC
AT29C010A-15TC
32J
32P6
32T
Commercial
(0° to 70°C)
AT29C010A-15JI
AT29C010A-15PI
AT29C010A-15TI
32J
32P6
32T
Industrial
(-40° to 85°C)
Package Type
32J
32 Lead, Plastic J-Leaded Chip Carrier (PLCC)
32 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
32 Lead, Thin Small Outline Package (TSOP)
32P6
32T
4-140
AT29C010A
相关型号：
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