AT32UC3A0128-ALUT [ATMEL]
AVR32 32-Bit Microcontroller; AVR32 32位微控制器
| 型号： | AT32UC3A0128-ALUT |
| 厂家： | 
ATMEL |
| 描述： | AVR32 32-Bit Microcontroller |
| 文件： | 总52页 (文件大小：660K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• High Performance, Low Power AVR®32 UC 32-Bit Microcontroller
– Compact Single-cycle RISC Instruction Set Including DSP Instruction Set
– Read-Modify-Write Instructions and Atomic Bit Manipulation
– Up to 66 MHz Clock Frequency with 1.24 DMIPS/MHz
– Memory Protection Unit
• Multi-hierarchy Bus System
– High-Performance Data Transfers on Separate Buses for Increased Performance
– 15 Peripheral DMA Channels for Automatic Data Transfer
• Internal High-Speed Flash
AVR®32
32-Bit
– 512K Bytes, 256K Bytes, 128K Bytes Versions
– Single Cycle Access up to 30 MHz
– Prefetch Buffer Optimizing Instruction Execution at Maximum Speed
– 1ms Page Programming Time and 2ms Full-Chip Erase Time
– 100,000 Write Cycles, 10-year Data Retention Capability
– Flash Security Locks and User Defined Configuration Area
• Internal High-Speed SRAM, Single-Cycle Access at Full Speed
– 64K Bytes (512KB and 256KB Flash), 32K Bytes (128KB Flash)
• External Memory Interface on AT32UC3A0 Derivatives
– SDRAM / SRAM Compatible Memory Bus (16-bit Data and 24-bit Address Buses)
• Interrupt Controller
Microcontroller
AT32UC3A0512
AT32UC3A0256
AT32UC3A0128
AT32UC3A1512
AT32UC3A1256
AT32UC3A1128
– Autovectored Low Latency Interrupt Service with Programmable Priority
• System Functions
– Power and Clock Manager Including Internal RC Clock and One 32KHz Oscillator
– Two Multipurpose Oscillators and Two Phase-Lock-Loop (PLL)
– Watchdog Timer, Real-Time Clock Timer
• Universal Serial Bus (USB)
– Device 2.0 Full Speed and On-The-Go (OTG) Low Speed and Full Speed
– Flexible End-Point Configuration and Management with Dedicated DMA Channels
– On-chip Transceivers Including Pull-Ups
Preliminary
Summary
• Ethernet MAC 10/100 Mbps interface
– 802.3 Ethernet Media Access Controller
– Supports Media Independent Interface (MII) and Reduced MII (RMII)
• One Three-Channel 16-bit Timer/Counter (TC)
– Three External Clock Inputs, PWM, Capture and Various Counting Capabilities
• One 7-Channel 16-bit Pulse Width Modulation Controller (PWM)
• Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART)
– Independant Baudrate Generator, Support for IrDA and ISO7816 interfaces
– Support for Hardware Handshaking, RS485 Interfaces and Modem Line
• Two Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals
• One Synchronous Serial Protocol Controller
– Supports I2S and Generic Frame-Based Protocols
• One Master/Slave Two-Wire Interface (TWI), 400kbit/s I2C-compatible
• One 8-channel 10-bit Analog-To-Digital Converter
• On-Chip Debug System (JTAG interface)
– Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace
• 100-pin TQFP (69 GPIO pins), 144-pin LQFP (109 GPIO pins)
• 5V Input Tolerant I/Os
• Single 3.3V Power Supply
32058AS–AVR32–03/07
1. Description
The AT32UC3A is a complete System-On-Chip microcontroller based on the AVR32 UC RISC
processor running at frequencies up to 66 MHz. AVR32 UC is a high-performance 32-bit RISC
microprocessor core, designed for cost-sensitive embedded applications, with particular empha-
sis on low power consumption, high code density and high performance.
The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt con-
troller for supporting modern operating systems and real-time operating systems. Higher
computation capabilities are achievable using a rich set of DSP instructions.
The AT32UC3A incorporates on-chip Flash and SRAM memories for secure and fast access.
For applications requiring additional memory, an external memory interface is provided on
AT32UC3A0 derivatives.
The Peripheral Direct Memory Access controller enables data transfers between peripherals and
memories without processor involvement. PDCA drastically reduces processing overhead when
transferring continuous and large data streams between modules within the MCU.
The PowerManager improves design flexibility and security: the on-chip Brown-Out Detector
monitors the power supply, the CPU runs from the on-chip RC oscillator or from one of external
oscillator sources, a Real-Time Clock and its associated timer keeps track of the time.
The Timer/Counter includes three identical 16-bit timer/counter channels. Each channel can be
independently programmed to perform frequency measurement, event counting, interval mea-
surement, pulse generation, delay timing and pulse width modulation.
The PWM modules provides seven independent channels with many configuration options
including polarity, edge alignment and waveform non overlap control. One PWM channel can
trigger ADC conversions for more accurate close loop control implementations.
The AT32UC3A also features many communication interfaces for communication intensive
applications. In addition to standard serial interfaces like UART, SPI or TWI, other interfaces like
flexible Synchronous Serial Controller, USB and Ethernet MAC are available.
The Synchronous Serial Controller provides easy access to serial communication protocols and
audio standards like I2S.
The Full-Speed USB 2.0 Device interface supports several USB Classes at the same time
thanks to the rich End-Point configuration. The On-The-GO (OTG) Host interface allows device
like a USB Flash disk or a USB printer to be directly connected to the processor.
The media-independent interface (MII) and reduced MII (RMII) 10/100 Ethernet MAC module
provides on-chip solutions for network-connected devices.
AT32UC3A integrates a class 2+ Nexus 2.0 On-Chip Debug (OCD) System, with non-intrusive
real-time trace, full-speed read/write memory access in addition to basic runtime control.
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32058AS–AVR32–03/07
2. Configuration Summary
The table below lists all AT32UC3A memory and package configurations:
Device
Flash
SRAM
Ext. Bus Interface Package
AT32UC3A0512
AT32UC3A1512
AT32UC3A0256
AT32UC3A1256
AT32UC3A0128
AT32UC3A1128
512 Kbytes
512 Kbytes
256 Kbytes
256 Kbytes
128 Kbytes
128 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
32 Kbytes
32 Kbytes
yes
no
144 lead LQFP
100 lead TQFP
144 lead LQFP
100 lead TQFP
144 lead LQFP
100 lead TQFP
yes
no
yes
no
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32058AS–AVR32–03/07
3. Blockdiagram
Figure 3-1. Blockdiagram
TCK
TDO
TDI
JTAG
INTERFACE
TMS
UC CPU
NEXUS
CLASS 2+
OCD
MCKO
MDO[5..0]
MSEO[1..0]
EVTI_N
MEMORY PROTECTION UNIT
INSTR
DATA
64 KB SRAM
EVTO_N
INTERFACE INTERFACE
VBUS
D+
D-
USB
INTERFACE
ID
VBOF
512 KB
FLASH
M
M
M
S
S
M
DMA
DMA
S
COL,
CRS,
RXD[3..0],
RX_CLK,
RX_DV,
RX_ER
M
HIGH SPEED
BUS MATRIX
DATA[15..0]
ADDR[23..0]
S
M
S
MDC,
TXD[3..0],
TX_CLK,
TX_EN,
TX_ER,
SPEED
NCS[3..0]
NRD
S
ETHERNET
MAC
NWAIT
NWE0
NWE1
NWE3
RAS
CONFIGURATION
REGISTERS BUS
HSB
PB
HSB
PERIPHERAL
DMA
CONTROLLER
HSB-PB
BRIDGE A
PB
HSB-PB
BRIDGE B
MDIO
CAS
SDA10
SDCK
SDCKE
SDCS1
SDWE
INTERRUPT
CONTROLLER
RXD
TXD
PA
PB
PC
PX
CLK
USART1
EXTERNAL
INTERRUPT
CONTROLLER
PA
PB
PC
PX
EXTINT[7..0]
KPS[7..0]
RTS, CTS
DSR, DTR, DCD, RI
NMI_N
RXD
TXD
CLK
USART0
USART2
REAL TIME
COUNTER
RTS, CTS
RXD
TXD
CLK
USART3
WATCHDOG
TIMER
SCK
SERIAL
PERIPHERAL
INTERFACE 0/1
MISO, MOSI
NPCS0
115 kHz
RCOSC
POWER
MANAGER
NPCS[3..1]
32 KHz
OSC
XIN32
XOUT32
TX_CLOCK, TX_FRAME_SYNC
TX_DATA
CLOCK
GENERATOR
SYNCHRONOUS
SERIAL
CONTROLLER
XIN0
RX_CLOCK, RX_FRAME_SYNC
RX_DATA
OSC0
OSC1
XOUT0
CLOCK
CONTROLLER
XIN1
XOUT1
SCL
SDA
TWO-WIRE
INTERFACE
SLEEP
CONTROLLER
PLL0
PLL1
RESET
CONTROLLER
PULSE WIDTH
MODULATION
CONTROLLER
GCLK[3..0]
RESET_N
PWM[6..0]
AD[7..0]
A[2..0]
B[2..0]
CLK[2..0]
TIMER/COUNTER
ANALOG TO
DIGITAL
ADVREF
CONVERTER
4
32058AS–AVR32–03/07
3.1
Processor and architecture
3.1.1
AVR32 UC CPU
• 32-bit load/store AVR32A RISC architecture.
– 15 general-purpose 32-bit registers.
– 32-bit Stack Pointer, Program Counter and Link Register reside in register file.
– Fully orthogonal instruction set.
– Privileged and unprivileged modes enabling efficient and secure Operating Systems.
– Innovative instruction set together with variable instruction length ensuring industry leading
code density.
– DSP extention with saturating arithmetic, and a wide variety of multiply instructions.
• 3 stage pipeline allows one instruction per clock cycle for most instructions.
– Byte, half-word, word and double word memory access.
– Multiple interrupt priority levels.
• MPU allows for operating systems with memory protection.
3.1.2
3.1.3
3.1.4
Debug and Test system
• IEEE1149.1 compliant JTAG and boundary scan
• Direct memory access and programming capabilities through JTAG interface
• Extensive On-Chip Debug features in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) Class 2+
– Low-cost NanoTrace supported.
• Auxiliary port for high-speed trace information
• Hardware support for 6 Program and 2 data breakpoints
• Unlimited number of software breakpoints supported
• Advanced Program, Data, Ownership, and Watchpoint trace supported
Peripheral DMA Controller
• Transfers from/to peripheral to/from any memory space without intervention of the processor.
• Next Pointer Support, forbids strong real-time constraints on buffer management.
• Fifteen channels
– Two for each USART
– Two for each Serial Synchronous Controller
– Two for each Serial Peripheral Interface
– One for each ADC
– Two for each TWI Interface
Bus system
• High Speed Bus (HSB) matrix with 6 Masters and 6 Slaves handled
– Handles Requests from the CPU Data Fetch, CPU Instruction Fetch, PDCA, USBB, Ethernet
Controller, CPU SAB, and to internal Flash, internal SRAM, Peripheral Bus A, Peripheral Bus
B, EBI.
– Round-Robin Arbitration (three modes supported: no default master, last accessed default
master, fixed default master)
– Burst Breaking with Slot Cycle Limit
– One Address Decoder Provided per Master
5
32058AS–AVR32–03/07
• Peripheral Bus A able to run on at divided bus speeds compared to the High Speed Bus
Figure 3-1 gives an overview of the bus system. All modules connected to the same bus use the
same clock, but the clock to each module can be individually shut off by the Power Manager.
The figure identifies the number of master and slave interfaces of each module connected to the
High Speed Bus, and which DMA controller is connected to which peripheral.
6
32058AS–AVR32–03/07
4. Signals Description
The following table gives details on the signal name classified by peripheral
The signals are multiplexed with GPIO pins as described in ”Peripheral Multiplexing on I/O lines”
on page 25.
Table 4-1.
Signal Description List
Active
Level
Signal Name
Function
Type
Comments
Power
VDDSYS
VDDCORE
VDDIO
Power supply for PLL and ADC
Core Power Supply
Power
Power
Power
Power
Power
1.65 to 1.95 V
1.65 to 1.95 V
3.0 to 3.6V
I/O Power Supply
VDDANA
VDDIN
Analog Power Supply
3.0 to 3.6V
Voltage Regulator Input Supply
3.0 to 3.6V
Power
Output
VDDOUT
Voltage Regulator Output
1.65 to 1.95 V
GNDANA
GND
Analog Ground
Ground
Ground
Ground
Clocks, Oscillators, and PLL’s
XIN0, XIN1, XIN32
Crystal 0, 1, 32 Input
Crystal 0, 1, 32 Output
Analog
XOUT0, XOUT1,
XOUT32
Analog
JTAG
Input
TCK
TDI
Test Clock
Test Data In
Input
TDO
TMS
Test Data Out
Test Mode Select
Output
Input
Auxiliary Port - AUX
Output
MCKO
Trace Data Output Clock
Trace Data Output
Trace Frame Control
Event In
MDO0 - MDO5
MSEO0 - MSEO1
EVTI_N
Output
Output
Output
Low
Low
EVTO_N
Event Out
Output
7
32058AS–AVR32–03/07
Table 4-1.
Signal Description List
Active
Level
Signal Name
Function
Type
Power Manager - PM
Comments
GCLK0 - GCLK3
RESET_N
Generic Clock Pins
Reset Pin
Output
Input
Low
Real Time Counter - RTC
Output
Watchdog Timer - WDT
RTC_CLOCK
WDTEXT
RTC clock
External Watchdog Pin
Output
External Interrupt Controller - EIC
EXTINT0 - EXTINT7
KPS0 - KPS7
NMI_N
External Interrupt Pins
Keypad Scan Pins
Input
Output
Non-Maskable Interrupt Pin
Input
Ethernet MAC - MACB
Low
COL
Collision Detect
Input
Input
Output
I/O
CRS
Carrier Sense and Data Valid
Management Data Clock
Management Data Input/Output
Receive Data
MDC
MDIO
RXD0 - RXD3
RX_CLK
RX_DV
RX_ER
SPEED
TXD0 - TXD3
TX_CLK
TX_EN
TX_ER
Input
Input
Input
Input
Receive Clock
Receive Data Valid
Receive Coding Error
Speed
Transmit Data
Output
Output
Output
Output
Transmit Clock or Reference Clock
Transmit Enable
Transmit Coding Error
External Bus Interface - HEBI - uC3015 Only
ADDR0 - ADDR23
CAS
Address Bus
Output
Column Signal
Output
Low
8
32058AS–AVR32–03/07
Table 4-1.
Signal Description List
Active
Level
Signal Name
Function
Type
I/O
Comments
DATA0 - DATA15
NCS0 - NCS3
NRD
Data Bus
Chip Select
Output
Output
Input
Low
Low
Low
Low
Low
Low
Low
Read Signal
NWAIT
External Wait Signal
Write Enable 0
NWE0
Output
Output
Output
Output
Output
Output
Output
Output
Output
NWE1
Write Enable 1
NWE3
Write Enable 3
RAS
Row Signal
SDA10
SDRAM Address 10 Line
SDRAM Clock
SDCK
SDCKE
SDCS0-SDCS1
SDWE
SDRAM Clock Enable
SDRAM Chip Select
SDRAM Write Enable
Low
Low
General Purpose Input/Output 2 - GPIOA, GPIOB, GPIOC
P0 - P31
P0 - P31
P0 - P5
Parallel I/O Controller GPIOA
I/O
I/O
I/O
I/O
Parallel I/O Controller GPIOB
Parallel I/O Controller GPIOC
Parallel I/O Controller GPIOX
P0 - P31
Serial Peripheral Interface - SPI0, SPI1
MISO
Master In Slave Out
Master Out Slave In
I/O
I/O
MOSI
NPCS0 - NPCS3
SCK
SPI Peripheral Chip Select
Clock
I/O
Low
Output
Synchronous Serial Controller - SSC
RX_CLOCK
SSC Receive Clock
SSC Receive Data
I/O
RX_DATA
Input
RX_FRAME_SYNC
TX_CLOCK
SSC Receive Frame Sync
SSC Transmit Clock
I/O
I/O
9
32058AS–AVR32–03/07
Table 4-1.
Signal Description List
Active
Level
Signal Name
Function
Type
Output
I/O
Comments
TX_DATA
SSC Transmit Data
TX_FRAME_SYNC
SSC Transmit Frame Sync
Timer/Counter - TIMER
A0
Channel 0 Line A
I/O
I/O
A1
Channel 1 Line A
A2
Channel 2 Line A
I/O
B0
Channel 0 Line B
I/O
B1
Channel 1 Line B
I/O
B2
Channel 2 Line B
I/O
CLK0
CLK1
CLK2
Channel 0 External Clock Input
Channel 1 External Clock Input
Channel 2 External Clock Input
Input
Input
Input
Two-wire Interface - TWI
SCL
SDA
Serial Clock
Serial Data
I/O
I/O
Universal Synchronous Asynchronous Receiver Transmitter - USART0, USART1, USART2, USART3
CLK
CTS
DCD
DSR
DTR
RI
Clock
I/O
Clear To Send
Input
Only USART0, USART1
Only USART0
Data Carrier Detect
Data Set Ready
Data Terminal Ready
Ring Indicator
Only USART0
Only USART0
Only USART0
RTS
RXD
RXDN
TXD
TXDN
Request To Send
Receive Data
Output
Only USART0, USART1
Input
Inverted Receive Data
Transmit Data
Input
Low
Low
Output
Output
Inverted Transmit Data
Analog to Digital Converter - ADC
10
32058AS–AVR32–03/07
Table 4-1.
Signal Description List
Active
Level
Signal Name
Function
Type
Comments
Analog
input
AD0 - AD7
Analog input pins
Analog
input
ADVREF
Analog positive reference voltage input
2.6 to 3.6V
Pulse Width Modulator - PWM
PWM0 - PWM6
PWM Output Pins
Output
Universal Serial Bus Device - USB
DDM
DDP
USB Device Port Data -
USB Device Port Data +
Analog
Analog
11
32058AS–AVR32–03/07
5. Package and Pinout
The device pins are multiplexed with peripheral functions as described in ”Peripheral Multiplexing on I/O lines” on page 25.
Figure 5-1. TQFP100 Pinout
75
51
76
50
26
100
1
25
Table 5-1.
TQFP100 Package Pinout
1
2
PB20
PB21
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
PA05
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PA21
PA22
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
PB08
PB09
PB10
VDDIO
GND
PA06
PA07
3
PB22
PA23
4
VDDIO
GND
PA08
PA24
5
PA09
PA25
6
PB23
PA10
PA26
PB11
PB12
PA29
PA31
PC02
PC03
PB13
PB14
TMS
7
PB24
N/C
PA27
8
PB25
PA11
PA28
9
PB26
VDDCORE
GND
VDDANA
ADVREF
GNDANA
VDDSYS
PC00
10
11
12
13
14
15
16
17
18
19
20
21
22
PB27
VDDOUT
VDDIN
GND
PA12
PA13
VDDCORE
PA14
PB28
PC01
PB29
PA15
PB00
TCK
PB30
PA16
PB01
TDO
PB31
PA17
VDDIO
VDDIO
GND
TDI
RESET_N
PA00
PA18
PC04
PC05
PB15
PB16
VDDCORE
PA19
PA01
PA20
PB02
GND
VBUS
VDDIO
PB03
VDDCORE
PB04
12
32058AS–AVR32–03/07
Table 5-1.
TQFP100 Package Pinout
23
24
25
PA02
PA03
PA04
48
49
50
DM
DP
73
74
75
PB05
PB06
PB07
98
99
PB17
PB18
PB19
GND
100
Figure 5-2. LQFP144 Pinout
108
73
109
72
37
144
1
36
Table 5-2.
VQFP144 Package Pinout
1
2
PX00
PX01
PB20
PX02
PB21
PB22
VDDIO
GND
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
GND
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
PA21
PA22
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
GND
PX30
PB08
PX31
PB09
PX32
PB10
VDDIO
GND
PX33
PB11
PX34
PB12
PA29
PA31
PC02
PC03
PB13
PB14
TMS
PX10
PA05
3
PA23
4
PX11
PA06
PA24
5
PA25
6
PX12
PA07
PA26
7
PA27
8
PX13
PA08
PA28
9
PB23
PX03
PB24
PX04
PB25
PB26
PB27
VDDOUT
VDDIN
GND
VDDANA
ADVREF
GNDANA
VDDSYS
PC00
10
11
12
13
14
15
16
17
18
19
20
21
PX14
PA09
PA10
N/C
PA11
PC01
VDDCORE
GND
PX20
PB00
PA12
PX21
PA13
PB01
PB28
PB29
PB30
VDDCORE
PA14
PX22
VDDIO
VDDIO
PA15
TCK
13
32058AS–AVR32–03/07
Table 5-2.
VQFP144 Package Pinout
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PB31
RESET_N
PX05
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PA16
PX15
PA17
PX16
PA18
PX17
PA19
PX18
PA20
PX19
VBUS
VDDIO
DM
94
95
GND
PX23
PB02
PX24
PB03
PX25
PB04
PX26
PB05
PX27
PB06
PX28
PB07
PX29
VDDIO
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
TDO
TDI
96
PC04
PC05
PB15
PX35
PB16
PX36
VDDCORE
PB17
PX37
PB18
PX38
PB19
PX39
PA00
97
PX06
98
PA01
99
GND
100
101
102
103
104
105
106
107
108
VDDCORE
PA02
PX07
PA03
PX08
PA04
PX09
DP
VDDIO
GND
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32058AS–AVR32–03/07
6. Power Considerations
6.1
Power Supplies
The AT32UC3A has several types of power supply pins:
• VDDIO: Powers I/O lines. Voltage is 3.3V nominal.
• VDDANA: Powers the ADC Voltage is 3.3V nominal.
• VDDIN: Input voltage for the voltage regulator. Voltage is 3.3V nominal.
• VDDCORE: Powers the core, memories, and peripherals. Voltage is 1.8V nominal.
• VDDSYS: Powers the PLL and ADC. Voltage is 1.8V nominal.
The ground pins GND are common to VDDCORE and VDDIO. The ground pin for VDDANA and
VDDSYS is GNDANA.
See ”Electrical Characteristics” on page 33 for power consumption on the various supply pins.
6.2
Voltage Regulator
The AT32UC3A embeds a voltage regulator that converts from 3.3V to 1.8V with a load of up to
100 mA. The regulator takes its input voltage from VDDIN, and supplies the output voltage on
VDDOUT. VDDOUT should be externally connected to the 1.8V domains to be powered.
Adequate output supply decoupling is mandatory for VDDOUT to reduce ripple and avoid oscil-
lations. The best way to achieve this is to use two capacitors in parallel: one external 470 pF (or
1 nF) NPO capacitor should be connected between VDDOUT and GND as close to the chip as
possible. One external 2.2 µF (or 3.3 µF) X7R capacitor should be connected between VDDOUT
and GND.
Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability
and reduce source voltage drop. The input decoupling capacitor should be placed close to the
chip. For example, two capacitors can be used in parallel: 100 nF NPO and 4.7 µF X7R.
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32058AS–AVR32–03/07
7. I/O Line Considerations
7.1
JTAG pins
TMS, TDI and TCK have pull-up resistors. TDO is an output, driven at up to VDDIO, and has no
pull-up resistor.
7.2
RESET_N pin
The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIO. As
the product integrates a power-on reset cell, the RESET_N pin can be left unconnected in case
no reset from the system needs to be applied to the product.
7.3
7.4
TWI pins
When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and
inputs with inputs with spike-filtering. When used as GPIO-pins or used for other peripherals, the
pins have the same characteristics as PIO pins.
GPIO pins
All the I/O lines integrate a programmable pull-up resistor. Programming of this pull-up resistor is
performed independently for each I/O line through the GPIO Controllers. After reset, I/O lines
default as inputs with pull-up resistors disabled, except when indicated otherwise in the column
“Reset State” of the GPIO Controller multiplexing tables.
16
32058AS–AVR32–03/07
8. Memories
8.1
Embedded Memories
• Internal High-Speed Flash
– 512 KBytes (AT32UC3A0512, AT32UC3A1512)
– 256 KBytes (AT32UC3A0256, AT32UC3A1256)
– 128 KBytes (AT32UC3A1128)
- 0 Wait State Access at up to 30 MHz in Worst Case Conditions
- 1 Wait State Access at up to 60 MHz in Worst Case Conditions
- Pipelined Flash Architecture, allowing burst reads from sequential Flash locations, hiding
penalty of 1 wait state access
- Pipelined Flash Architecture typically reduces the cycle penalty of 1 wait state operation
to only 15% compared to 0 wait state operation
- 10 000 Write Cycles, 10-year Data Retention Capability
- 1 ms Page Programming Time, 2 ms Chip Erase Time
- Sector Lock Capabilities, Bootloader Protection, Security Bit
- 64 Fuses, 32 Of Which Are Preserved During Chip Erase
- User Page For Data To Be Preserved During Chip Erase
• Internal High-Speed SRAM, Single-cycle access at full speed
– 64 KBytes (AT32UC3A0512, AT32UC3A0, AT32UC3A0256 & AT32UC3A1256)
– 32KBytes (AT32UC3A1128)
8.2
Physical Memory Map
The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they
are never remapped in any way, not even in boot. Note that AVR32 UC CPU uses unsegmented
translation, as described in the AVR32 Architecture Manual. The 32-bit physical address space
is mapped as follows:
Table 8-1.
AT32UC3A Physical Memory Map
Size
Start Address
Device
AT32UC3A0512
64 Kbyte
AT32UC3A1512
AT32UC3A0256
64 Kbyte
256 Kbyte
16 Mbyte
16 Mbyte
16 Mbyte
128 Mbyte
64 Kbyte
64 Kbyte
64 kByte
AT32UC3A1256
AT32UC3A1128
0x0000_0000
0x8000_0000
0xC000_0000
0xC800_0000
0xCC00_0000
0xD000_0000
0xE000_0000
0xFFFE_0000
0xFFFF_0000
64 Kbyte
64 Kbyte
32 Kbyte
Embedded SRAM
Embedded Flash
EBI SRAM CS0
512 Kbyte
16 Mbyte
16 Mbyte
16 Mbyte
128 Mbyte
64 Kbyte
64 Kbyte
64 Kbyte
512 Kbyte
256 Kbyte
128 Kbyte
-
-
-
-
-
-
EBI SRAM CS2
-
-
-
EBI SRAM CS3
-
-
-
EBI SRAM/SDRAM CS1
USB Configuration
HSB-PB Bridge A
HSB-PB Bridge B
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 kByte
64 Kbyte
64 Kbyte
64 Kbyte
Accesses to unused areas returns an error result to the master requesting such an access.
The bus matrix has the several masters and slaves. Each master has its own bus and its own
decoder, thus allowing a different memory mapping per master. The master number in the table
17
32058AS–AVR32–03/07
below can be used to index the HMATRIX control registers. For example, MCFG0 is associated
with the CPU Data master interface.
Table 8-2.
Master 0
Master 1
Master 2
Master 3
Master 4
Master 5
High Speed Bus masters
CPU Data
CPU Instruction
CPU SAB
PDCA
MACB DMA
USBB DMA
Each slave has its own arbiter, thus allowing a different arbitration per slave. The slave number
in the table below can be used to index the HMATRIX control registers. For example, SCFG3 is
associated with the Internal SRAM Slave Interface.
Table 8-3.
Slave 0
Slave 1
Slave 2
Slave 3
Slave 4
Slave 5
High Speed Bus slaves
Internal Flash
HSB-PB Bridge 0
HSB-PB Bridge 1
Internal SRAM Slave
USBB Slave
EBI
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32058AS–AVR32–03/07
9. Peripherals
9.1
Peripheral address map
Table 9-1.
Peripheral Address Mapping
Address
Peripheral Name
Bus
0xE0000000
USBB
USBB Slave Interface - USBB
HSB
PBB
PBB
PBB
PBB
PBB
PBB
PBA
PBA
PBA
PBA
PBA
PBA
PBA
PBA
PBA
0xFFFE0000
0xFFFE1000
0xFFFE1400
0xFFFE1800
0xFFFE1C00
0xFFFE2000
0xFFFF0000
0xFFFF0800
0xFFFF0C00
0xFFFF0D00
0xFFFF0D30
0xFFFF0D80
0xFFFF1000
0xFFFF1400
0xFFFF1800
USBB
HMATRIX
FLASHC
MACB
SMC
USBB Configuration Interface - USBB
HMATRIX Configuration Interface - HMATRIX
Flash Controller - FLASHC
MACB Configuration Interface - MACB
Static Memory Controller Configuration Interface -
SMC
SDRAM Controller Configuration Interface -
SDRAMC
SDRAMC
PDCA
INTC
Peripheral DMA Interface - PDCA
Interrupt Controller Interface - INTC
Power Manager - PM
PM
RTC
Real Time Clock - RTC
WDT
WatchDog Timer - WDT
EIC
External Interrupt Controller - EIC
General Purpose IO Controller - GPIO
GPIO
Universal Synchronous Asynchronous Receiver
Transmitter - USART0
USART0
USART1
Universal Synchronous Asynchronous Receiver
Transmitter - USART1
19
32058AS–AVR32–03/07
Table 9-1.
Peripheral Address Mapping (Continued)
Address
Peripheral Name
Bus
0xFFFF1C00
Universal Synchronous Asynchronous Receiver
Transmitter - USART2
USART2
PBA
PBA
PBA
PBA
PBA
PBA
PBA
PBA
PBA
0xFFFF2000
Universal Synchronous Asynchronous Receiver
Transmitter - USART3
USART3
0xFFFF2400
SPI0
Serial Peripheral Interface - SPI0
Serial Peripheral Interface - SPI1
Two Wire Interface - TWI
0xFFFF2800
SPI1
0xFFFF2C00
TWI
0xFFFF3000
PWM
Pulse Width Modulation Controller - PWM
Synchronous Serial Controller - SSC
Timer/Counter - TC
0xFFFF3400
SSC
0xFFFF3800
TC
0xFFFF3C00
ADC
Analog To Digital Converter - ADC
9.2
Interrupt Request Signal Map
The various modules may output Interrupt request signals. These signals are routed to the Inter-
rupt Controller (INTC), described in a later chapter. The Interrupt Controller supports up to 64
groups of interrupt requests. Each group can have up to 32 interrupt request signals. All interrupt
signals in the same group share the same autovector address and priority level. Refer to the
documentation for the individual submodules for a description of the semantic of the different
interrupt requests.
The interrupt request signals are connected to the INTC as follows.
Table 9-2.
Group
0
Interrupt Request Signal Map
Line
Module
Signal
0
Peripheral DMA Controller
PDCA 16
20
32058AS–AVR32–03/07
Table 9-2.
Interrupt Request Signal Map
0
1
External Interrupt Controller
EIC 0
EIC 1
External Interrupt Controller
2
External Interrupt Controller
EIC 2
3
External Interrupt Controller
EIC 3
4
External Interrupt Controller
EIC 4
1
5
External Interrupt Controller
EIC 5
6
External Interrupt Controller
EIC 6
7
External Interrupt Controller
EIC 7
8
Real Time Counter
RTC
9
Power Manager
PM
0
General Purpose Input/Output Controller
General Purpose Input/Output Controller
General Purpose Input/Output Controller
General Purpose Input/Output Controller
General Purpose Input/Output Controller
General Purpose Input/Output Controller
General Purpose Input/Output Controller
General Purpose Input/Output Controller
General Purpose Input/Output Controller
General Purpose Input/Output Controller
General Purpose Input/Output Controller
General Purpose Input/Output Controller
General Purpose Input/Output Controller
General Purpose Input/Output Controller
GPIO 0
GPIO 1
GPIO 2
GPIO 3
GPIO 4
GPIO 5
GPIO 6
GPIO 7
GPIO 8
GPIO 9
GPIO 10
GPIO 11
GPIO 12
GPIO 13
1
2
3
4
5
6
2
7
8
9
10
11
12
13
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32058AS–AVR32–03/07
Table 9-2.
Interrupt Request Signal Map
0
1
Peripheral DMA Controller
PDCA 0
PDCA 1
PDCA 2
PDCA 3
PDCA 4
PDCA 5
PDCA 6
PDCA 7
PDCA 8
PDCA 9
PDCA 10
PDCA 11
PDCA 12
PDCA 13
PDCA 14
FLASHC
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Flash Controller
2
3
4
5
6
3
7
8
9
10
11
12
13
14
0
4
5
Universal Synchronous Asynchronous
Receiver Transmitter
0
0
0
0
USART0
USART1
USART2
USART3
Universal Synchronous Asynchronous
Receiver Transmitter
6
7
8
Universal Synchronous Asynchronous
Receiver Transmitter
Universal Synchronous Asynchronous
Receiver Transmitter
9
0
0
0
0
0
0
1
2
0
0
0
0
Serial Peripheral Interface
Serial Peripheral Interface
Two-wire Interface
SPI0
SPI1
10
11
12
13
TWI
Pulse Width Modulation Controller
Synchronous Serial Controller
Timer/Counter
PWM
SSC
TC0
14
Timer/Counter
TC1
Timer/Counter
TC2
15
16
17
18
Analog to Digital Converter
Ethernet MAC
ADC
MACB
USBB
SDRAMC
USB Interface
SDRAM Controller
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32058AS–AVR32–03/07
9.3
Clock Connections
9.3.1
Timer/Counters
Each Timer/Counter channel can independently select an internal or external clock source for its
counter:
Table 9-3.
Source
Timer/Counter clock connections
Name
Connection
Internal
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
XC0
clk_slow
clk_pba / 4
clk_pba / 8
clk_pba / 16
clk_pba / 32
See Section 9.6
External
XC1
XC2
9.3.2
USARTs
Each USART can be connected to an internally divided clock:
Table 9-4.
USART clock connections
USART
Source
Name
Connection
0
1
2
3
Internal
CLK_DIV
clk_pba / 8
9.3.3
SPIs
Each SPI can be connected to an internally divided clock:
Table 9-5.
SPI clock connections
SPI
0
Source
Name
CLK_DIV
Connection
Internal
clk_pba / 32
1
9.4
Nexus OCD AUX port connections
If the OCD trace system is enabled, the trace system will take control over a number of pins, irre-
spectively of the PIO configuration. Two different OCD trace pin mappings are possible,
23
32058AS–AVR32–03/07
depending on the configuration of the OCD AXS register. For details, see the AVR32 UCTechni-
cal Reference Manual.
Table 9-6.
Pin
Nexus OCD AUX port connections
AXS=0
PB19
PB16
PB14
PB13
PB12
PB11
PB10
PB20
PB21
PB04
PB17
AXS=1
PA08
PA27
PA26
PA25
PA24
PA23
PA22
PB20
PA21
PA07
PA28
EVTI_N
MDO[5]
MDO[4]
MDO[3]
MDO[2]
MDO[1]
MDO[0]
EVTO_N
MCKO
MSEO[1]
MSEO[0]
9.5
DMA handshake signals
The PDMA and the peripheral modules communicate through a set of handshake signals. The
following table defines the valid settings for the Peripheral Identifier (PID) in the PDMA Periph-
eral Select Register (PSR).
Table 9-7.
PDMA Handshake Signals
Peripheral module & direction
ADC
PID Value
0
1
SSC - RX
2
USART0 - RX
USART1 - RX
USART2 - RX
USART3 - RX
TWI - RX
3
4
5
6
7
SPI0 - RX
8
SPI1 - RX
9
SSC - TX
10
11
12
13
USART0 - TX
USART1 - TX
USART2 - TX
USART3 - TX
24
32058AS–AVR32–03/07
Table 9-7.
PDMA Handshake Signals
Peripheral module & direction
TWI - TX
PID Value
14
15
16
SPI0 - TX
SPI1 - TX
9.6
Peripheral Multiplexing on I/O lines
Each GPIO line can be assigned to one of 3 peripheral functions; A, B or C. The following table
define how the I/O lines on the peripherals A, B and C are multiplexed by the GPIO.
Table 9-8.
GPIO Controller Function Multiplexing
TQFP100
19
VQFP144
25
PIN
GPIO Pin
GPIO 0
GPIO 1
GPIO 2
GPIO 3
GPIO 4
GPIO 5
GPIO 6
GPIO 7
GPIO 8
GPIO 9
GPIO 10
GPIO 11
GPIO 12
GPIO 13
Function A
Function B
TC - CLK0
Function C
PA00
PA01
PA02
PA03
PA04
PA05
PA06
PA07
PA08
PA09
PA10
PA11
PA12
PA13
USART0 - RXD
USART0 - TXD
USART0 - CLK
USART0 - RTS
USART0 - CTS
USART1 - RXD
USART1 - TXD
USART1 - CLK
USART1 - RTS
USART1 - CTS
SPI0 - NPCS[0]
SPI0 - MISO
20
27
TC - CLK1
23
30
TC - CLK2
24
32
EIC - EXTINT[4]
EIC - EXTINT[5]
PWM - PWM[4]
PWM - PWM[5]
PM - GCLK[0]
SPI0 - NPCS[1]
SPI0 - NPCS[2]
EIC - EXTINT[6]
USBB - USB_ID
USBB - USB_VBOF
25
34
26
39
27
41
28
43
SPI0 - NPCS[3]
EIC - EXTINT[7]
29
45
30
47
31
48
33
50
36
53
SPI0 - MOSI
37
54
SPI0 - SCK
SSC -
TX_FRAME_SYNC
39
56
PA14
GPIO 14
SPI1 - NPCS[0]
EBI - NCS[0]
40
41
42
43
57
58
60
62
PA15
PA16
PA17
PA18
GPIO 15
GPIO 16
GPIO 17
GPIO 18
SSC - TX_CLOCK
SSC - TX_DATA
SSC - RX_DATA
SSC - RX_CLOCK
SPI1 - SCK
SPI1 - MOSI
SPI1 - MISO
SPI1 - NPCS[1]
EBI - ADDR[20]
EBI - ADDR[21]
EBI - ADDR[22]
SSC -
RX_FRAME_SYNC
44
64
PA19
GPIO 19
SPI1 - NPCS[2]
45
51
52
53
54
55
56
66
73
74
75
76
77
78
PA20
PA21
PA22
PA23
PA24
PA25
PA26
GPIO 20
GPIO 21
GPIO 22
GPIO 23
GPIO 24
GPIO 25
GPIO 26
NMI
SPI1 - NPCS[3]
EIC - EXTINT[0]
EIC - EXTINT[1]
EIC - EXTINT[2]
EIC - EXTINT[3]
EIC - SCAN[0]
EIC - SCAN[1]
ADC - AD[0]
ADC - AD[1]
ADC - AD[2]
ADC - AD[3]
ADC - AD[4]
ADC - AD[5]
EBI - NCS[0]
EBI - ADDR[20]
25
32058AS–AVR32–03/07
Table 9-8.
GPIO Controller Function Multiplexing
57
58
83
84
65
66
70
71
72
73
74
75
76
77
78
81
82
87
88
95
96
98
99
100
1
79
80
PA27
PA28
PA29
PA30
PB00
PB01
PB02
PB03
PB04
PB05
PB06
PB07
PB08
PB09
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
PC00
PC01
PC02
GPIO 27
GPIO 28
GPIO 29
GPIO 30
GPIO 32
GPIO 33
GPIO 34
GPIO 35
GPIO 36
GPIO 37
GPIO 38
GPIO 39
GPIO 40
GPIO 41
GPIO 42
GPIO 43
GPIO 44
GPIO 45
GPIO 46
GPIO 47
GPIO 48
GPIO 49
GPIO 50
GPIO 51
GPIO 52
GPIO 53
GPIO 54
GPIO 55
GPIO 56
GPIO 57
GPIO 58
GPIO 59
GPIO 60
GPIO 61
GPIO 62
GPIO 63
GPIO 64
GPIO 65
GPIO 66
ADC - AD[6]
ADC - AD[7]
EIC - SCAN[2]
EIC - SCAN[3]
USART2 - RTS
USART2 - CTS
USART2 - RTS
USART2 - CTS
EBI - ADDR[21]
EBI - ADDR[22]
122
123
88
TWI - SDA
TWI - SCL
MACB - TX_CLK
MACB - TX_EN
MACB - TXD[0]
MACB - TXD[1]
MACB - CRS
MACB - RXD[0]
MACB - RXD[1]
MACB - RX_ER
MACB - MDC
MACB - MDIO
MACB - TXD[2]
MACB - TXD[3]
MACB - TX_ER
MACB - RXD[2]
MACB - RXD[3]
MACB - RX_DV
MACB - COL
MACB - RX_CLK
MACB - SPEED
PWM - PWM[0]
PWM - PWM[1]
PWM - PWM[2]
PWM - PWM[3]
TC - A0
90
96
98
100
102
104
106
111
113
115
119
121
126
127
134
136
139
141
143
3
USART3 - CLK
EBI - NCS[3]
USART3 - RXD
USART3 - TXD
TC - CLK0
EBI - SDCK
EBI - SDCKE
EBI - RAS
TC - CLK1
EBI - CAS
TC - CLK2
EBI - SDWE
USBB - USB_ID
USBB - USB_VBOF
ADC - TRIGGER
PM - GCLK[0]
PM - GCLK[1]
PM - GCLK[2]
PM - GCLK[3]
USART1 - DCD
USART1 - DSR
USART1 - DTR
USART1 - RI
EBI - SDA10
EBI - ADDR[23]
PWM - PWM[6]
EIC - SCAN[4]
EIC - SCAN[5]
EIC - SCAN[6]
EIC - SCAN[7]
2
5
3
6
6
9
7
11
TC - B0
8
13
TC - A1
9
14
TC - B1
10
14
15
16
17
63
64
85
15
TC - A2
PWM - PWM[4]
PWM - PWM[5]
PM - GCLK[1]
PM - GCLK[2]
PM - GCLK[3]
19
TC - B2
20
USART2 - RXD
USART2 - TXD
USART2 - CLK
EBI - NCS[2]
EBI - SDCS
EBI - NWAIT
21
22
85
86
124
26
32058AS–AVR32–03/07
Table 9-8.
GPIO Controller Function Multiplexing
86
93
94
125
132
133
1
PC03
PC04
PC05
PX00
PX01
PX02
PX03
PX04
PX05
PX06
PX07
PX08
PX09
PX10
PX11
PX12
PX13
PX14
PX15
PX16
PX17
PX18
PX19
PX20
PX21
PX22
PX23
PX24
PX25
PX26
PX27
PX28
PX29
PX30
PX31
PX32
PX33
PX34
PX35
GPIO 67
GPIO 68
GPIO 69
GPIO 100
GPIO 99
GPIO 98
GPIO 97
GPIO 96
GPIO 95
GPIO 94
GPIO 93
GPIO 92
GPIO 91
GPIO 90
GPIO 109
GPIO 108
GPIO 107
GPIO 106
GPIO 89
GPIO 88
GPIO 87
GPIO 86
GPIO 85
GPIO 84
GPIO 83
GPIO 82
GPIO 81
GPIO 80
GPIO 79
GPIO 78
GPIO 77
GPIO 76
GPIO 75
GPIO 74
GPIO 73
GPIO 72
GPIO 71
GPIO 70
GPIO 105
EBI - DATA[10]
EBI - DATA[9]
EBI - DATA[8]
EBI - DATA[7]
EBI - DATA[6]
EBI - DATA[5]
EBI - DATA[4]
EBI - DATA[3]
EBI - DATA[2]
EBI - DATA[1]
EBI - DATA[0]
EBI - NWE1
2
4
10
12
24
26
31
33
35
38
40
42
EBI - NWE0
44
EBI - NRD
46
EBI - NCS[1]
59
EBI - ADDR[19]
EBI - ADDR[18]
EBI - ADDR[17]
EBI - ADDR[16]
EBI - ADDR[15]
EBI - ADDR[14]
EBI - ADDR[13]
EBI - ADDR[12]
EBI - ADDR[11]
EBI - ADDR[10]
EBI - ADDR[9]
EBI - ADDR[8]
EBI - ADDR[7]
EBI - ADDR[6]
EBI - ADDR[5]
EBI - ADDR[4]
EBI - ADDR[3]
EBI - ADDR[2]
EBI - ADDR[1]
EBI - ADDR[0]
EBI - DATA[15]
61
63
65
67
87
89
91
95
97
99
101
103
105
107
110
112
114
118
120
135
27
32058AS–AVR32–03/07
Table 9-8.
GPIO Controller Function Multiplexing
137
140
142
144
PX36
PX37
PX38
PX39
GPIO 104
GPIO 103
GPIO 102
GPIO 101
EBI - DATA[14]
EBI - DATA[13]
EBI - DATA[12]
EBI - DATA[11]
9.7
Oscillator Pinout
The oscillators are not mapped to the normal A,B or C functions and their muxings are controlled
by registers in the Power Manager (PM). Please refer to the power manager chapter for more
information about this.
Table 9-9.
Oscillator pinout
TQFP100 pin
VQFP144 pin
Pad
Oscillator pin
xin0
85
93
63
86
94
64
124
132
85
PC02
PC04
PC00
PC03
PC05
PC01
xin1
xin32
125
133
86
xout0
xout1
xout32
9.8
Peripheral overview
9.8.1
External Bus Interface
• Optimized for Application Memory Space support
• Integrates Two External Memory Controllers:
– Static Memory Controller
– SDRAM Controller
• Optimized External Bus:
– 16-bit Data Bus
– 24-bit Address Bus, Up to 16-Mbytes Addressable
– Optimized pin multiplexing to reduce latencies on External Memories
• 4 SRAM Chip Selects, 1SDRAM Chip Select:
– Static Memory Controller on NCS0
– SDRAM Controller or Static Memory Controller on NCS1
– Static Memory Controller on NCS2
– Static Memory Controller on NCS3
28
32058AS–AVR32–03/07
9.8.2
Static Memory Controller
• 5 Chip Selects Available
• 64-Mbyte Address Space per Chip Select
• 8-, 16-bit Data Bus
• Word, Halfword, Byte Transfers
• Byte Write or Byte Select Lines
• Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select
• Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select
• Programmable Data Float Time per Chip Select
• Compliant with LCD Module
• External Wait Request
• Automatic Switch to Slow Clock Mode
• Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes
9.8.3
SDRAM Controller
• Numerous Configurations Supported
– 2K, 4K, 8K Row Address Memory Parts
– SDRAM with Two or Four Internal Banks
– SDRAM with 16- or 32-bit Data Path
• Programming Facilities
– Word, Half-word, Byte Access
– Automatic Page Break When Memory Boundary Has Been Reached
– Multibank Ping-pong Access
– Timing Parameters Specified by Software
– Automatic Refresh Operation, Refresh Rate is Programmable
• Energy-saving Capabilities
– Self-refresh, Power-down and Deep Power Modes Supported
– Supports Mobile SDRAM Devices
• Error Detection
– Refresh Error Interrupt
• SDRAM Power-up Initialization by Software
• CAS Latency of 1, 2, 3 Supported
• Auto Precharge Command Not Used
9.8.4
9.8.5
USB Controller
• USB 2.0 Compliant, Full-/Low-Speed (FS/LS) and On-The-Go (OTG), 12 Mbit/s
• 7 Pipes/Endpoints
• 960 bytes of Embedded Dual-Port RAM (DPRAM) for Pipes/Endpoints
• Up to 2 Memory Banks per Pipe/Endpoint (Not for Control Pipe/Endpoint)
• Flexible Pipe/Endpoint Configuration and Management with Dedicated DMA Channels
• On-Chip Transceivers Including Pull-Ups
Serial Peripheral Interface
• Supports communication with serial external devices
– Four chip selects with external decoder support allow communication with up to 15
peripherals
– Serial memories, such as DataFlash and 3-wire EEPROMs
– Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors
– External co-processors
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32058AS–AVR32–03/07
• Master or slave serial peripheral bus interface
– 8- to 16-bit programmable data length per chip select
– Programmable phase and polarity per chip select
– Programmable transfer delays between consecutive transfers and between clock and data
per chip select
– Programmable delay between consecutive transfers
– Selectable mode fault detection
• Very fast transfers supported
– Transfers with baud rates up to MCK
– The chip select line may be left active to speed up transfers on the same device
9.8.6
9.8.7
Two-wire Interface
• High speed up to 400kbit/s
• Compatibility with standard two-wire serial memory
• One, two or three bytes for slave address
• Sequential read/write operations
USART
• Programmable Baud Rate Generator
• 5- to 9-bit full-duplex synchronous or asynchronous serial communications
– 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode
– Parity generation and error detection
– Framing error detection, overrun error detection
– MSB- or LSB-first
– Optional break generation and detection
– By 8 or by-16 over-sampling receiver frequency
– Hardware handshaking RTS-CTS
– Receiver time-out and transmitter timeguard
– Optional Multi-drop Mode with address generation and detection
– Optional Manchester Encoding
• RS485 with driver control signal
• ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards
– NACK handling, error counter with repetition and iteration limit
• IrDA modulation and demodulation
– Communication at up to 115.2 Kbps
• Test Modes
– Remote Loopback, Local Loopback, Automatic Echo
9.8.8
Serial Synchronous Controller
• Provides serial synchronous communication links used in audio and telecom applications (with
CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader, etc.)
• Contains an independent receiver and transmitter and a common clock divider
• Offers a configurable frame sync and data length
• Receiver and transmitter can be programmed to start automatically or on detection of different
event on the frame sync signal
• Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal
9.8.9
Timer Counter
• Three 16-bit Timer Counter Channels
• Wide range of functions including:
– Frequency Measurement
30
32058AS–AVR32–03/07
– Event Counting
– Interval Measurement
– Pulse Generation
– Delay Timing
– Pulse Width Modulation
– Up/down Capabilities
• Each channel is user-configurable and contains:
– Three external clock inputs
– Five internal clock inputs
– Two multi-purpose input/output signals
• Two global registers that act on all three TC Channels
9.8.10
Pulse Width Modulation Controller
• 7 channels, one 16-bit counter per channel
• Common clock generator, providing Thirteen Different Clocks
– A Modulo n counter providing eleven clocks
– Two independent Linear Dividers working on modulo n counter outputs
• Independent channel programming
– Independent Enable Disable Commands
– Independent Clock
– Independent Period and Duty Cycle, with Double Bufferization
– Programmable selection of the output waveform polarity
– Programmable center or left aligned output waveform
9.8.11
Ethernet 10/100 MAC
• Compatibility with IEEE Standard 802.3
• 10 and 100 Mbits per second data throughput capability
• Full- and half-duplex operations
• MII or RMII interface to the physical layer
• Register Interface to address, data, status and control registers
• DMA Interface, operating as a master on the Memory Controller
• Interrupt generation to signal receive and transmit completion
• 28-byte transmit and 28-byte receive FIFOs
• Automatic pad and CRC generation on transmitted frames
• Address checking logic to recognize four 48-bit addresses
• Support promiscuous mode where all valid frames are copied to memory
• Support physical layer management through MDIO interface control of alarm and update
time/calendar data
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32058AS–AVR32–03/07
10. Boot Sequence
This chapter summarizes the boot sequence of the AT32UC3A. The behaviour after power-up is
controlled by the Power Manager. For specific details, refer to Section 13. ”Power Manager
(PM)” on page 47.
10.1 Starting of clocks
After power-up, the device will be held in a reset state by the Power-On Reset circuitry, until the
power has stabilized throughout the device. Once the power has stabilized, the device will use
the internal RC Oscillator as clock source.
On system start-up, the PLLs are disabled. All clocks to all modules are running. No clocks have
a divided frequency, all parts of the system recieves a clock with the same frequency as the
internal RC Oscillator.
10.2 Fetching of initial instructions
After reset has been released, the AVR32 UC CPU starts fetching instructions from the reset
address, which is 0x8000_0000. This address points to the first address in the internal Flash.
The code read from the internal Flash is free to configure the system to use for example the
PLLs, to divide the frequency of the clock routed to some of the peripherals, and to gate the
clocks to unused peripherals.
32
32058AS–AVR32–03/07
11. Electrical Characteristics
11.1 Absolute Maximum Ratings*
Operating Temperature.................................... -40°C to +85°C
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Storage Temperature.......................................................... ....-
60°C to +150°C
Voltage on any Pin except RESET_N
with respect to Ground ............................-TBDV to VCC+TBDV
Voltage on RESET_N with respect to Ground-TBDV to +TBDV
Maximum Operating Voltage (VDDCORE, VDDSYS) .... 1.95V
Maximum Operating Voltage (VDDIO).............................. 3.6V
DC Current per I/O Pin ............................................... TBD mA
DC Current VCC and GND Pins.................................. TBD mA
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32058AS–AVR32–03/07
11.2 DC Characteristics
The following characteristics are applicable to the operating temperature range: TA = -40°C to 85°C, unless otherwise spec-
ified and are certified for a junction temperature up to TJ = 100°C.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
VVDDCOR
DC Supply Core
1.65
1.95
E
VVDDBU
VVDDOSC
VVDDPLL
VVDDUSB
VVDDIO
VREF
DC Supply Backup
1.65
1.65
1.65
1.65
3.0
1.95
1.95
DC Supply Oscillator
DC Supply PLL
1.95
DC Supply USB
1.95
DC Supply Peripheral I/Os
Analog reference voltage
Input Low-level Voltage
Input High-level Voltage
Output Low-level Voltage
Output High-level Voltage
Input Leakage Current
Input Capacitance
3.6
2.6
3.6
VIL
-0.3
2.0
+0.8
VIH
VVDDIO+0.3
0.4
VOL
VOH
VVDDIO= VVDDIOM or VVDDIOP
Pullup resistors disabled
TQFP100 Package
VVDDIO-0.4
ILEAK
TBD
TBD
CIN
RPULLUP
IO
Pull-up Resistance
TBD
TBD
Output Current
TBD
On VVDDCORE = 1.8V,
TA =25°C
TA =85°C
CPU = 0 Hz, CPU is in
static mode
ISC
Static Current
All inputs driven;
RESET_N=1, CPU is in
static mode
TBD
11.3 Power Consumption
The values in Table 11-1 and Table 11-2 on page 35 are measured values of power consump-
tion with operating conditions as follows:
•VDDIO = 3.3V
•VDDCORE = VDDSYS = 1.8V
•TA = 25°C
•I/Os are inactive
34
32058AS–AVR32–03/07
These figures represent the power consumption measured on the power supplies.
Table 11-1. Power Consumption for Different Modes(1)
Mode
Conditions
Consumption
Unit
Core/HSB clock is 66 MHz.
PBA clock is 30 MHz.
PBB clock is 66 MHz.
Active
40
mA
All peripheral clocks activated.
Measured while the processor is executing a
recursive Fibonacci algorithm.
Table 11-2. Power Consumption by Peripheral in Active Mode
Peripheral
Consumption
TBD
Unit
GPIO
USART
TBD
USBB
TBD
MACB
TBD
SMC
TBD
SDRAMC
TBD
mA
ADC
TBD
TWI
TBD
PWM
TBD
SPI
TBD
SSC
TBD
Timer Counter Channels
TBD
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32058AS–AVR32–03/07
11.4 Clock Characteristics
These parameters are given in the following conditions:
•VDDCORE = 1.8V
•Ambient Temperature = 25°C
11.4.1
CPU/HSB Clock Characteristics
Table 11-3. Core Clock Waveform Parameters
Symbol
1/(tCPCPU
tCPCPU
Parameter
Conditions
Conditions
Conditions
Conditions
Min
Max
Units
MHz
ns
)
CPU Clock Frequency
CPU Clock Period
66
15,15
11.4.2
PBA Clock Characteristics
Table 11-4. PBA Clock Waveform Parameters
Symbol
1/(tCPPBA
tCPPBA
Parameter
Min
Max
Units
MHz
ns
)
PBA Clock Frequency
PBA Clock Period
33
30,30
11.4.3
PBB Clock Characteristics
Table 11-5. PBB Clock Waveform Parameters
Symbol
1/(tCPPBB
tCPPBB
Parameter
Min
Max
Units
MHz
ns
)
PBB Clock Frequency
PBB Clock Period
66
15,15
11.4.4
XIN Clock Characteristics
Table 11-6. XIN Clock Electrical Characteristics
Symbol
Parameter
Min
Max
Units
1/(tCPXIN
tCPXIN
tCHXIN
tCLXIN
CIN
)
XIN Clock Frequency
XIN Clock Period
3
24
MHz
ns
20.0
XIN Clock High Half-period
XIN Clock Low Half-period
XIN Input Capacitance
XIN Pulldown Resistor
0.4 x tCPXIN
0.4 x tCPXIN
0.6 x tCPXIN
0.6 x tCPXIN
TBD
(1)
(1)
pF
RIN
TBD
kΩ
Note:
1. These characteristics apply only when the Main Oscillator is in bypass mode (i.e., when MOSCEN = 0 and OSCBYPASS =
1 in the CKGR_MOR register.)
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32058AS–AVR32–03/07
11.5 Crystal Oscillator Characteristis
The following characteristics are applicable to the operating temperature range: TA = -40°C to 85°C and worst case of
power supply, unless otherwise specified.
11.5.1
32 KHz Oscillator Characteristics
Table 11-7. 32 KHz Oscillator Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Hz
%
1/(tCP32KHz
)
Crystal Oscillator Frequency
Duty Cycle
32 768
TBD
TBD
TBD
tST
Startup Time
RS = TBD kΩ, CL = TBD pF(1)
ms
Note:
1. RS is the equivalent series resistance, CL is the equivalent load capacitance.
11.5.2
Main Oscillators Characteristics
Table 11-8. Main Oscillator Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1/(tCPMAIN
)
Crystal Oscillator Frequency
0.45
16
MHz
Internal Load Capacitance
(CL1 = CL2)
CL1, CL2
CL
TBD
pF
Equivalent Load Capacitance
Duty Cycle
TBD
TBD
pF
%
TBD
TBD
TBD
TBD
TBD
tST
Startup Time
ms
µA
µA
Active mode @TBD MHz
Standby mode @TBD V
IOSC
Current Consumption
Notes: 1. CS is the shunt capacitance
11.5.3 PLL Characteristics
Table 11-9. Phase Lock Loop Characteristics
Symbol
FOUT
Parameter
Conditions
Min
80
Typ
Max
240
Unit
MHz
MHz
mA
Output Frequency
Input Frequency
FIN
TBD
TBD
TBD
TBD
active mode
IPLL
Current Consumption
standby mode
µA
Note:
1. Startup time depends on PLL RC filter. A calculation tool is provided by Atmel.
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32058AS–AVR32–03/07
11.6 USB Transceiver Characteristics
11.6.1
Electrical Characteristics
Table 11-10. Electrical Parameters
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Input Levels
VIL
VIH
VDI
Low Level
TBD
V
V
V
High Level
TBD
TBD
Differential Input Sensivity
|(D+) - (D-)|
Differential Input Common
Mode Range
VCM
TBD
TBD
V
CIN
I
Transceiver capacitance
Capacitance to ground on each line
0V < VIN < 3.3V
TBD
TBD
pF
µA
Hi-Z State Data Line Leakage
TBD
Recommended External USB
Series Resistor
REXT
In series with each USB pin with 5%
TBD
Ω
Output Levels
VOL
Measured with RL of 1.425 kΩ tied to
3.6V
Low Level Output
High Level Output
TBD
TBD
TBD
TBD
TBD
TBD
V
V
V
Measured with RL of 14.25 kΩ tied to
GND
VOH
Output Signal Crossover
Voltage
Measure conditions described in
Figure 11-1
VCRS
11.6.2
Switching Characteristics
Table 11-11. In Low Speed
Symbol
tFR
Parameter
Conditions
Min
TBD
TBD
TBD
Typ
Typ
Max
TBD
TBD
TBD
Unit
ns
Transition Rise Time
Transition Fall Time
Rise/Fall time Matching
CLOAD = 400 pF
CLOAD = 400 pF
CLOAD = 400 pF
tFE
ns
tFRFM
%
Table 11-12. In Full Speed
Symbol
tFR
Parameter
Conditions
CLOAD = 50 pF
CLOAD = 50 pF
Min
TBD
TBD
TBD
Max
TBD
TBD
TBD
Unit
ns
Transition Rise Time
Transition Fall Time
Rise/Fall time Matching
tFE
ns
tFRFM
%
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32058AS–AVR32–03/07
Figure 11-1. USB Data Signal Rise and Fall Times
11.7 AC Characteristics - TBD
11.8 EBI Timings - TBD
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32058AS–AVR32–03/07
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32058AS–AVR32–03/07
12. Mechanical Characteristics
12.1 Thermal Considerations
12.1.1
Thermal Data
Table 12-1 summarizes the thermal resistance data depending on the package.
Table 12-1. Thermal Resistance Data
Symbol
θJA
Parameter
Condition
Package
TQFP100
TQFP100
LQFP144
LQFP144
Typ
TBD
TBD
TBD
TBD
Unit
Junction-to-ambient thermal resistance Still Air
Junction-to-case thermal resistance
°C/W
θJC
θJA
Junction-to-ambient thermal resistance Still Air
Junction-to-case thermal resistance
°C/W
θJC
12.1.2
Junction Temperature
The average chip-junction temperature, TJ, in °C can be obtained from the following:
1. = T + (P × θ
T
)
JA
J
A
D
2. TJ = TA + (PD × (θHEATSINK + θJC ))
where:
• θJA = package thermal resistance, Junction-to-ambient (°C/W), provided in Table 12-1 on page
41.
• θJC = package thermal resistance, Junction-to-case thermal resistance (°C/W), provided in
Table 12-1 on page 41.
• θHEAT SINK = cooling device thermal resistance (°C/W), provided in the device datasheet.
• PD = device power consumption (W) estimated from data provided in the section ”Power
Consumption” on page 34.
• TA = ambient temperature (°C).
From the first equation, the user can derive the estimated lifetime of the chip and decide if a
cooling device is necessary or not. If a cooling device is to be fitted on the chip, the second
equation should be used to compute the resulting average chip-junction temperature TJ in °C.
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32058AS–AVR32–03/07
12.2 Package Drawings
Figure 12-1. TQFP-100 package drawing
Table 12-2. Device and Package Maximum Weight
TBD
mg
Table 12-3. Package Characteristics
Moisture Sensitivity Level
TBD
Table 12-4. Package Reference
JEDEC Drawing Reference
JESD97 Classification
MS-026
E3
42
32058AS–AVR32–03/07
Figure 12-2. LQFP-144 package drawing
Table 12-5. Device and Package Maximum Weight
TBD
mg
Table 12-6. Package Characteristics
Moisture Sensitivity Level
TBD
Table 12-7. Package Reference
JEDEC Drawing Reference
JESD97 Classification
MS-026
E3
43
32058AS–AVR32–03/07
12.3 Soldering Profile
Table 12-8 gives the recommended soldering profile from J-STD-20.
Table 12-8. Soldering Profile
Profile Feature
Green Package
TBD
Average Ramp-up Rate (217°C to Peak)
Preheat Temperature 175°C 25°C
Temperature Maintained Above 217°C
Time within 5°C of Actual Peak Temperature
Peak Temperature Range
TBD
TBD
TBD
TBD
Ramp-down Rate
TBD
Time 25°C to Peak Temperature
TBD
Note:
It is recommended to apply a soldering temperature higher than 250°C.
A maximum of three reflow passes is allowed per component.
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32058AS–AVR32–03/07
13. Ordering Information
Temperature Operating
Range
Device
Ordering Code
Package
Conditioning
Tray
AT32UC3A0512
AT32UC3A1512
AT32UC3A0256
AT32UC3A1256
AT32UC3A0128
AT32UC3A1128
AT32UC3A0512-ALUT
AT32UC3A1512-AUT
AT32UC3A0256-ALUT
AT32UC3A1256-AUT
AT32UC3A0128-ALUT
AT32UC3A1128-AUT
144 lead LQFP
100 lead TQFP
144 lead LQFP
100 lead TQFP
100 lead TQFP
100 lead TQFP
Industrial (-40°C to 85°C)
Industrial (-40°C to 85°C)
Industrial (-40°C to 85°C)
Industrial (-40°C to 85°C)
Industrial (-40°C to 85°C)
Industrial (-40°C to 85°C)
Tray
Tray
Tray
Tray
Tray
14. Errata
14.1 Rev. E
1. SPI FDIV option does not work
Selecting clock signal using FDIV = 1 does not work as specified.
Fix/Workaround
Do not set FDIV = 1.
2. PWM counter restarts at 0x0001
The PWM counter restarts at 0x0001 and not 0x0000 as specified. Because of this the first
PWM period has one more clock cycle.
Fix/Workaround
- The first period is 0x0000, 0x0001, ..., period
- Consecutive periods are 0x0001, 0x0002, ..., period
3. PWM channel interrupt enabling triggers an interrupt
When enabling a PWM channel that is configured with center aligned period (CALG=1), an
interrupt is signalled.
Fix/Workaround
When using center aligned mode, enable the channel and read the status before channel
interrupt is enabled.
4. PWM update period to a 0 value does not work
It is impossible to update a period equal to 0 by the using the PWM update register
(PWM_CUPD).
Fix/Workaround
Do not update the PWM_CUPD register with a value equal to 0.
5. PWM channel status may be wrong if disabled before a period has elapsed
Before a PWM period has elapsed, the read channel status may be wrong. The CHIDx-bit
for a PWM channel in the PWM Enable Register will read '1' for one full PWM period even if
the channel was disabled before the period elapsed. It will then read '0' as expected.
Fix/Workaround
45
32058AS–AVR32–03/07
Reading the PWM channel status of a disabled channel is only correct after a PWM period
has elapsed.
6. SSC does not trigger RF when data is low
The SSC cannot transmit or receive data when CKS = CKDIV and CKO = none, in TCMR or
RCMR respectively.
Fix/Workaround
Set CKO to a value that is not "none" and bypass the output of the TK/RK pin with the PIO.
7. SSC Data is not sent unless clock is set as output
The SSC cannot transmit or receive data when CKS = CKDIV and CKO = none, in TCMR or
RCMR respectively.
Fix/Workaround
Set CKO to a value that is not "none" and bypass the output of the TK/RK pin with the PIO.
8. USB No end of host reset signaled upon disconnection
In host mode, in case of an unexpected device disconnection whereas a usb reset is being
sent by the usb controller, the UHCON.RESET bit may not been cleared by the hardware at
the end of the reset.
Fix/Workaround
A software workaround consists in testing (by polling or interrupt) the disconnection
(UHINT.DDISCI == 1) while waiting for the end of reset (UHCON.RESET == 0) to avoid
being stuck.
9. Incorrect Processor ID
The processor ID reads 0x01 and not 0x02 as it should.
Fix/Workaround
None.
10. Bus error should be masked in Debug mode
If a bus error occurs during debug mode, the processor will not respond to debug com-
mands through the DINST register.
Fix/Workaround
A reset of the device will make the CPU respond to debug commands again.
11. Code execution from external SDRAM does not work
Code execution from SDRAM does not work.
Fix/Workaround
Do not run code from SDRAM.
12. Read Modify Write (RMW) instructions on data outside the internal RAM does not
work.
Read Modify Write (RMW) instructions on data outside the internal RAM does not work.
Fix/Workaround
Do not perform RMW instructions on data outside the internal RAM.
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32058AS–AVR32–03/07
13. USART Manchester Encoder Not Working
Manchester encoding/decoding is not working.
Fix/Workaround
Do not use manchester encoding.
14. USART RXBREAK problem when no timeguard
In asynchronous mode the RXBREAK flag is not correctly handled when the timeguard is 0
and the break character is located just after the stop bit.
Fix/Workaround
If the NBSTOP is 1, timeguard should be different from 0.
15 USART Handshaking: 2 characters sent / CTS rises when TX
If CTS switches from 0 to 1 during the TX of a character, if the Holding register is not empty,
the TXHOLDING is also transmitted.
Fix/Workaround
None.
16. USART PDC and TIMEGUARD not supported in MANCHESTER
Manchester encoding/decoding is not working.
Fix/Workaround
Do not use manchester encoding.
17. Voltage regulator input and output is connected to VDDIO and VDDCORE inside the
device
The voltage regulator input and output is connected to VDDIO and VDDCORE respectively
inside the device.
Fix/Workaround
Do not supply VDDCORE externally, as this supply will work in paralell with the regulator.
18. ADC possible miss on DRDY when disabling a channel
The ADC does not work properly when more than one channel is enabled.
Fix/Workaround
Do not use the ADC with more than one channel enabled at a time.
19. ADC OVRE flag sometimes not reset on Status Register read
The OVRE flag does not clear properly if read simultaneously to an end of conversion.
Fix/Workaround
None.
20. CRC calculation of a locked device will calculate CRC for 512 kB of flash memory,
even though the part has less flash.
Fix/Workaround
The flash address space is wrapping, so it is possible to use the CRC value by calculating
CRC of the flash content concatenated with itself N times. Where N is 512 kB/flash size.
21. SDRAM SDCKE rise at the same time as SDCK while exiting self-refresh mode
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32058AS–AVR32–03/07
SDCKE rise at the same time as SDCK while exiting self-refresh mode.
Fix/Workaround
None.
22. PCx pins go low in stop mode
In sleep mode stop all PCx pins will be controlled by GPIO module instead of oscillators.
This can cause drive contention on the XINx in worst case.
Fix/Workaround
Before entering stop mode set all PCx pins to input and GPIO controlled.
23. Need two NOPs instruction after instructions masking interrupts
The instructions following in the pipeline the instruction masking the interrupt through SR
may behave abnormally.
Fix/Workaround
Place two NOPs instructions after each SSRF or MTSR instruction setting IxM or GM in SR.
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32058AS–AVR32–03/07
15. Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The
referring revision in this section are referring to the document revision.
15.1 Rev. A 03/07
1.
Initial revision.
49
32058AS–AVR32–03/07
1
2
3
Description ............................................................................................... 2
Configuration Summary .......................................................................... 3
Blockdiagram ........................................................................................... 4
3.1Processor and architecture .......................................................................................5
4
5
6
Signals Description ................................................................................. 7
Package and Pinout ............................................................................... 12
Power Considerations ........................................................................... 15
6.1Power Supplies .......................................................................................................15
6.2Voltage Regulator ....................................................................................................15
7
I/O Line Considerations ......................................................................... 16
7.1JTAG pins ................................................................................................................16
7.2RESET_N pin ..........................................................................................................16
7.3TWI pins ..................................................................................................................16
7.4GPIO pins ................................................................................................................16
8
9
Memories ................................................................................................ 17
8.1Embedded Memories ..............................................................................................17
8.2Physical Memory Map .............................................................................................17
Peripherals ............................................................................................. 19
9.1Peripheral address map ..........................................................................................19
9.2Interrupt Request Signal Map ..................................................................................20
9.3Clock Connections ..................................................................................................23
9.4Nexus OCD AUX port connections .........................................................................23
9.5DMA handshake signals ..........................................................................................24
9.6Peripheral Multiplexing on I/O lines .........................................................................25
9.7Oscillator Pinout ......................................................................................................28
9.8Peripheral overview .................................................................................................28
10 Boot Sequence ....................................................................................... 32
10.1Starting of clocks ...................................................................................................32
10.2Fetching of initial instructions ................................................................................32
11 Electrical Characteristics ...................................................................... 33
11.1Absolute Maximum Ratings* .................................................................................33
11.2DC Characteristics ................................................................................................34
11.3Power Consumption ..............................................................................................34
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32058AS–AVR32–03/07
11.4Clock Characteristics .............................................................................................36
11.5Crystal Oscillator Characteristis ............................................................................37
11.6USB Transceiver Characteristics ...........................................................................38
11.7AC Characteristics - TBD ......................................................................................39
11.8EBI Timings - TBD .................................................................................................39
12 Mechanical Characteristics ................................................................... 41
12.1Thermal Considerations ........................................................................................41
12.2Package Drawings ................................................................................................42
12.3Soldering Profile ....................................................................................................44
13 Ordering Information ............................................................................. 45
14 Errata ....................................................................................................... 45
14.1Rev. E ....................................................................................................................45
15 Datasheet Revision History .................................................................. 49
15.1Rev. A 03/07 ..........................................................................................................49
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32058AS–AVR32–03/07
相关型号：
AT32UC3A0512-ALTRA
RISC Microcontroller, 32-Bit, FLASH, AVR RISC CPU, 66MHz, CMOS, PQFP144, MS-026, LQFP-144
ATMEL
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