AT48801-16QC [ATMEL]

8 Bit Spread- Spectrum Microcontroller; 8位扩频微控制器


型号：	AT48801-16QC
厂家：	ATMEL
描述：	8 Bit Spread- Spectrum Microcontroller 8位扩频微控制器微控制器
文件：	总17页 (文件大小：433K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT48801

Features

Compatible with MCS-51 Products

8K bytes of On-Board Program Memory

Fully Static Operation: 0 Hz to 16 MHz

256 x 8 Bit Internal RAM

32 Programmable I/O Lines

Three 16 Bit Timer/Counters

Eight Interrupt Sources

Programmable Serial Channel

•

Low Power Idle and Power Down Modes

•

8 Bit

Spread-

Spectrum

Microcontroller

Description

The AT48801 is a low-power, high-performance CMOS 8 bit microcomputer with 8K

bytes on-board program memory. The device is compatible with the industry standard

80C51 and 80C52 instruction set and pinout. The Atmel AT48801 is a powerful micro-

computer which provides a highly flexible and cost effective solution to spread-spec-

trum applications.

The AT48801 provides the following standard features: 8K bytes of program memory,

256-bytes of RAM, 32 I/O lines, three 16 bit timer/counters, a six-vector two-level

interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In

addition, the AT48801 is designed with static logic for operation down to zero fre-

quency and supports two software selectable power saving modes. The Idle Mode

stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt sys-

tem to continue functioning. The Power Down Mode saves the RAM contents but

freezes the oscillator, disabling all other chip functions until the next hardware reset.

Preliminary

Pin Configuration

PQFP

0629A

1-1

Block Diagram

1-2

AT48801

the internal pullups and can be used as inputs. As inputs,

Port 3 pins that are externally being pulled low will source

Pin Description

current (I ) because of the pullups.

Supply voltage.

GND

Port 3 also serves the functions of various special features

of the AT89C51, as shown in the following table.

Ground.

Port 0

Alternate Functions

Port Pin

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

RXD (serial input port)

Port 0 is an 8 bit open drain bidirectional I/O port. As an

output port, each pin can sink eight TTL inputs. When 1s

are written to port 0 pins, the pins can be used as high-im-

pedance inputs.

TXD (serial output port)

INT0 (external interrupt 0)

INT1 (external interrupt 1)

T0 (timer 0 external input)

T1 (timer 1 external input)

WR (external data memory write strobe)

RD (external data memory read strobe)

Port 0 can also be configured to be the multiplexed low-or-

der address/data bus during accesses to external pro-

gram and data memory. In this mode, P0 has internal pul-

lups.

Port 1

RST

Port 1 is an 8 bit bidirectional I/O port with internal pullups.

The Port 1 output buffers can sink/source four TTL inputs.

When 1s are written to Port 1 pins, they are pulled high by

the internal pullups and can be used as inputs. As inputs,

Port 1 pins that are externally being pulled low will source

Reset input. A high on this pin for two machine cycles

while the oscillator is running resets the device.

ALE

Address Latch Enable is an output pulse for latching the

low byte of the address during accesses to external mem-

ory.

current (I ) because of the internal pullups.

In addition, P1.0 and P1.1 can be configured to be the

timer/counter 2 external count input (P1.0/T2) and the

timer/counter 2 trigger input (P1.1/T2EX), respectively, as

shown in the following table.

In normal operation, ALE is emitted at a constant rate of

1/6 the oscillator frequency and may be used for external

timing or clocking purposes. Note, however, that one ALE

pulse is skipped during each access to external data

memory.

Alternate Functions

Port Pin

T2 (external count input to

Timer/Counter 2), clock-out

P1.0

If desired, ALE operation can be disabled by setting bit 0

of SFR location 8EH. With the bit set, ALE is active only

during a MOVX or MOVC instruction. Otherwise, the pin is

weakly pulled high. Setting the ALE-disable bit has no ef-

fect if the microcrontroller is in external execution mode.

T2EX (Timer/Counter 2 capture/reload

trigger and direction control)

P1.1

Port 2

PSEN

Port 2 is an 8 bit bidirectional I/O port with internal pullups.

The Port 2 output buffers can sink/source four TTL inputs.

When 1s are written to Port 2 pins, they are pulled high by

the internal pullups and can be used as inputs. As inputs,

Port 2 pins that are externally being pulled low will source

Program Store Enable is the read strobe to external pro-

gram memory.

When the AT48801 is executing code from external pro-

gram memory, PSEN is activated twice each machine cy-

cle, except that two PSEN activations are skipped during

each access to external data memory.

current (I ) because of the internal pullups.

Port 2 emits the high-order address byte during fetches

from external program memory and during accesses to

external data memory that use 16 bit addresses (MOVX

@ DPTR). In this application, Port 2 uses strong internal

pullups when emitting 1s. During accesses to external

data memory that use 8 bit addresses (MOVX @ RI), Port

2 emits the contents of the P2 Special Function Register.

External Access Enable. EA must be strapped to GND in

order to enable the device to fetch code from external pro-

gram memory locations starting at 0000H up to FFFFH.

Note, however, that if lock bit 1 is programmed, EA will be

internally latched on reset.

Port 3

EA should be strapped to V for internal program execu-

tions.

Port 3 is an 8 bit bidirectional I/O port with internal pullups.

The Port 3 output buffers can sink/source four TTL inputs.

When 1s are written to Port 3 pins, they are pulled high by

(continued)

1-3

Note that not all of the addresses are occupied, and unoc-

cupied addresses may not be implemented on the chip.

Read accesses to these addresses will in general return

random data, and write accesses will have an indetermi-

nate effect.

Pin Description (Continued)

XTAL1

Input to the inverting oscillator amplifier and input to the

internal clock operating circuit.

XTAL2

User software should not write 1s to these unlisted loca-

tions, since they may be used in future products to invoke

new features. In that case, the reset or inactive values of

the new bits will always be 0.

Output from the inverting oscillator amplifier.

Special Function Registers

A map of the on-chip memory area called the Special

Function Register (SFR) space is shown in Table 1.

Timer 2 Registers Control and status bits are contained

in registers T2CON (shown in Table 2) and T2MOD

(shown in Table 4) for Timer 2. The register pair

(continued)

Table 1. AT48801 SFR Map and Reset Values

0F8H

0FFH

0F7H

0EFH

0E7H

0DFH

0D7H

0F0H

00000000

0E8H

ACC

0E0H

00000000

0D8H

PSW

0D0H

00000000

T2CON

T2MOD

RCAP2L

RCAP2H

00000000

TL2

00000000

TH2

00000000

0C8H

0C0H

0B8H

0B0H

0A8H

0A0H

98H

0CFH

0C7H

0BFH

0B7H

0AFH

0A7H

9FH

00000000 XXXXXX00 00000000

XX000000

11111111

0X000000

11111111

SCON

00000000 XXXXXXXX

SBUF

11111111

90H

97H

TCON

00000000

TMOD

00000000

TL0

00000000

TL1

00000000

TH0

00000000

TH1

00000000

88H

8FH

11111111

00000111

DPL

00000000

DPH

00000000

PCON

0XXX0000

80H

87H

1-4

AT48801

Table 2. T2CON—Timer/Counter 2 Control Register

T2CON Address = 0C8H

Bit Addressable

Reset Value = 0000 0000B

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2

CP/RL2

Bit

Symbol

Function

TF2

Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be

set when either RCLK = 1 or TCLK = 1.

EXF2

Timer 2 external flag set when either a capture or reload is caused by a negative transition on

T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector

to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an

interrupt in up/down counter mode (DCEN = 1).

RCLK

TCLK

Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its

receive clock in serial port Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the

receive clock.

Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its

transmit clock in serial port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for

the transmit clock.

EXEN2

Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative

transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer

2 to ignore events at T2EX.

TR2

Start/Stop control for Timer 2. TR2 = 1 starts the timer.

Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event

counter (falling edge triggered).

C/T2

CP/RL2

Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if

EXEN2 = 1. CP/RL2 = 0 causes automatic reloads to occur when Timer 2 overflows or negative

transitions occur at T2EX when EXEN2 = 1. When either RCLK or TCLK = 1, this bit is ignored

and the timer is forced to auto-reload on Timer 2 overflow.

Special Function Registers (Continued)

(RCAP2H, RCAP2L) are the Capture/Reload registers for

Timer 2 in 16 bit capture mode or 16 bit auto-reload mode.

When an instruction accesses an internal location above

address 7FH, the address mode used in the instruction

specifies whether the CPU accesses the upper 128-bytes

of RAM or the SFR space. Instructions that use direct ad-

dressing access SFR space.

Interrupt Registers The individual interrupt enable bits

are in the IE register. Two priorities can be set for each of

the six interrupt sources in the IP register.

For example, the following direct addressing instruction

accesses the SFR at location 0A0H (which is P2).

MOV 0A0H, #data

Data Memory

Instructions that use indirect addressing access the upper

128-bytes of RAM. For example, the following indirect ad-

dressing instruction, where R0 contains 0A0H, accesses

the data byte at address 0A0H, rather than P2 (whose ad-

dress is 0A0H).

The AT48801 implements 256-bytes of on-chip RAM. The

upper 128-bytes occupy a parallel address space to the

Special Function Registers. That means the upper 128-

bytes have the same addresses as the SFR space but are

physically separate from SFR space.

(continued)

1-5

Data Memory (Continued)

MOV @R0, #data

cillator frequency. To ensure that a given level is sampled

at least once before it changes, the level should be held

for at least one full machine cycle.

Note that stack operations are examples of indirect ad-

dressing, so the upper 128-bytes of data RAM are avail-

able as stack space.

Table 3. Timer 2 Operating Modes

RCLK + TCLK

CP/RL2

TR2

MODE

Timer 0 and 1

Timer 0 and Timer 1 in the AT48801 operate the same

way as Timer 0 and Timer 1 in the AT89C51.

16 Bit Auto-Reload

16 Bit Capture

Baud Rate Generator

(Off)

Timer 2

Timer 2 is a 16 bit Timer/Counter that can operate as

either a timer or an event counter. The type of operation is

selected by bit C/T2 in the SFR T2CON (shown in Table

2). Timer 2 has three operating modes: capture, auto-re-

load (up or down counting), and baud rate generator. The

modes are selected by bits in T2CON, as shown in Table

Capture Mode

In the capture mode, two options are selected by bit

EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16 bit timer

or counter which upon overflow sets bit TF2 in T2CON.

This bit can then be used to generate an interrupt. If

EXEN2 = 1, Timer 2 performs the same operation, but a

l-to-0 transition at external input T2EX also causes the

current value in TH2 and TL2 to be captured into RCAP2H

and RCAP2L, respectively. In addition, the transition at

T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit,

like TF2, can generate an interrupt. The capture mode is

illustrated in Figure 1.

Timer 2 consists of two 8 bit registers, TH2 and TL2. In the

Timer function, the TL2 register is incremented every ma-

chine cycle. Since a machine cycle consists of 12 oscilla-

tor periods, the count rate is 1/12 of the oscillator fre-

quency.

In the Counter function, the register is incremented in re-

sponse to a l-to-0 transition at its corresponding external

input pin, T2. In this function, the external input is sampled

during S5P2 of every machine cycle. When the samples

show a high in one cycle and a low in the next cycle, the

count is incremented. The new count value appears in the

which the transition was detected. Since two machine cy-

cles (24 oscillator periods) are required to recognize a 1-

to-0 transition, the maximum count rate is 1/24 of the os-

Auto-Reload (Up or Down Counter)

Timer 2 can be programmed to count up or down when

configured in its 16 bit auto-reload mode. This feature is

invoked by the DCEN (Down Counter Enable) bit located

in the SFR T2MOD (see Table 4). Upon reset, the DCEN

bit is set to 0 so that timer 2 will default to count up. When

DCEN is set, Timer 2 can count up or down, depending on

the value of the T2EX pin.

(continued)

Figure 1. Timer 2 in Capture Mode

1-6

AT48801

Auto-Reload (Up or Down Counter) (Continued)

Figure 2 shows Timer 2 automatically counting up when

DCEN = 0. In this mode, two options are selected by bit

EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to

0FFFFH and then sets the TF2 bit upon overflow. The

overflow also causes the timer registers to be reloaded

with the 16 bit value in RCAP2H and RCAP2L. The values

in RCAP2H and RCAP2L are preset by software. If

EXEN2 = 1, a 16 bit reload can be triggered either by an

overflow or by a l-to-0 transition at external input T2EX.

This transition also sets the EXF2 bit. Both the TF2 and

EXF2 bits can generate an interrupt if enabled.

2 count up. The timer will overflow at 0FFFFH and set the

TF2 bit. This overflow also causes the 16 bit value in

RCAP2H and RCAP2L to be reloaded into the timer regis-

ters, TH2 and TL2, respectively.

A logic 0 at T2EX makes Timer 2 count down. The timer

underflows when TH2 and TL2 equal the values stored in

RCAP2H and RCAP2L. The underflow sets the TF2 bit

and causes 0FFFFH to be reloaded into the timer regis-

ters.

The EXF2 bit toggles whenever Timer 2 overflows or un-

derflows and can be used as a 17th bit of resolution. In this

operating mode, EXF2 does not flag an interrupt.

Setting the DCEN bit enables Timer 2 to count up or down,

as shown in Figure 3. In this mode, the T2EX pin controls

the direction of the count. A logic 1 at T2EX makes Timer

Figure 2. Timer 2 Auto Reload Mode (DCEN = 0)

Table 4. T2MOD—Timer 2 Mode Control Register

T2MOD Address = 0C9H

Reset Value = XXXX XX00B

Not Bit Addressable

—

T2OE

DCEN

Bit

Symbol

—

Function

Not implemented, reserved for future use.

Timer 2 Output Enable bit.

T2OE

DCEN

When set, this bit allows Timer 2 to be configured as an up/down counter.

1-7

Figure 3. Timer 2 Auto Reload Mode (DCEN = 1)

Figure 4. Timer 2 in Baud Rate Generator Mode

1-8

AT48801

Baud Rate Generator

Timer 2 is selected as the baud rate generator by setting

TCLK and/or RCLK in T2CON (Table 2). Note that the

baud rates for transmit and receive can be different if

Timer 2 is used for the receiver or transmitter and Timer 1

is used for the other function. Setting RCLK and/or TCLK

puts Timer 2 into its baud rate generator mode, as shown

in Figure 4.

Modes 1 and 3

Baud Rate

Oscillator Frequency

32 x [65536 − (RCAP2H, RCAP2L)]

where (RCAP2H, RCAP2L) is the content of RCAP2H and

RCAP2L taken as a 16 bit unsigned integer.

Timer 2 as a baud rate generator is shown in Figure 4.

This figure is valid only if RCLK or TCLK = 1 in T2CON.

Note that a rollover in TH2 does not set TF2 and will not

generate an interrupt. Note too, that if EXEN2 is set, a l-to-

0 transition in T2EX will set EXF2 but will not cause a re-

load from (RCAP2H, RCAP2L) to (TH2, TL2). Thus when

Timer 2 is in use as a baud rate generator, T2EX can be

used as an extra external interrupt.

The baud rate generator mode is similar to the auto-reload

mode, in that a rollover in TH2 causes the Timer 2 regis-

ters to be reloaded with the 16 bit value in registers

RCAP2H and RCAP2L, which are preset by software.

The baud rates in Modes l and 3 are determined by Timer

2’s overflow rate according to the following equation.

Note that when Timer 2 is running (TR2 = 1) as a timer in

the baud rate generator mode, TH2 or TL2 should not be

read from or written to. Under these conditions, the Timer

is incremented every state time, and the results of a read

or write may not be accurate. The RCAP2 registers may

be read but should not be written to, because a write might

overlap a reload and cause write and/or reload errors. The

timer should be turned off (clear TR2) before accessing

the Timer 2 or RCAP2 registers.

Timer2 Overflow Rate

Modes 1 and 3 Baud Rates =

The Timer can be configured for either timer or counter

operation. In most applications, it is configured for timer

operation (CP/T2 = 0). The timer operation is different for

Timer 2 when it is used as a baud rate generator. Nor-

mally, as a timer, it increments every machine cycle (at

1/12 the oscillator frequency). As a baud rate generator,

however, it increments every state time (at 1/2 the oscilla-

tor frequency). The baud rate formula is given below.

Figure 5. Timer 2 in Clock-Out Mode

1-9

Programmable Clock Out

Interrupts

A 50% duty cycle clock can be programmed to come out

on P1.0, as shown in Figure 5. This pin, besides being a

regular I/0 pin, has two alternate functions. It can be pro-

grammed to input the external clock for Timer/Counter 2 or

to output a 50% duty cycle clock ranging from 61 Hz to 4

MHz at a 16 MHz operating frequency.

The AT48801 has a total of six interrupt vectors: two exter-

nal interrupts (INT0 and INT1), three timer interrupts (Tim-

ers 0, 1, and 2), and the serial port interrupt. These inter-

rupts are all shown in Figure 6.

Each of these interrupt sources can be individually en-

abled or disabled by setting or clearing a bit in Special

Function Register IE. IE also contains a global disable bit,

EA, which disables all interrupts at once.

To configure the Timer/Counter 2 as a clock generator, bit

C/T2 (T2CON.1) must be cleared and bit T2OE

(T2MOD.1) must be set. Bit TR2 (T2CON.2) starts and

stops the timer.

Note that Table 5 shows that bit position IE.6 is unimple-

mented. In the AT89C51, bit position IE.5 is also unimple-

mented. User software should not write 1s to these bit po-

sitions, since they may be used in future AT89 products.

The clock-out frequency depends on the oscillator fre-

quency and the reload value of Timer 2 capture registers

(RCAP2H, RCAP2L), as shown in the following equation.

Timer 2 interrupt is generated by the logical OR of bits TF2

and EXF2 in register T2CON. Neither of these flags is

cleared by hardware when the service routine is vectored

(continued)

Oscillator Frequency

Clock−Out Frequency =

4 x [65536 − (RCAP2H, RCAP2L)]

In the clock-out mode, Timer 2 roll-overs will not generate

an interrupt. This behavior is similar to when Timer 2 is

used as a baud-rate generator. It is possible to use Timer

2 as a baud-rate generator and a clock generator simulta-

neously. Note, however, that the baud-rate and clock-out

frequencies cannot be determined independently from

one another since they both use RCAP2H and RCAP2L.

Table 5. Interrupt Enable (IE) Register

(MSB)

(LSB)

—

ET2 ES ET1 EX1 ET0 EX0

Enable Bit = 1 enables the interrupt.

Enable Bit = 0 disables the interrupt.

UART

The UART in the AT48801 operates the same way as the

UART in the AT89C51.

Symbol Position Function

Figure 6. Interrupt Sources

Disables all interrupts. If

EA = 0, no interrupt is

acknowledged. If EA = 1,

each interrupt source is

individually enabled or

disabled by setting or clearing

its enable bit.

IE.7

—

IE.6

IE.5

IE.4

IE.3

IE.2

IE.1

IE.0

Reserved.

ET2

Timer 2 interrupt enable bit.

Serial Port interrupt enable bit.

Timer 1 interrupt enable bit.

External interrupt 1 enable bit.

Timer 0 interrupt enable bit.

External interrupt 0 enable bit.

ET1

EX1

ET0

EX0

User software should never write 1s to

unimplemented bits, because they may be used in

future AT89 products.

1-10

AT48801

Power Down Mode

Interrupts (Continued)

In the power down mode, the oscillator is stopped, and the

instruction that invokes power down is the last instruction

executed. The on-chip RAM and Special Function Regis-

ters retain their values until the power down mode is termi-

nated. The only exit from power down is a hardware reset.

Reset redefines the SFRs but does not change the on-

to. In fact, the service routine may have to determine

whether it was TF2 or EXF2 that generated the interrupt,

and that bit will have to be cleared in software.

The Timer 0 and Timer 1 flags, TF0 and TFI, are set at

S5P2 of the cycle in which the timers overflow. The values

are then polled by the circuitry in the next cycle. However,

the Timer 2 flag, TF2, is set at S2P2 and is polled in the

same cycle in which the timer overflows.

chip RAM. The reset should not be activated before V

is restored to its normal operating level and must be held

active long enough to allow the oscillator to restart and

stabilize.

Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, respectively,

of an inverting amplifier that can be configured for use as

an on-chip oscillator, as shown in Figure 7. Either a quartz

crystal or ceramic resonator may be used. To drive the

device from an external clock source, XTAL2 should be

left unconnected while XTAL1 is driven, as shown in Fig-

ure 8. There are no requirements on the duty cycle of the

external clock signal, since the input to the internal clock-

ing circuitry is through a divide-by-two flip-flop, but mini-

mum and maximum voltage high and low time specifica-

tions must be observed.

Figure 7. Oscillator Connections

Idle Mode

Notes: C1, C2 = 30 pF ± 10 pF for Crystals

= 40 pF ± 10 pF for Ceramic Resonators

In idle mode, the CPU puts itself to sleep while all the on-

chip peripherals remain active. The mode is invoked by

software. The content of the on-chip RAM and all the spe-

cial functions registers remain unchanged during this

mode. The idle mode can be terminated by any enabled

interrupt or by a hardware reset.

Figure 8. External Clock Drive Configuration

Note that when idle mode is terminated by a hardware re-

set, the device normally resumes program execution from

where it left off, up to two machine cycles before the inter-

nal reset algorithm takes control. On-chip hardware inhib-

its access to internal RAM in this event, but access to the

port pins is not inhibited. To eliminate the possibility of an

unexpected write to a port pin when idle mode is termi-

nated by a reset, the instruction following the one that in-

vokes idle mode should not write to a port pin or to external

memory.

Status of External Pins During Idle and Power Down

Mode

Program Memory

Internal

ALE

PSEN

PORT0

Data

PORT1

Data

PORT2

Data

PORT3

Data

Idle

External

Float

Data

Address

Data

Power Down

Internal

Data

External

Float

Data

1-11

Absolute Maximum Ratings*

*NOTICE: Stresses beyond those listed under “Absolute Maxi-

mum Ratings” may cause permanent damage to the device.

This is a stress rating only and functional operation of the

device at these or any other conditions beyond those indi-

cated in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions

for extended periods may affect device reliability.

Operating Temperature................... -55°C to +125°C

Storage Temperature...................... -65°C to +150°C

Voltage on Any Pin

with Respect to Ground ..................... -1.0V to +7.0V

Maximum Operating Voltage ............................. 6.6V

DC Output Current....................................... 15.0 mA

DC Characteristics

The values shown in this table are valid for T = -40°C to 85°C and V = 5.0V ± 20%, unless otherwise noted.

Symbol Parameter

Condition

Min

-0.5

Max

Units

V_IL

Input Low Voltage

(Except EA)

0.2 V_CC- 0.1

0.2 V_CC- 0.3

V_CC+ 0.5

V_IL1

V_IH

Input Low Voltage (EA)

Input High Voltage

-0.5

(Except XTAL1, RST)

(XTAL1, RST)

0.2 V_CC+ 0.9

0.7 V_CC

V_IH1

V_CC+ 0.5

Output Low Voltage ⁽¹⁾

(Ports 1,2,3)

Output Low Voltage ⁽¹⁾

(Port 0, ALE, PSEN)

V_OL

_OL= 1.6 mA

0.45

V_OL1

I_OL= 3.2 mA

_OH= -60 µA, V_CC= 5V ± 10%

2.4

Output High Voltage

(Ports 1,2,3, ALE, PSEN)

V_OH

I_OH= -25 µA

I_OH= -10 µA

0.75 V_CC

0.9 V_CC

2.4

I_OH= -800 µA, V_CC= 5V ± 10%

I_OH= -300 µA

Output High Voltage

(Port 0 in External Bus Mode)

V_OH1

0.75 V_CC

0.9 V_CC

I_OH= -80 µA

Logical 0 Input Current

(Ports 1,2,3)

I_IL

I_TL

I_LI

V_IN= 0.45V

V_IN= 2V

-50

µA

Logical 1 to 0 Transition

Current (Ports 1,2,3)

-650

Input Leakage Current

(Port 0, EA)

0.45 < V_IN< V_CC

±10

µA

kΩ

RRST

C_IO

Reset Pulldown Resistor

Pin Capacitance

300

Test Freq. = 1 MHz, T_A= 25°C

Active Mode, 12 MHz

Idle Mode, 12 MHz

V_CC= 6V

µA

Power Supply Current

Power Down Mode ⁽²⁾

6.5

100

I_CC

_CC= 3V

Notes: 1. Under steady state (non-transient) conditions, I_OL

must be externally limited as follows:

Maximum I_OLper port pin: 10 mA

Maximum I_OLper 8 bit port:

Maximum total I_OLfor all output pins: 71 mA

If I_OLexceeds the test condition, V_OLmay exceed the

related specification. Pins are not guaranteed to sink

current greater than the listed test conditions.

2. Minimum V_CCfor Power Down is 2V.

Port 0: 26 mA

Ports 1,2, 3: 15 mA

1-12

AT48801

AC Characteristics

Under operating conditions, load capacitance for Port 0, ALE, and PSEN = 100 pF; load capacitance for all other

outputs = 80 pF.

External Program and Data Memory Characteristics

12 MHz Oscillator

Variable Oscillator

Symbol Parameter

Units

MHz

Min

Max

Min

Max

1/t

Oscillator Frequency

CLCL

ALE Pulse Width

127

- 40

LHLL

CLCL

Address Valid to ALE Low

Address Hold After ALE Low

ALE Low to Valid Instruction In

ALE Low to PSEN Low

PSEN Pulse Width

- 13

- 20

AVLL

LLAX

LLIV

CLCL

233

- 65

CLCL

- 13

- 20

LLPL

CLCL

205

CLCL

PLPH

PLIV

PSEN Low to Valid Instruction In

Input Instruction Hold After PSEN

Input Instruction Float After PSEN

PSEN to Address Valid

Address to Valid Instruction In

PSEN Low to Address Float

RD Pulse Width

145

- 45

- 10

- 55

CLCL

PXIX

PXIZ

CLCL

- 8

PXAV

AVIV

CLCL

312

CLCL

PLAZ

RLRH

WLWH

RLDV

RHDX

RHDZ

LLDV

AVDV

LLWL

AVWL

QVWX

QVWH

WHQX

RLAZ

WHLH

400

- 100

CLCL

WR Pulse Width

CLCL

RD Low to Valid Data In

Data Hold After RD

252

- 90

- 28

CLCL

Data Float After RD

CLCL

ALE Low to Valid Data In

Address to Valid Data In

ALE Low to RD or WR Low

Address to RD or WR Low

Data Valid to WR Transition

Data Valid to WR High

Data Hold After WR

517

585

300

- 150

- 165

+ 50

CLCL

200

203

- 50

- 75

- 20

- 120

- 20

CLCL

433

RD Low to Address Float

RD or WR High to ALE High

123

- 20

+ 25

CLCL

1-13

External Program Memory Read Cycle

External Data Memory Read Cycle

1-14

AT48801

External Data Memory Cycle

External Clock Drive Waveforms

External Clock Drive

Symbol

1/t

Parameter

Oscillator Frequency

Clock Period

High Time

Min

Max

Units

MHz

CLCL

62.5

CLCL

CHCX

CLCX

CLCH

CHCL

Low Time

Rise Time

Fall Time

1-15

Serial Port Timing: Shift Register Mode Test Conditions

The values in this table are valid for V = 5.0V ± 20% and Load Capacitance = 80 pF.

12 MHz Osc

Variable Oscillator

Min Max

12t

Symbol

Parameter

Units

Min

1.0

700

Max

Serial Port Clock Cycle Time

µs

XLXL

CLCL

Output Data Setup to Clock Rising Edge

Output Data Hold After Clock Rising Edge

Input Data Hold After Clock Rising Edge

Clock Rising Edge to Input Data Valid

10t

- 133

- 33

QVXH

XHQX

XHDX

XHDV

CLCL

700

10t

- 133

CLCL

Shift Register Mode Timing Waveforms

Float Waveforms⁽¹⁾

AC Testing Input/Output Waveforms⁽¹⁾

Note: 1. For timing purposes, a port pin is no longer floating

when a 100 mV change from load voltage occurs. A

port pin begins to float when a 100 mV change from

the loaded V_OH/V_OLlevel occurs.

Note: 1. AC Inputs during testing are driven at V_CC- 0.5V

for a logic 1 and 0.45V for a logic 0. Timing meas-

urements are made at V_IHmin. for a logic 1 and

V_ILmax. for a logic 0.

1-16

AT48801

Ordering Information

Speed

(MHz)

Power

Ordering Code

Package

Operation Range

Supply

5V ± 20%

AT48801-16QC

44Q

Commercial

(0°C to 70°C)

AT48801-16QI

44Q

Industrial

(-40°C to 85°C)

Package Type

44 Lead, Plastic Gull Wing Quad Flatpack (PQFP)

44Q

1-17

AT48801-16QC [ATMEL]

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