AT49BV080 [ATMEL]
8-Megabit 1M x 8 Single 2.7-volt Battery-Voltage Flash Memory; 8兆位1M ×8单2.7伏的电池电压闪存
| 型号： | AT49BV080 |
| 厂家： | 
ATMEL |
| 描述： | 8-Megabit 1M x 8 Single 2.7-volt Battery-Voltage Flash Memory |
| 文件： | 总12页 (文件大小：204K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
Single Supply for Read and Write: 2.7V to 3.6V (BV), 3.0V to 3.6V (LV)
Fast Read Access Time - 120 ns
Internal Program Control and Timer
16K bytes Boot Block With Lockout
Fast Erase Cycle Time - 10 seconds
Byte-By-Byte Programming - 30 µs/Byte Typical
Hardware Data Protection
DATA Polling For End Of Program Detection
•
•
•
•
•
•
•
•
Low Power Dissipation
•
8-Megabit
- 25 mA Active Current
- 50 µA CMOS Standby Current
(1M x 8)
Typical 10,000 Write Cycles
Small Packaging
•
•
- 8 x 14 mm CBGA
Single 2.7-volt
Battery-Voltage
Flash Memory
Description
The AT49BV/LV080 are 3-volt-only in-system Flash Memory devices. Their 8 mega-
bits of memory are organized as 1,024,576 words by 8 bits. Manufactured with At-
mel’s advanced nonvolatile CMOS technology, the devices offer access times to 120
ns with power dissipation of just 90 mW over the commercial temperature range.
When the device is deselected, the CMOS standby current is less than 50 µA.
AT49BV080
AT49BV080T
AT49LV080
AT49LV080T
The device contains a user-enabled "boot block" protection feature. Two versions of
the feature are available: the AT49BV/LV080 locates the boot block at lowest order
addresses ("bottom boot"); the AT49BVLV080T locates it at highest order addresses
("top boot").
(continued)
TSOP Top View
Pin Configurations
Type 1
Pin Name
A0 - A19
CE
Function
Addresses
Chip Enable
Output Enable
Write Enable
Reset
OE
WE
RESET
RDY/BUSY
I/O0 - I/O7
Ready/Busy Output
Data Inputs/Outputs
CBGA Top View
SOIC
1
2
3
4
5
6
7
NC
RESET
A11
A10
A9
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VCC
CE
2
3
A12
A13
A14
A15
A16
A17
A18
A19
NC
4
5
A
B
C
D
E
F
A8
6
A5 A8 A11 NC A12 A15 A17
A4 A7 A10 VCC A13 NC A18
A6 A9 RST CE A14 A16 A19
A3 I/O1 NC VCC I/O4 I/O7 NC
A2 A0 I/O3 GND I/O6 OE NC
A1 I/O0 I/O2 GND I/O5 RY/BY WE
A7
7
A6
8
A5
9
A4
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
NC
NC
A3
NC
A2
NC
A1
WE
A0
OE
I/O0
I/O1
I/O2
I/O3
GND
GND
RDY/BUSY
I/O7
I/O6
I/O5
I/O4
VCC
0812A–8/97
Description (Continued)
To allow for simple in-system reprogrammability, the
AT49BV/LV080 does not require high input voltages for
programming. 3-volt-only commands determine the read
and programming operation of the device. Reading data
out of the device is similar to reading from an EPROM.
Reprogramming the AT49BV/LV080 is performed by eras-
ing the entire 8 megabits of memory and then program-
ming on a byte-by-byte basis. The typical byte program-
ming time is a fast 30 µs. The end of a program cycle can
be optionally detected by the DATA polling feature. Once
the end of a byte program cycle has been detected, a new
access for a read or program can begin. The typical num-
ber of program and erase cycles is in excess of 10,000
cycles.
The optional 16K bytes boot block section includes a re-
programming write lock out feature to provide data integ-
rity. The boot sector is designed to contain user secure
code, and when the feature is enabled, the boot sector is
permanently protected from being reprogrammed.
Block Diagram
AT49BV/LV080
DATA INPUTS/OUTPUTS
AT49BV/LV080T
DATA INPUTS/OUTPUTS
I/O7 - I/O0
I/O7 - I/O0
VCC
GND
8
8
OE
WE
CE
DATA LATCH
DATA LATCH
OE, CE, AND WE
LOGIC
INPUT/OUTPUT
BUFFERS
INPUT/OUTPUT
BUFFERS
Y DECODER
X DECODER
Y-GATING
Y-GATING
FFFFFH
03FFFH
00000H
FFFFFH
FC000H
00000H
ADDRESS
INPUTS
MAIN MEMORY
(1008K BYTES)
OPTIONAL BOOT
BLOCK (16K BYTES)
OPTIONAL BOOT
MAIN MEMORY
(1008K BYTES)
BLOCK (16K BYTES)
Device Operation
READ: The AT49BV/LV080 is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-
line control gives designers flexibility in preventing bus
contention.
ternal device command register and is a 4 bus cycle op-
eration (please refer to the Command Definitions table).
The device will automatically generate the required inter-
nal program pulses.
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
ERASURE: Before a byte can be reprogrammed, the
1024K bytes memory array (or 1008K bytes if the boot
block featured is used) must be erased. The erased state
of the memory bits is a logical “1”. The entire device can
be erased at one time by using a 6-byte software code.
The software chip erase code consists of 6-byte load com-
mands to specific address locations with a specific data
pattern (please refer to the Chip Erase Cycle Waveforms).
first. Programming is completed after the specified t cy-
cle time. The DATA polling feature may also be used to
indicate the end of a program cycle.
BP
BOOT BLOCK PROGRAMMING LOCKOUT: The de-
vice has one designated block that has a programming
lockout feature. This feature prevents programming of
data in the designated block once the feature has been
enabled. The size of the block is 16K bytes. This block,
referred to as the boot block, can contain secure code that
is used to bring up the system. Enabling the lockout fea-
ture will allow the boot code to stay in the device while data
in the rest of the device is updated. This feature does not
have to be activated; the boot block’s usage as a write
protected region is optional to the user. The address
range of the AT49BV/LV080 boot block is 00000H to
03FFFH while the address range of the AT49BV/LV080T
boot block is FC000H to FFFFFH.
After the software chip erase has been initiated, the device
will internally time the erase operation so that no external
clocks are required. The maximum time needed to erase
the whole chip is t . If the boot block lockout feature has
EC
been enabled, the data in the boot sector will not be
erased.
BYTE PROGRAMMING: Once the memory array is
erased, the device is programmed (to a logical “0”) on a
byte-by-byte basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can con-
vert “0”s to “1”s. Programming is accomplished via the in-
To activate the lockout feature, a series of six program
commands to specific addresses with specific data must
2
AT49BV/LV080
AT49BV/LV080
Device Operation (Continued)
be performed. Please refer to the Command Definitions
table.
zero. Once the program cycle has completed, I/O6 will
stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the
boot block section is locked out. When the device is in the
software product identification mode (see Software Prod-
uct Identification Entry and Exit sections) a read from ad-
dress location 00002H will show if programming the boot
block is locked out. If the data on I/O0 is low, the boot
block can be programmed; if the data on I/O0 is high, the
program lockout feature has been activated and the block
cannot be programmed. The software product identifica-
tion exit code should be used to return to standard opera-
tion.
RDY/BUSY: An open drain READY/BUSY output pin pro-
vides another method of detecting the end of a program or
erase operation. RDY/BUSY is actively pulled low during
the internal program and erase cycles and is released at
the completion of the cycle. The open drain connection al-
lows for OR - tying of several devices to the same
RDY/BUSY line.
RESET: A RESET input pin is provided to ease some
system applications. When RESET is at a logic high level,
the device is in its standard operating mode. A low level on
the RESET input halts the present device operation and
puts the outputs of the device in a high impedance state.
If the RESET pin makes a high to low transition during a
program or erase operation, the operation may not be suc-
cessfully completed, and the operation will have to be re-
peated after a high level is applied to the RESET pin.
When a high level is reasserted on the RESET pin, the
device returns to the read or standby mode, depending
upon the state of the control inputs. By applying a 12V +
0.5V input signal to the RESET pin the boot block array
can be reprogrammed even if the boot block lockout fea-
ture has been enabled (see Boot Block Programming
Lockout Override section).
BOOT BLOCK PROGRAMMING LOCKOUT OVER-
RIDE: The user can override the boot block programming
lockout by taking the RESET pin to 12 + 0.5 volts. By doing
this, protected boot block data can be altered through a
chip erase, or byte programming. When the RESET pin is
brought back to TTL levels the boot block programming
lockout feature is again active.
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
AT49BV/LV080 in the following ways: (a) V
sense: if
CC
V
is below 1.8V (typical), the program function is inhib-
CC
ited. (b) Program inhibit: holding any one of OE low, CE
high or WE high inhibits program cycles. (c) Noise filter:
pulses of less than 15 ns (typical) on the WE or CE inputs
will not initiate a program cycle.
DATA POLLING: The AT49BV/LV080 features DATA
polling to indicate the end of a program cycle. During a
program cycle an attempted read of the last byte loaded
will result in the complement of the loaded data on I/O7.
Once the program cycle has been completed, true data is
valid on all outputs and the next cycle may begin. DATA
polling may begin at any time during the program cycle.
TOGGLE BIT: I n a d d it io n t o DATA polling, the
AT49BV/LV080 provides another method for determining
the end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from
the device will result in I/O6 toggling between one and
3
Command Definition (in Hex)
Command Bus
Sequence Cycles
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Addr
Data
DOUT
AA
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
1
6
Addr
5555
Read
2AAA
2AAA
55
55
5555
5555
80
5555
Addr
AA
2AAA
2AAA
55
5555
5555
10
Chip Erase
Byte
Program
4
6
3
3
1
5555
5555
5555
5555
XXXX
AA
AA
AA
AA
F0
A0
DIN
Boot Block
Lockout
2AAA
2AAA
2AAA
55
55
55
5555
5555
5555
80
90
F0
5555
AA
55
40
(1)
Product ID
Entry
Product ID
(2)
Exit
Product ID
(2)
Exit
Notes: 1. The 16K byte boot sector has the address range 00000H to 03FFFH for the AT49BV/LV080 and FC000H to FFFFFH for the
AT49BV/LV080T.
2. Either one of the Product ID Exit commands can be used.
Absolute Maximum Ratings*
Temperature Under Bias................. -55°C to +125°C
Storage Temperature...................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
All Output Voltages
This is a stress rating only and functional operation of the
with Respect to Ground .............-0.6V to V
+ 0.6V
CC
device at these or any other conditions beyond those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Voltage on OE
with Respect to Ground ................... -0.6V to +13.5V
4
AT49BV/LV080
AT49BV/LV080
DC and AC Operating Range
AT49BV/LV080-12
AT49BV/LV080-15
0°C - 70°C
AT49BV/LV080-20
0°C - 70°C
Com.
Ind.
0°C - 70°C
Operating
Temperature (Case)
-40°C - 85°C
-40°C - 85°C
-40°C - 85°C
V
Power Supply
2.7V - 3.6V / 3.0V - 3.6V 2.7V - 3.6V / 3.0V - 3.6V 2.7V - 3.6V / 3.0V - 3.6V
CC
Operating Modes
Mode
CE
OE
WE
RESET
Ai
Ai
Ai
I/O
RDY/BUSY
Read
V
V
V
IL
V
V
V
D
D
V
OH
IL
IH
IH
IH
OUT
IN
(2)
Program
V
V
IL
V
OL
IL
IH
Standby/Write
Inhibit
(1)
V
X
X
V
X
High Z
V
OH
IH
IH
Program Inhibit
Program Inhibit
Output Disable
RESET
X
X
V
V
V
V
V
OH
V
OH
V
OH
IH
IH
IH
IH
X
X
X
V
IL
X
V
X
X
High Z
High Z
IH
X
X
V
IL
Product
Identification
A1 - A19 = VIL, A9 = VH, (3)
A0 = VIL
(4)
(4)
Manufacturer Code
Hardware
V
IL
V
IL
V
V
IH
IH
A1 - A19 = VIL, A9 = VH, (3)
A0 = VIH
(4)
Device Code
A0 = VIL, A1 - A19 = VIL
A0 = VIH, A1 - A19 = VIL
Manufacturer Code
(5)
Software
(4)
Device Code
Notes: 1. X can be VIL or VIH.
4. Manufacturer Code: 1FH,
2. Refer to AC Programming Waveforms.
Device Code: 23H (AT49BV/LV080), 27H (AT49BV/LV080T)
5. See details under Software Product Identification Entry/Exit.
3. VH = 12.0V ± 0.5V.
DC Characteristics
Symbol
Parameter
Condition
Min
Max
1
Units
µA
µA
µA
mA
mA
V
I
LI
Input Load Current
Output Leakage Current
V
V
= 0V to V
CC
IN
I
I
I
I
= 0V to V
CC
1
LO
I/O
V
V
V
Standby Current CMOS
Standby Current TTL
Active Current
CE = V - 0.3V to V
CC
50
1
SB1
SB2
CC
CC
CC
CC
CE = 2.0V to V
CC
(1)
f = 5 MHz; I
= 0 mA, V = 3.6V
25
0.6
CC
OUT
CC
V
V
V
V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
IL
2.0
2.4
V
IH
I
I
= 1.6 mA, V = 3.0V
0.45
V
OL
OH
OL
CC
= -100 µA, V = 3.0V
V
OH
CC
Note: 1. ICC in the erase mode is 50 mA.
5
AC Read Characteristics
AT49BV/LV080-12 AT49BV/LV080-15 AT49BV/LV080-20
Min
Max
120
120
50
Min
Max
150
150
70
Min
Max
200
200
100
50
Symbol Parameter
Units
ns
t
t
t
t
Address to Output Delay
CE to Output Delay
ACC
(1)
ns
CE
OE
DF
(2)
OE to Output Delay
0
0
0
0
0
0
ns
(3, 4)
CE or OE to Output Float
30
40
ns
Output Hold from OE, CE or
Address, whichever occurred first
t
0
0
0
ns
OH
AC Read Waveforms (1,2,3,4)
Notes: 1. CE may be delayed up to tACC - tCE after the address
transition without impact on tACC
3. tDF is specified from OE or CE whichever occurs first
(CL = 5 pF).
.
2. OE may be delayed up to tCE - tOE after the falling
edge of CE without impact on tCE or by tACC - tOE
4. This parameter is characterized and is not 100% tested.
after an address change without impact on tACC
.
Input Test Waveforms and Measurement Level
Output Test Load
t , t < 5 ns
R
F
Pin Capacitance (f = 1 MHz, T = 25°C) (1)
Typ
Max
6
Units
pF
Conditions
C
C
4
8
V
V
= 0V
IN
IN
12
pF
= 0V
OUT
OUT
Note: 1. This parameter is characterized and is not 100% tested.
6
AT49BV/LV080
AT49BV/LV080
AC Byte Load Characteristics
Symbol
Parameter
Min
0
Max
Units
ns
t
t
t
t
t
t
t
t
, t
Address, OE Set-up Time
Address Hold Time
AS OES
100
0
ns
AH
CS
CH
WP
DS
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
ns
0
ns
200
100
0
ns
ns
, t
Data, OE Hold Time
Write Pulse Width High
ns
DH OEH
200
ns
WPH
AC Byte Load Waveforms
WE Controlled
CE Controlled
7
Program Cycle Characteristics
Symbol
Parameter
Min
Typ
Max
Units
µs
t
t
t
t
t
t
t
t
Byte Programming Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
30
50
BP
0
ns
AS
100
100
0
ns
AH
ns
DS
DH
WP
WPH
EC
ns
Write Pulse Width
Write Pulse Width High
Erase Cycle Time
200
200
ns
ns
10
seconds
Program Cycle Waveforms
Chip Erase Cycle Waveforms
Note: OE must be high only when WE and CE are both low.
8
AT49BV/LV080
AT49BV/LV080
Data Polling Characteristics (1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
t
t
t
t
Data Hold Time
OE Hold Time
OE to Output Delay
DH
10
ns
OEH
OE
(2)
ns
Write Recovery Time
0
ns
WR
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
Toggle Bit Characteristics (1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
t
t
t
t
t
Data Hold Time
OE Hold Time
OE to Output Delay
OE High Pulse
DH
10
ns
OEH
OE
(2)
ns
150
0
ns
OEHP
WR
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms(1, 2, 3)
Notes: 1. Toggling either OE or CE or both OE and CE will
operate toggle bit. The tOEHP specification must be
met by the toggling input(s).
3. Any address location may be used but the address
should not vary.
2. Beginning and ending state of I/O6 will vary.
9
Software Product
Boot Block Lockout
Identification Entry (1)
Feature Enable Algorithm (1)
LOAD DATA AA
TO
LOAD DATA AA
TO
ADDRESS 5555
ADDRESS 5555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS 2AAA
ADDRESS 2AAA
LOAD DATA 90
TO
LOAD DATA 80
TO
ADDRESS 5555
ADDRESS 5555
ENTER PRODUCT
IDENTIFICATION
MODE (2, 3, 5)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
Software Product
Identification Exit (1)
LOAD DATA 40
TO
ADDRESS 5555
OR
LOAD DATA F0
TO
ANY ADDRESS
LOAD DATA AA
TO
PAUSE 1 second (2)
ADDRESS 5555
EXIT PRODUCT
IDENTIFICATION
MODE (4)
LOAD DATA 55
TO
ADDRESS 2AAA
Notes for boot block lockout feature enable:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
LOAD DATA F0
TO
ADDRESS 5555
2. Boot block lockout feature enabled.
EXIT PRODUCT
IDENTIFICATION
MODE (4)
Notes for software product identification:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A19 = VIL.
Manufacture Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 1FH
Device Code: 23H (AT49BV/LV080), 27H (AT49BV/LV080T)
10
AT49BV/LV080
AT49BV/LV080
Ordering Information
t
I
(mA)
ACC
CC
Ordering Code
Package
Operation Range
(ns)
Active
Standby
120
25
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
AT49BV080-12CC
AT49BV080-12RC
AT48BV080-12TC
42C2
44R
40T
Commercial
(0° to 70°C)
25
25
25
25
25
25
25
25
25
25
25
AT49BV080-12CI
AT49BV080-12RI
AT49BV080-12TI
42C2
44R
40T
Industrial
(-40° to 85°C)
150
200
120
150
200
AT49BV080-15CC
AT49BV080-15RC
AT49BV080-15TC
42C2
44R
40T
Commercial
(0° to 70°C)
AT49BV080-15CI
AT49BV080-15RI
AT49BV080-15TI
42C2
44R
40T
Industrial
(-40° to 85°C)
AT49BV080-20CC
AT49BV080-20RC
AT49BV080-20TC
42C2
44R
40T
Commercial
(0° to 70°C)
AT49BV080-20CI
AT49BV080-20RI
AT49BV080-20TI
42C2
44R
40T
Industrial
(-40° to 85°C)
AT49BV080T-12CC
AT49BV080T-12RC
AT48BV080T-12TC
42C2
44R
40T
Commercial
(0° to 70°C)
AT49BV080T-12CI
AT49BV080T-12RI
AT49BV080T-12TI
42C2
44R
40T
Industrial
(-40° to 85°C)
AT49BV080T-15CC
AT49BV080T-15RC
AT49BV080T-15TC
42C2
44R
40T
Commercial
(0° to 70°C)
AT49BV080T-15CI
AT49BV080T-15RI
AT49BV080T-15TI
42C2
44R
40T
Industrial
(-40° to 85°C)
AT49BV080T-20CC
AT49BV080T-20RC
AT49BV080T-20TC
42C2
44R
40T
Commercial
(0° to 70°C)
AT49BV080T-20CI
AT49BV080T-20RI
AT49BV080T-20TI
42C2
44R
40T
Industrial
(-40° to 85°C)
Package Type
42C2
44R
40T
42-Ball, Plastic Chip-Size Ball Grid Array Package (CBGA) 8 x 14 mm
44-Lead, 0.525" Wide, Plastic Gull Wing Small Outline Package (SOIC/SOP)
40-Lead, Thin Small Outline Package (TSOP)
11
Ordering Information
t
I
(mA)
ACC
CC
Ordering Code
Package
Operation Range
(ns)
Active
Standby
120
25
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
AT49LV080-12CC
AT49LV080-12RC
AT48LV080-12TC
42C2
44R
40T
Commercial
(0° to 70°C)
25
25
25
25
25
25
25
25
25
25
25
AT49LV080-12CI
AT49LV080-12RI
AT49LV080-12TI
42C2
44R
40T
Industrial
(-40° to 85°C)
150
200
120
150
200
AT49LV080-15CC
AT49LV080-15RC
AT49LV080-15TC
42C2
44R
40T
Commercial
(0° to 70°C)
AT49LV080-15CI
AT49LV080-15RI
AT49LV080-15TI
42C2
44R
40T
Industrial
(-40° to 85°C)
AT49LV080-20CC
AT49LV080-20RC
AT49LV080-20TC
42C2
44R
40T
Commercial
(0° to 70°C)
AT49LV080-20CI
AT49LV080-20RI
AT49LV080-20TI
42C2
44R
40T
Industrial
(-40° to 85°C)
AT49LV080T-12CC
AT49LV080T-12RC
AT48LV080T-12TC
42C2
44R
40T
Commercial
(0° to 70°C)
AT49LV080T-12CI
AT49LV080T-12RI
AT49LV080T-12TI
42C2
44R
40T
Industrial
(-40° to 85°C)
AT49LV080T-15CC
AT49LV080T-15RC
AT49LV080T-15TC
42C2
44R
40T
Commercial
(0° to 70°C)
AT49LV080T-15CI
AT49LV080T-15RI
AT49LV080T-15TI
42C2
44R
40T
Industrial
(-40° to 85°C)
AT49LV080T-20CC
AT49LV080T-20RC
AT49LV080T-20TC
42C2
44R
40T
Commercial
(0° to 70°C)
AT49LV080T-20CI
AT49LV080T-20RI
AT49LV080T-20TI
42C2
44R
40T
Industrial
(-40° to 85°C)
Package Type
42C2
44R
40T
42-Ball, Plastic Chip-Size Ball Grid Array Package (CBGA) 8 x 14 mm
44-Lead, 0.525" Wide, Plastic Gull Wing Small Outline Package (SOIC/SOP)
40-Lead, Thin Small Outline Package (TSOP)
12
AT49BV/LV080
相关型号：
©2020 ICPDF网 联系我们和版权申明