AT49BV160C-70TJ [ATMEL]
Flash, 1MX16, 70ns, PDSO48, 12 X 20 MM, PLASTIC, MO-142DD, TSOP1-48;
| 型号： | AT49BV160C-70TJ |
| 厂家： | 
ATMEL |
| 描述： | Flash, 1MX16, 70ns, PDSO48, 12 X 20 MM, PLASTIC, MO-142DD, TSOP1-48 |
| 文件： | 总30页 (文件大小：233K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Single Voltage Read/Write Operation: 2.65V to 3.6V
• Access Time – 70 ns
• Sector Erase Architecture
– Thirty-one 32K Word (64K Bytes) Sectors with Individual Write Lockout
– Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout
• Fast Word Program Time – 12 µs
• Fast Sector Erase Time – 300 ms
• Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming from Any Sector by Suspending Erase
of a Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
• Low-power Operation
16-megabit
(1M x 16)
3-volt Only
Flash Memory
– 12 mA Active
– 13 µA Standby
• VPP Pin for Write Protection
• WP Pin for Sector Protection
• RESET Input for Device Initialization
• Flexible Sector Protection
• TSOP and CBGA Package Options
• Top or Bottom Boot Block Configuration Available
• 128-bit Protection Register
• Minimum 100,000 Erase Cycles
• Common Flash Interface (CFI)
AT49BV160C
AT49BV160CT
Description
The AT49BV160C(T) is a 2.7-volt 16-megabit Flash memory organized as 1,048,576
words of 16 bits each. The memory is divided into 39 sectors for erase operations.
The device is offered in a 48-lead TSOP and a 46-ball CBGA package. The device has
CE and OE control signals to avoid any bus contention. This device can be read or
reprogrammed using a single power supply, making it ideally suited for in-system
programming.
Pin Configurations
Pin Name
A0 - A19
CE
Function
Addresses
Chip Enable
Output Enable
Write Enable
Reset
OE
WE
RESET
VPP
Write Protection
Data Inputs/Outputs
No Connect
I/O0 - I/O15
NC
VCCQ
WP
Output Power Supply
Write Protect
3367D–FLASH–5/04
TSOP Top View
CBGA Top View
Type 1
8
1
2
3
4
5
6
7
A15
A14
A13
A12
A11
A10
A9
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
2
VCCQ
GND
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
3
4
A
B
C
D
E
F
5
6
A13
A14
A15
A16
A11
A10
A8
WE
VPP
RST
WP
A19
A17
A6
A7
A5
A4
A2
7
A8
8
NC
9
A18
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
WE
RESET
VPP
WP
A19
A18
A17
A7
A12
A9
A3
A1
I/O14
I/O5
I/O6
I/O13
I/O11
I/O12
I/O4
I/O2
I/O3
I/O8
I/O9
CE
A0
VCCQ I/O15
I/O0
I/O1
GND
OE
A6
A5
A4
GND
I/O7
VCC I/O10
A3
GND
CE
A2
A1
A0
The device powers on in the read mode. Command sequences are used to place the device in
other operation modes such as program and erase. The device has the capability to protect
the data in any sector (see Flexible Sector Protection section).
To increase the flexibility of the device, it contains an Erase Suspend and Program Suspend
feature. This feature will put the erase or program on hold for any amount of time and let the
user read data from or program data to any of the remaining sectors within the memory.
The VPP pin provides data protection. When the VPP input is below 0.4V, the program and
erase functions are inhibited. When VPP is at 1.5V or above, normal program and erase opera-
tions can be performed.
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AT49BV160C(T)
3367D–FLASH–5/04
AT49BV160C(T)
Block Diagram
I/O0 - I/O15
OUTPUT
BUFFER
INPUT
BUFFER
IDENTIFIER
REGISTER
INPUT
A0 - A19
BUFFER
STATUS
CE
REGISTER
WE
COMMAND
REGISTER
OE
RESET
WP
ADDRESS
LATCH
DATA
COMPARATOR
WRITE STATE
MACHINE
PROGRAM/ERASE
VPP
VOLTAGE SWITCH
Y-DECODER
X-DECODER
Y-GATING
VCC
GND
MAIN
MEMORY
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3367D–FLASH–5/04
Device
Operation
READ: When the AT49BV160C(T) is in the read mode, with CE and OE low and WE high, the
data stored at the memory location determined by the address pins are asserted on the out-
puts. The outputs are put in the high impedance state whenever CE or OE is high. This dual-
line control gives designers flexibility in preventing bus contention.
COMMAND SEQUENCES: When the device is first powered on, it will be in the read mode. In
order to perform other device functions, a series of command sequences are entered into the
device. The command sequences are shown in the “Command Definition” table on page 15
(I/O8 - I/O15 are don’t care inputs for the command codes). The command sequences are
written by applying a low pulse on the WE or CE input with CE or WE low (respectively) and
OE high. The address and data are latched by the first rising edge of CE or WE. Standard
microprocessor write timings are used. The address locations used in the command
sequences are not affected by entering the command sequences.
RESET: A RESET input pin is provided to ease some system applications. When RESET is at
a logic high level, the device is in its standard operating mode. A low level on the RESET input
halts the present device operation and puts the outputs of the device in a high impedance
state. When a high level is reasserted on the RESET pin, the device returns to the read mode,
depending upon the state of the control inputs.
ERASURE: Before a word can be reprogrammed, it must be erased. The erased state of
memory bits is a logical “1”. The individual sectors can be erased by using the Sector Erase
command.
SECTOR ERASE: The device is organized into 39 sectors (SA0 - SA38) that can be individu-
ally erased. The Sector Erase command is a two-bus cycle operation. The sector address and
the D0H Data Input command are latched on the rising edge of WE. The sector erase starts
after the rising edge of WE of the second cycle provided the given sector has not been pro-
tected. The erase operation is internally controlled; it will automatically time to completion. The
maximum time to erase a sector is tSEC. An attempt to erase a sector that has been protected
will result in the operation terminating immediately.
WORD PROGRAMMING: Once a memory sector is erased, it is programmed (to a logical “0”)
on a word-by-word basis. Programming is accomplished via the Internal Device command reg-
ister and is a two-bus cycle operation. The device will automatically generate the required
internal program pulses.
Any commands written to the chip during the embedded programming cycle will be ignored. If
a hardware reset happens during programming, the data at the location being programmed
will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase
operations can convert “0”s to “1”s. Programming is completed after the specified tBP cycle
time. If the program status bit is a “1”, the device was not able to verify that the program oper-
ation was performed successfully. The status register indicates the programming status. While
the program sequence executes, status bit I/O7 is “0”. While programming, the only valid com-
mands are Read Status Register, Program Suspend and Program Resume.
VPP PIN: The circuitry of the AT49BV160C(T) is designed so that the device cannot be pro-
grammed or erased if the VPP voltage is less that 0.4V. When VPP is at 1.5V or above, normal
program and erase operations can be performed. The VPP pin cannot be left floating.
READ STATUS REGISTER: The status register indicates the status of device operations and
the success/failure of that operation. The Read Status Register command causes subsequent
reads to output data from the status register until another command is issued. To return to
reading from the memory, issue a Read command.
The status register bits are output on I/O7 - I/O0. The upper byte, I/O15 - I/O8, outputs 00H
when a Read Status Register command is issued.
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AT49BV160C(T)
3367D–FLASH–5/04
AT49BV160C(T)
The contents of the status register [SR7:SR0] are latched on the falling edge of OE or CE
(whichever occurs last), which prevents possible bus errors that might occur if status register
contents change while being read. CE or OE must be toggled with each subsequent status
read, or the status register will not indicate completion of a Program or Erase operation.
When the Write State Machine (WSM) is active, SR7 will indicate the status of the WSM; the
remaining bits in the status register indicate whether the WSM was successful in performing
the preferred operation (see Table 1).
Table 1. Status Register Bit Definition
WSMS
7
ESS
6
ES
5
PS
4
VPPS
3
PSS
2
SLS
1
R
0
Notes
SR7 WRITE STATE MACHINE STATUS (WSMS)
Check Write State Machine bit first to determine Word Program
or Sector Erase completion, before checking program or erase
status bits.
1 = Ready
0 = Busy
SR6 = ERASE SUSPEND STATUS (ESS)
1 = Erase Suspended
When Erase Suspend is issued, WSM halts execution and sets
both WSMS and ESS bits to “1” – ESS bit remains set to “1” until
an Erase Resume command is issued.
0 = Erase In Progress/Completed
SR5 = ERASE STATUS (ES)
1 = Error in Sector Erase
0 = Successful Sector Erase
When this bit is set to “1”, WSM has applied the max number of
erase pulses to the sector and is still unable to verify successful
sector erasure.
SR4 = PROGRAM STATUS (PS)
1 = Error in Programming
When this bit is set to “1”, WSM has attempted but failed to
program a word
0 = Successful Programming
SR3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
The VPP status bit does not provide continuous indication of VPP
level. The WSM interrogates VPP level only after the Program or
Erase command sequences have been entered and informs the
system if VPP has not been switched on. The VPP is also checked
before the operation is verified by the WSM.
SR2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
When Program Suspend is issued, WSM halts execution and
sets both WSMS and PSS bits to “1”. PSS bit remains set to “1”
until a Program Resume command is issued.
0 = Program in Progress/Completed
SR1 = SECTOR LOCK STATUS
If a Program or Erase operation is attempted to one of the locked
sectors, this bit is set by the WSM. The operation specified is
aborted and the device is returned to read status mode.
1 = Prog/Erase attempted on a locked sector; Operation aborted.
0 = No operation to locked sectors
SR0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
This bit is reserved for future use and should be masked out
when polling the status register.
Note:
1. A Command Sequence Error is indicated when SR1, SR3, SR4 and SR5 are set.
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3367D–FLASH–5/04
CLEAR STATUS REGISTER: The WSM can set status register bits 1 through 7 and can clear
bits 2, 6 and 7; but, the WSM cannot clear status register bits 1, 3, 4 or 5. Because bits 1, 3, 4
and 5 indicate various error conditions, these bits can be cleared only through the Clear Status
Register command. By allowing the system software to control the resetting of these bits, sev-
eral operations may be performed (such as cumulatively programming several addresses or
erasing multiple sectors in sequence) before reading the status register to determine if an
error occurred during those operations. The status register should be cleared before beginning
another operation. The Read command must be issued before data can be read from the
memory array. The status register can also be cleared by resetting the device.
FLEXIBLE SECTOR PROTECTION: The AT49BV160C(T) offers two sector protection
modes, the Softlock and the Hardlock. The Softlock mode is optimized as sector protection for
sectors whose content changes frequently. The Hardlock protection mode is recommended
for sectors whose content changes infrequently. Once either of these two modes is enabled,
the contents of the selected sector is read-only and cannot be erased or programmed. Each
sector can be independently programmed for either the Softlock or Hardlock sector protection
mode. At power-up and reset, all sectors have their Softlock protection mode enabled.
SOFTLOCK AND UNLOCK: The Softlock protection mode can be disabled by issuing a two-
bus cycle Unlock command to the selected sector. Once a sector is unlocked, its contents can
be erased or programmed. To enable the Softlock protection mode, a two-bus cycle Softlock
command must be issued to the selected sector.
HARDLOCK AND WRITE PROTECT: The Hardlock sector protection mode operates in con-
junction with the Write Protect (WP) pin. The Hardlock sector protection mode can be enabled
by issuing a two-bus cycle Hardlock Software command to the selected sector. The state of
the Write Protect pin affects whether the Hardlock protection mode can be overridden.
•
When the WP pin is low and the Hardlock protection mode is enabled, the sector cannot
be unlocked and the contents of the sector is read-only.
•
When the WP pin is high, the Hardlock protection mode is overridden and the sector can
be unlocked via the Unlock command.
To disable the Hardlock sector protection mode, the chip must be either reset or power cycled.
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AT49BV160C(T)
3367D–FLASH–5/04
AT49BV160C(T)
Table 2. Hardlock and Softlock Protection Configurations in Conjunction with WP
Erase/
Hard-
lock
Soft-
lock
Prog
Allowed?
VPP
WP
0
Comments
VCC/5V
0
0
0
1
Yes
No
No sector is locked
VCC/5V
0
Sector is Softlocked. The Unlock command can
unlock the sector.
VCC/5V
0
1
1
No
Hardlock protection mode is enabled. The sector
cannot be unlocked.
V
CC/5V
CC/5V
1
1
0
0
0
1
Yes
No
No sector is locked.
V
Sector is Softlocked. The Unlock command can
unlock the sector.
V
CC/5V
CC/5V
1
1
x
1
1
x
0
1
x
Yes
No
No
Hardlock protection mode is overridden and the
sector is not locked.
V
Hardlock protection mode is overridden and the
sector can be unlocked via the Unlock command.
VIL
Erase and Program Operations cannot be
performed.
Figure 1. Sector Locking State Diagram
UNLOCKED
LOCKED
60h/
D0h
60h/01h
[000]
[001]
Power-Up/Reset
Default
60h/
2Fh
WP = VIL = 0
Hardlocked
[011]
60h/
01h
Hardlocked is disabled by
60h/D0h
WP
= VIH
[110]
[111]
60h/
2Fh
WP = VIH = 1
60h/
2Fh
Power-Up/Reset
Default
60h/
D0h
60h/
01h
[100]
[101]
60h/D0h = Unlock Command
60h/01h = Softlock Command
60h/2Fh = Hardlock Command
Notes: 1. The notation [X, Y, Z] denotes the locking state of a sector. The current locking state of a sector is defined by the state of WP
and the two bits of the sector-lock status D[1:0].
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3367D–FLASH–5/04
SECTOR PROTECTION DETECTION: A software method is available to determine if the sec-
tor protection Softlock or Hardlock features are enabled. When the device is in the software
product identification mode, a read from the I/O0 and I/O1 at address location 00002H within a
sector will show if the sector is unlocked, softlocked, or hardlocked.
Table 3. Sector Protection Status
I/O1
0
I/O0
0
Sector Protection Status
Sector Not Locked
0
1
Softlock Enabled
1
0
Hardlock Enabled
1
1
Both Hardlock and Softlock Enabled
ERASE SUSPEND/ERASE RESUME: The Erase Suspend command allows the system to
interrupt a sector erase operation and then program or read data from a different sector within
the memory. After the Erase Suspend command is given, the device requires a maximum time
of 15 µs to suspend the erase operation. After the erase operation has been suspended, the
system can then read data or program data to any other sector within the device. An address
is not required during the Erase Suspend command. During a sector erase suspend, another
sector cannot be erased. To resume the sector erase operation, the system must write the
Erase Resume command. The Erase Resume command is a one-bus cycle command. The
only valid commands while erase is suspended are Read Status Register, Product ID Entry,
CFI Query, Program, Program Resume, Erase Resume, Sector Softlock/Hardlock, Sector
Unlock.
PROGRAM SUSPEND/PROGRAM RESUME: The Program Suspend command allows the
system to interrupt a programming operation and then read data from a different word within
the memory. After the Program Suspend command is given, the device requires a maximum
of 20 µs to suspend the programming operation. After the programming operation has been
suspended, the system can then read data from any other word within the device. An address
is not required during the program suspend operation. To resume the programming operation,
the system must write the Program Resume command. The program suspend and resume are
one-bus cycle commands. The command sequence for the erase suspend and program sus-
pend are the same and the command sequence for the erase resume and program resume
are the same. The only other valid commands while program is suspended are Read Status
Register, Product ID Entry, CFI Query and Program Resume.
PRODUCT IDENTIFICATION: The product identification mode identifies the device and man-
ufacturer as Atmel. It may be accessed a software operation. For details, see “Operating
Modes” on page 19.
128-BIT PROTECTION REGISTER: The AT49BV160C(T) contains a 128-bit register that can
be used for security purposes in system design. The protection register is divided into two 64-
bit sectors. The two sectors are designated as sector A and sector B. The data in sector A is
non-changeable and is programmed at the factory with a unique number. The data in sector B
is programmed by the user and can be locked out such that data in the sector cannot be repro-
grammed. To program sector B in the protection register, the two-bus cycle Program
Protection Register command must be used as shown in the “Command Definition” table on
page 15. To lock out sector B, the two-bus cycle Lock Protection Register command must be
used as shown in the “Command Definition” table. Data bit D1 must be zero during the second
bus cycle. All other data bits during the second bus cycle are don’t cares. To determine
whether sector B is locked out, use the status of sector B protection command. If data bit D1 is
zero, sector B is locked. If data bit D1 is one, sector B can be reprogrammed. Please see the
“Protection Register Addressing Table” on page 16 for the address locations in the protection
8
AT49BV160C(T)
3367D–FLASH–5/04
AT49BV160C(T)
register. To read the protection register, the Product ID Entry command is given followed by a
normal read operation from an address within the protection register. After determining
whether sector B is protected or not, or reading the protection register, the Read command
must be given to return to the read mode.
CFI: Common Flash Interface (CFI) is a published, standardized data structure that may be
read from a flash device. CFI allows system software to query the installed device to deter-
mine the configurations, various electrical and timing parameters and functions supported by
the device. CFI is used to allow the system to learn how to interface to the flash device most
optimally. The two primary benefits of using CFI are ease of upgrading and second source
availability. The command to enter the CFI Query mode is a one-bus cycle command which
requires writing data 98h to any address. The CFI Query command can be written when the
device is ready to read data or can also be written when the part is in the product ID mode.
Once in the CFI Query mode, the system can read CFI data at the addresses given in Table 4
on page 25. To return to the read mode, issue the Read command.
HARDWARE DATA PROTECTION: The Hardware Data Protection feature protects against
inadvertent programs to the AT49BV160C(T) in the following ways: (a) VCC sense: if VCC is
below 1.8V (typical), the program function is inhibited. (b) VCC power-on delay: once VCC has
reached the VCC sense level, the device will automatically time out 10 ms (typical) before pro-
gramming. (c) Program inhibit: holding any one of OE low, CE high or WE high inhibits
program cycles. (d) Program inhibit: VPP is less than VILPP. (e) VPP power-on delay: once VPP
has reached 0.9V, program and erase operations are inhibited for 100 ns.
INPUT LEVELS: While operating with a 2.65V to 3.6V power supply, the address inputs and
control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the
operation of the device. The I/O lines can only be driven from 0 to VCCQ + 0.6V.
OUTPUT LEVELS: For the AT49BV160C(T), output high levels (VOH) are equal to VCCQ - 0.1V
(not VCC). For 2.65V - 3.6V output levels, VCCQ must be tied to VCC. For 1.8V - 2.2V output lev-
els, VCCQ must be regulated to 2.0V 10ꢀ, while VCC must be regulated to 2.65V - 3.0V (for
minimum power).
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3367D–FLASH–5/04
Word Program Flowchart
Word Program Procedure
Bus
Operation
Start
Command
Comments
Write
Program
Setup
Data = 40
Addr = Location to program
Write 40,
(Setup)
Word Address
Write
Read
Idle
Data
None
None
Data = Data to program
Addr = Location to program
Write Data,
Word Address
(Confirm)
Status register data: Toggle CE or
OE to update status register
Program
Suspend
Loop
Check SR7
Read Status
Register
1 = WSM Ready
0 = WSM Busy
No
Yes
0
Repeat for subsequent Word Program operations.
SR7 =
1
Suspend?
Full status register check can be done after each program, or after a
sequence of program operations.
Write FF after the last operation to set to the Read state.
Full Status
Check
(If Desired)
Program
Complete
Full Status Check Flowchart
Full Status Check Procedure
Bus
Operation
Read Status
Register
Command
Comments
Idle
None
Check SR3:
1 = VPP Error
1
1
1
VPP Range
Error
SR3 =
0
Idle
Idle
None
None
Check SR4:
1 = Data Program Error
Check SR1:
1 = Sector locked; operation aborted
Program
Error
SR4 =
0
SR3 MUST be cleared before the Write State Machine allows further program
attempts.
If an error is detected, clear the status register before continuing operations –
only the Clear Status Register command clears the status register error bits.
Device
Protect Error
SR1 =
0
Program
Successful
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AT49BV160C(T)
3367D–FLASH–5/04
AT49BV160C(T)
Program Suspend/Resume Flowchart
Program Suspend/Resume Procedure
Bus
Operation
Start
Command
Comments
Write
Write
Read
Read
Status
Data = 70
Addr = Any address
Write B0
(Program Suspend)
Any Address
Program
Suspend
Data = B0
Addr = Any address
Write 70
(Read Status)
Any Address
None
None
None
Status register data: Toggle CE or
OE to update status register
Addr = Any address
Read Status
Register
Idle
Idle
Check SR7
1 = WSM Ready
0 = WSM Busy
0
SR7 =
Check SR2
1
1 = Program suspended
0 = Program completed
0
Program
Completed
SR2 =
1
Write
Read Array
None
Data = FF
Addr = Any address
Read
Write
Read data from any word in the memory
Write FF
(Read Array)
Program
Resume
Data = D0
Addr = Any address
(Read
Array)
Read
Data
Write FF
Read
Data
Done
Reading
No
Yes
Write D0
Any Address
(Program Resume)
Program
Resumed
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3367D–FLASH–5/04
Erase Suspend/Resume Procedure
Erase Suspend/Resume Flowchart
Bus
Operation
Start
Command
Comments
Write
Read
Status
Data = 70
Write B0,
(Erase Suspend)
Any Address
Addr = Any address
Write
Read
Erase
Suspend
Data = B0
Write 70,
(Read Status)
Addr = Any address
Any Address
None
None
None
Status register data: Toggle CE or
OE to update status register
Addr = Any address
Read Status
Register
0
Idle
Idle
Check SR7
SR7 =
1 = WSM Ready
0 = WSM Busy
1
0
Erase
Completed
SR6 =
1
Check SR6
1 = Erase suspended
0 = Erase completed
Write FF
Write
Read or
Program
Data = FF or 40
Addr = Any address
Read
Data
(Read Array)
Read or
Write
None
Read or program data from/to sector other
than the one being erased
0
Done
Write
Program
Resume
Data = D0
Reading
Addr = Any address
1
Write D0,
Any Address
(Erase Resume)
(Read Array)
Write FF
Erase
Resumed
Read Array
Data
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AT49BV160C(T)
3367D–FLASH–5/04
AT49BV160C(T)
Sector Erase Procedure
Sector Erase Flowchart
Bus
Operation
Start
Command
Comments
Write
Sector
Erase
Setup
Data = 20
Write 20,
Sector Address
(
Sector Erase)
Addr = Sector to be erased (SA)
Write D0,
Sector Address
Write
Read
Idle
Erase
Confirm
Data = D0
(Erase Confirm)
Addr = Sector to be erased (SA)
Suspend
Erase
Loop
Read Status
Register
None
Status register data: Toggle CE or
OE to update status register data
No
None
Check SR7
0
Yes
Suspend
Erase
SR7
=
1 = WSM Ready
0 = WSM Busy
1
Full Erase
Status Check
(If Desired)
Repeat for subsequent sector erasures.
Full status register check can be done after each sector erase, or after a
sequence of sector erasures.
Write FF after the last operation to enter read mode.
Sector
Erase
Complete
Full Erase Status Check Flowchart
Full Erase Status Check Procedure
Bus
Operation
Read Status
Register
Command
Comments
Idle
None
Check SR3:
1 = VPP Range Error
1
VPP Range
Error
SR3 =
0
Idle
Idle
Idle
None
None
None
Check SR4, SR5:
Both 1 = Command Sequence Error
1,1
1
Command
=
SR4, SR5
0
Sequence Error
Check SR5:
1 = Sector Erase Error
Sector
Erase
SR5
SR1
=
Error
0
0
Check SR1:
1 = Attempted erase of locked sector;
erase aborted.
1
Sector Locked
Error
=
SR1, SR3 must be cleared before the Write State Machine allows further
erase attempts.
Sector Erase
Successful
Only the Clear Status Register command clears SR1, SR3, SR4, SR5.
If an error is detected, clear the status register before attempting an
erase retry or other error recovery.
13
3367D–FLASH–5/04
Protection Register Programming Procedure
Protection Register Programming
Flowchart
Bus
Operation
Command
Comments
Start
Write
Program
Data = C0
PR Setup
Addr = First Location to Program
Write C0,
(Program Setup)
PR Address
Write
Read
Idle
Protection
Program
Data = Data to Program
Addr = Location to Program
Write PR
(Confirm Data)
Address & Data
None
Status register data: Toggle CE or
OE to update status register data
Read Status
Register
None
Check SR7
1 = WSM Ready
0 = WSM Busy
0
SR7
1
=
Program Protection Register operation addresses must be within the
protection register address space. Addresses outside this space will
return an error.
Full Status
Check
(If Desired)
Repeat for subsequent programming operations.
Full status register check can be done after each program, or after a
sequence of program operations.
Program
Complete
Write FF after the last operation to return to the Read mode.
Full Status Check Flowchart
Full Status Check Procedure
Read Status
Register Data
Bus
Operation
Command
Comments
Idle
None
Check SR1, SR3, SR4:
0,1,1 = VPP Range Error
1
SR3, SR4
0
=
VPP Range Error
Program Error
Idle
Idle
None
None
Check SR1, SR3, SR4:
0,0,1 = Programming Error
1
1
SR3, SR4 =
0
Check SR1, SR3, SR4:
1, 0,1 = Sector locked; operation
aborted
Register Locked;
Program Aborted
SR3 must be cleared before the Write State Machine allows further
program attempts.
=
SR3, SR4
0
Only the Clear Status Register command clears SR1, SR3, SR4.
Program
Successful
If an error is detected, clear the status register before attempting a
program retry or other error recovery.
14
AT49BV160C(T)
3367D–FLASH–5/04
AT49BV160C(T)
Command Definition in Hex(1)
1st Bus
Cycle
2nd Bus
Cycle
Command
Sequence
Bus
Cycles
Addr
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
Data
FF
20
Addr
Data
Read
1
2
2
1
1
1
2
2
2
2
1
2
2
2
1
Sector Erase/Confirm
Word Program
SA(2)
Addr
D0
40/10
B0
D0
90
DIN
Erase/Program Suspend
Erase/Program Resume
Product ID Entry
Sector Softlock
60
SA(2)
SA(2)
SA(2)
XX
01
2F
D0
Sector Hardlock
60
Sector Unlock
60
(3)
Read Status Register
Clear Status Register
Program Protection Register
Lock Protection Register – Sector B
Status of Sector B Protection
CFI Query
70
DOUT
50
C0
C0
90
Addr
80
DIN
FFFD
(4)
80
DOUT
98
Notes: 1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). I/O15 - I/O8 are don’t care. The ADDRESS
FORMAT shown for each bus cycle is as follows: A7 - A0 (Hex). Address A19 through A8 are don’t care.
2. SA = sector address. Any word address within a sector can be used to designate the sector address (see pages 17 and 18
for details).
3. The status register bits are output on I/O7 - I/O0.
4. If data bit D1 is “0”, sector B is locked. If data bit D1 is “1”, sector B can be reprogrammed.
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature under Bias ................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on VPP
with Respect to Ground...................................-0.6V to +13.0V
15
3367D–FLASH–5/04
Protection Register Addressing Table
Word
Use
Factory
Factory
Factory
Factory
User
Sector
A7
A6
0
A5
0
A4
0
A3
0
A2
0
A1
0
A0
1
0
1
2
3
4
5
6
7
A
A
A
A
B
B
B
B
1
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
1
0
0
0
0
1
0
1
User
1
0
0
0
0
1
1
0
User
1
0
0
0
0
1
1
1
User
1
0
0
0
1
0
0
0
Note:
All address lines not specified in the above table must be “0” when accessing the protection register, i.e., A19 - A8 = 0.
16
AT49BV160C(T)
3367D–FLASH–5/04
AT49BV160C(T)
AT49BV160C – Sector Address Table
Sector
Size (Bytes/Words)
Address Range (A19 - A0)
SA0
8K/4K
00000 - 00FFF
01000 - 01FFF
02000 - 02FFF
03000 - 03FFF
04000 - 04FFF
05000 - 05FFF
06000 - 06FFF
07000 - 07FFF
08000 - 0FFFF
10000 - 17FFF
18000 - 1FFFF
20000 - 27FFF
28000 - 2FFFF
30000 - 37FFF
38000 - 3FFFF
40000 - 47FFF
48000 - 4FFFF
50000 - 57FFF
58000 - 5FFFF
60000 - 67FFF
68000 - 6FFFF
70000 - 77FFF
78000 - 7FFFF
80000 - 87FFF
88000 - 8FFFF
90000 - 97FFF
98000 - 9FFFF
A0000 - A7FFF
A8000 - AFFFF
B0000 - B7FFF
B8000 - BFFFF
C0000 - C7FFF
C8000 - CFFFF
D0000 - D7FFF
D8000 - DFFFF
E0000 - E7FFF
E8000 - EFFFF
F0000 - F7FFF
F8000 - FFFFF
SA1
8K/4K
SA2
8K/4K
SA3
8K/4K
SA4
8K/4K
SA5
8K/4K
SA6
8K/4K
SA7
8K/4K
SA8
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
17
3367D–FLASH–5/04
AT49BV160CT – Sector Address Table
x16
Sector
SA0
Size (Bytes/Words)
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
8K/4K
Address Range (A19 - A0)
00000 - 07FFF
08000 - 0FFFF
10000 - 17FFF
18000 - 1FFFF
20000 - 27FFF
28000 - 2FFFF
30000 - 37FFF
38000 - 3FFFF
40000 - 47FFF
48000 - 4FFFF
50000 - 57FFF
58000 - 5FFFF
60000 - 67FFF
68000 - 6FFFF
70000 - 77FFF
78000 - 7FFFF
80000 - 87FFF
88000 - 8FFFF
90000 - 97FFF
98000 - 9FFFF
A0000 - A7FFF
A8000 - AFFFF
B0000 - B7FFF
B8000 - BFFFF
C0000 - C7FFF
C8000 - CFFFF
D0000 - D7FFF
D8000 - DFFFF
E0000 - E7FFF
E8000 - EFFFF
F0000 - F7FFF
F8000 - F8FFF
F9000 - F9FFF
FA000 - FAFFF
FB000 - FBFFF
FC000 - FCFFF
FD000 - FDFFF
FE000 - FEFFF
FF000 - FFFFF
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
8K/4K
8K/4K
8K/4K
8K/4K
8K/4K
8K/4K
8K/4K
18
AT49BV160C(T)
3367D–FLASH–5/04
AT49BV160C(T)
DC and AC Operating Range
AT49BV160C(T)-70
-40°C - 85°C
Operating
Temperature (Case)
Ind.
VCC Power Supply
2.65V to 3.6V
Operating Modes
Mode
CE
VIL
VIL
VIH
X
OE
VIL
VIH
X(1)
X
WE
VIH
VIL
X
RESET
VIH
VPP
X
Ai
Ai
Ai
X
I/O
Read
DOUT
DIN
Program/Erase(2)
Standby/Program Inhibit
VIH
VIHPP
X
(5)
VIH
High-Z
VIH
X
VIH
X
Program Inhibit
X
VIL
X
VIH
X
(6)
X
X
VIH
VILPP
X
Output Disable
Reset
X
VIH
X
X
VIH
High-Z
High-Z
X
X
VIL
X
X
A0 = VIL, A1 - A19 = VIL
A0 = VIH, A1 - A19 = VIL
Manufacturer Code(4)
Device Code(4)
Product Identification Software
VIH
Notes: 1. X can be VIL or VIH.
2. Refer to AC programming waveforms on page 24.
3. VH = 12.0V 0.5V.
4. Manufacturer Code: 001FH, Device Code: 88C3H – AT49BV160C; 88C2H – AT49BV160CT
5. VIHPP (min) = 0.9V; VIHPP (max) = 1.95V.
6. VILPP (max) = 0.4V.
19
3367D–FLASH–5/04
DC Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
10
Units
µA
µA
µA
mA
mA
µA
V
ILI
Input Load Current
VIN = 0V to VCC
ILO
Output Leakage Current
VCC Standby Current CMOS
VCC Active Read Current
VCC Programming Current
VPP Input Load Current
Input Low Voltage
VI/O = 0V to VCC
10
ISB
CE = VCC - 0.3V to VCC
f = 5 MHz; IOUT = 0 mA
13
12
25
(1)
ICC
25
ICC1
IPP1
VIL
45
10
0.4
VIH
Input High Voltage
VCCQ - 0.2
VCCQ - 0.1
V
VOL
VOH
Output Low Voltage
IOL = 100 µA
IOH = -100 µA
0.10
V
Output High Voltage
V
Note:
1. In the erase mode, ICC is 65 mA.
20
AT49BV160C(T)
3367D–FLASH–5/04
AT49BV160C(T)
AC Read Characteristics
AT49BV160C(T)-70
Symbol
tRC
Parameter
Min
Max
Units
ns
Read Cycle Time
70
tACC
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
70
70
20
25
ns
(1)
tCE
ns
(2)
tOE
0
0
ns
(3)(4)
tDF
ns
Output Hold from OE, CE or Address,
whichever occurred first
tOH
tRO
0
ns
ns
RESET to Output Delay
100
AC Read Waveforms(1)(2)(3)(4)
tRC
ADDRESS
CE
ADDRESS VALID
tCE
tOE
OE
tDF
tOH
tACC
tRO
RESET
HIGH Z
OUTPUT
VALID
OUTPUT
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC
.
.
3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100ꢀ tested.
21
3367D–FLASH–5/04
Input Test Waveforms and Measurement Level
VCC
VCC/2
0V
tR, tF < 5 ns
Output Test Load
VCCQ
15
15
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
Typ
4
Max
6
Units
pF
Conditions
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
This parameter is characterized and is not 100ꢀ tested.
22
AT49BV160C(T)
3367D–FLASH–5/04
AT49BV160C(T)
AC Word Load Characteristics
Symbol
tAS, tOES
tAH
Parameter
Min
45
0
Max
Units
ns
Address, OE Setup Time
Address Hold Time
ns
tCS
Chip Select Setup Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Setup Time
0
ns
tCH
0
ns
tWP
40
45
0
ns
tDS
ns
tDH, tOEH
tWPH
Data, OE Hold Time
Write Pulse Width High
ns
30
ns
AC Word Load Waveforms
WE Controlled
CE Controlled
23
3367D–FLASH–5/04
Program Cycle Characteristics
Symbol
Parameter
Min
Typ
Max
Units
µs
tBP
Word Programming Time
Address Setup Time
12
120
tAS
45
0
ns
tAH
Address Hold Time
ns
tDS
Data Setup Time
45
0
ns
tDH
Data Hold Time
ns
tWP
Write Pulse Width
40
30
70
500
ns
tWPH
tWC
Write Pulse Width High
Write Cycle Time
ns
ns
tRP
Reset Pulse Width
ns
tSEC1
tSEC2
tES
Sector Erase Cycle Time (4K Word Sectors)
Sector Erase Cycle Time (32K Word Sectors)
Erase Suspend Time
Program Suspend Time
0.3
0.8
3.0
6.0
15
seconds
seconds
µs
tPS
20
µs
Program Cycle Waveforms
PROGRAM CYCLE
OE
CE
t
t
BP
WP
WE
t
WPH
t
DH
t
t
AH
AS
ADDRESS
A0 - A19
DATA
XX(1)
t
WC
t
DS
INPUT DATA
Note 3
Sector Erase Cycle Waveforms
(2)
OE
CE
t
WP
t
WE
WPH
t
DH
t
t
AS
AH
XX(1)
SA(4)
A0-A19
DATA
t
t
DS
WC
t
EC
D0
WORD
20
WORD
0
1
Notes: 1. Any address can be used to load the data.
2. OE must be high only when WE and CE are both low.
3. The data can be 40H or 10H.
4. The address depends on what sector is to be erased.
24
AT49BV160C(T)
3367D–FLASH–5/04
AT49BV160C(T)
Table 4. Common Flash Interface Definition
Address
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
AT49BV160CT
0051h
0052h
0059h
0003h
0000h
0041h
0000h
0000h
0000h
0000h
0000h
0027h
0036h
00B5h
00C5h
0004h
0000h
000Ah
0000h
0003h
0000h
0003h
0000h
0015h
0001h
0000h
0000h
0000h
0002h
001Eh
0000h
0000h
0001h
0007h
0000h
0020h
0000h
AT49BV160C
0051h
0052h
0059h
0003h
0000h
0041h
0000h
0000h
0000h
0000h
0000h
0027h
0036h
00B5h
00C5h
0004h
0000h
000Ah
0000h
0003h
0000h
0003h
0000h
0015h
0001h
0000h
0000h
0000h
0002h
0007h
0000h
0020h
0000h
001Eh
0000h
0000h
0001h
“Q”
“R”
“Y”
VCC min write/erase
VCC max write/erase
VPP min voltage
VPP max voltage
Typ word write – 12 µs
Typ sector erase, 1,000 ms
Typ chip erase, not supported
Max word write/typ time
n/a
Max sector erase/typ sector erase
Max chip erase/ typ chip erase
Device size
x16 device
x16 device
Multiple byte write not supported
Multiple byte write not supported
2 regions, x = 2
64K bytes, Y = 30 (Top); 8K bytes, Y = 7 (Bottom)
64K bytes, Y = 30 (Top); 8K bytes, Y = 7 (Bottom)
64K bytes, Z = 256 (Top); 8K bytes, Z = 32 (Bottom)
64K bytes, Z = 256 (Top); 8K bytes, Z = 32 (Bottom)
8K bytes, Y = 7 (Top); 64K bytes, Y = 30 (Bottom)
8K bytes, Y = 7 (Top); 64K bytes, Y = 30 (Bottom)
8K bytes, Z = 32 (Top); 64K bytes, Z = 256 (Bottom)
8K bytes, Z = 32 (Top); 64K bytes, Z = 256 (Bottom)
25
3367D–FLASH–5/04
Table 4. Common Flash Interface Definition (Continued)
Address
AT49BV160CT
AT49BV160C
VENDOR SPECIFIC EXTENDED QUERY
41h
42h
43h
44h
45h
46h
0050h
0052h
0049h
0031h
0030h
0086h
0050h
0052h
0049h
0031h
0030h
0086h
“P”
“R”
“I”
Major version number, ASCII
Minor version number, ASCII
Bit 0 – chip erase supported, 0 – no, 1 – yes
Bit 1 – erase suspend supported, 0 – no, 1 – yes
Bit 2 – program suspend supported, 0 – no, 1 – yes
Bit 3 – simultaneous operations supported,
0 – no, 1 – yes
Bit 4 – burst mode read supported, 0 – no, 1 – yes
Bit 5 – page mode read supported, 0 – no, 1 – yes
Bit 6 – queued erase supported, 0 – no, 1 – yes
Bit 7 – protection bits supported, 0 – no, 1 – yes
47h
48h
0000h
0000h
0001h
0000h
Bit 8 – top (“0”) or bottom (“1”) boot sector device undefined bits are “0”
Bit 0 – 4 word linear burst with wrap around,
0 – no, 1 – yes
Bit 1 – 8 word linear burst with wrap around,
0 – no, 1 – yes
Bit 2 – continuos burst, 0 - no, 1 - yes
Undefined bits are “0”
49h
0000h
0000h
Bit 0 – 4 word page, 0 – no, 1 – yes
Bit 1 – 8 word page, 0 – no, 1 – yes
Undefined bits are “0”
4Ah
4Bh
4Ch
0080h
0003h
0003h
0080h
0003h
0003h
Location of protection register lock byte, the
section’s first byte
# of bytes in the factory prog section of prot
register – 2*n
# of bytes in the user prog section of prot
register – 2*n
26
AT49BV160C(T)
3367D–FLASH–5/04
AT49BV160C(T)
AT49BV160C(T) Ordering Information
I
CC (mA)
tACC
(ns)
Active
Standby
Ordering Code
AT49BV160C-70CI
AT49BV160C-70TI
AT49BV160CT-70CI
AT49BV160CT-70TI
Package
46C3
48T
Operation Range
Industrial
70
25
0.025
0.025
(-40° to 85° C)
Industrial
70
25
46C3
48T
(-40° to 85° C)
Package Type
46C3
48T
46-ball, Plastic Chip-Size Ball Grid Array Package (CBGA)
48-lead, Plastic Thin Small Outline Package (TSOP)
27
3367D–FLASH–5/04
Packaging Information
46C3 – CBGA
E
A1 BALL ID
D
TOP VIEW
A1
A
SIDE VIEW
E1
0.625 REF
e
A1 BALL CORNER
1.875 REF
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
6.50
NOTE
SYMBOL
A
B
C
D
E
F
E
6.40
6.60
E1
D
5.25 TYP
7.50
7.40
7.60
D1
D1
A
3.75 TYP
–
–
1.00
–
A1
e
0.22
–
0.75 BSC
0.35 TYP
b
8
7
6
5
4
3
2
1
b
BOTTOM VIEW
7/2/03
DRAWING NO. REV.
46C3
TITLE
2325 Orchard Parkway
San Jose, CA 95131
46C3, 46-ball (8 x 6 Array),0.75 mm Pitch, 6.5 x 7.5 x 1.0 mm
Chip-scale Ball Grid Array Package (CBGA)
A
R
28
AT49BV160C(T)
3367D–FLASH–5/04
AT49BV160C(T)
48T – TSOP
PIN 1
0º ~ 8º
c
Pin 1 Identifier
D1
D
L
b
L1
e
A2
E
GAGE PLANE
A
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
–
MAX
1.20
0.15
1.05
20.20
NOM
–
NOTE
SYMBOL
A
A1
A2
D
0.05
0.95
19.80
18.30
11.90
0.50
–
1.00
Notes:
1. This package conforms to JEDEC reference MO-142, Variation DD.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
20.00
18.40
12.00
0.60
D1
E
18.50 Note 2
12.10 Note 2
0.70
L
L1
b
0.25 BASIC
0.22
0.17
0.10
0.27
0.21
c
–
e
0.50 BASIC
10/18/01
DRAWING NO. REV.
48T
TITLE
2325 Orchard Parkway
San Jose, CA 95131
48T, 48-lead (12 x 20 mm Package) Plastic Thin Small Outline
Package, Type I (TSOP)
B
R
29
3367D–FLASH–5/04
Atmel Corporation
Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
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Fax: 1(408) 436-4314
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3367D–FLASH–5/04
/xM
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