AT49BV512-12VL [ATMEL]
Flash, 64KX8, 120ns, PDSO32, 8 X 14 MM, PLASTIC, VSOP-32;
| 型号： | AT49BV512-12VL |
| 厂家： | 
ATMEL |
| 描述： | Flash, 64KX8, 120ns, PDSO32, 8 X 14 MM, PLASTIC, VSOP-32 光电二极管 |
| 文件： | 总17页 (文件大小：173K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Single Supply Voltage Range, 2.7V to 3.6V
• Single Supply for Read and Write
• Fast Read Access Time – 70 ns
• Internal Program Control and Timer
• 8K Bytes Boot Block with Lockout
• Fast Erase Cycle Time – 10 Seconds
• Byte-by-Byte Programming – 30 µs/Byte Typical
• Hardware Data Protection
• DATA Polling for End of Program Detection
• Low Power Dissipation
– 25 mA Active Current
– 50 µA CMOS Standby Current
• Typical 10,000 Write Cycles
512K (64K x 8)
Single 2.7-volt
Battery-Voltage™
Flash Memory
Description
The AT49BV512 is a 3-volt only, 512K Flash memories organized as 65,536 words of
8 bits each. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the
devices offer access times to 70 ns with power dissipation of just 90 mW over the
commercial temperature range. When the devices are deselected, the CMOS standby
current is less than 50 µA.
AT49BV512
To allow for simple in-system reprogrammability, the AT49BV512 does not require
high input voltages for programming. Three-volt only commands determine the read
and programming operation of the device. Reading data out of the device is similar to
reading from an EPROM. Reprogramming the AT49BV512 is performed by erasing
DIP Top View
Pin Configurations
NC
NC
A15
A12
A7
1
2
3
4
5
6
7
8
9
32 VCC
31 WE
30 NC
29 A14
28 A13
27 A8
Pin Name
A0 - A15
CE
Function
Addresses
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
A6
A5
26 A9
OE
A4
25 A11
24 OE
23 A10
22 CE
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
A3
WE
A2 10
A1 11
I/O0 - I/O7
NC
A0 12
I/O0 13
I/O1 14
I/O2 15
GND 16
VSOP Top View (8 x 14 mm) or
TSOP Top View (8 x 20 mm)
Type 1
PLCC Top View
A11
A9
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
2
A10
CE
A8
3
A7
A6
A5
A4
A3
5
6
7
8
9
29 A14
A13
A14
NC
WE
VCC
NC
NC
A15
A12
A7
4
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 I/O7
5
6
7
8
A2 10
A1 11
A0 12
I/O0 13
9
10
11
12
13
14
15
16
A6
A1
A5
A2
Rev. 1026E–FLASH–06/02
A4
A3
the entire 1 megabit of memory and then programming on a byte-by-byte basis. The typ-
ical byte programming time is a fast 30 µs. The end of a program cycle can be optionally
detected by the DATA polling feature. Once the end of a byte program cycle has been
detected, a new access for a read or program can begin. The typical number of program
and erase cycles is in excess of 10,000 cycles.
The optional 8K bytes boot block section includes a reprogramming write lock out fea-
ture to provide data integrity. The boot sector is designed to contain user secure code,
and when the feature is enabled, the boot sector is permanently protected from being
reprogrammed.
Block Diagram
DATA INPUTS/OUTPUTS
I/O0 - I/O7
VCC
GND
OE
WE
CE
DATA LATCH
OE, CE AND WE
LOGIC
INPUT/OUTPUT
BUFFERS
Y DECODER
X DECODER
Y-GATING
ADDRESS
INPUTS
FFFFH
MAIN MEMORY
(56K BYTES)
2000H
1FFFH
OPTIONAL BOOT
BLOCK (8K BYTES)
0000H
Device Operation
READ: The AT49BV512 is accessed like an EPROM. When CE and OE are low and
WE is high, the data stored at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high impedance state whenever CE
or OE is high. This dual-line control gives designers flexibility in preventing bus
contention.
ERASURE: Before a byte can be reprogrammed, the 64K bytes memory array (or 56K
bytes if the boot block featured is used) must be erased. The erased state of the mem-
ory bits is a logical “1”. The entire device can be erased at one time by using a 6-byte
software code. The software chip erase code consists of 6-byte load commands to spe-
cific address locations with a specific data pattern (please refer to the Chip Erase Cycle
Waveforms).
After the software chip erase has been initiated, the device will internally time the erase
operation so that no external clocks are required. The maximum time needed to erase
the whole chip is tEC. If the boot block lockout feature has been enabled, the data in the
boot sector will not be erased.
BYTE PROGRAMMING: Once the memory array is erased, the device is programmed
(to a logical “0”) on a byte-by-byte basis. Please note that a data “0” cannot be pro-
grammed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is
accomplished via the internal device command register and is a 4 bus cycle operation
(please refer to the Command Definitions table). The device will automatically generate
the required internal program pulses.
The program cycle has addresses latched on the falling edge of WE or CE, whichever
occurs last, and the data latched on the rising edge of WE or CE, whichever occurs first.
Programming is completed after the specified tBP cycle time. The DATA polling feature
may also be used to indicate the end of a program cycle.
2
AT49BV512
1026E–FLASH–06/02
AT49BV512
BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block
that has a programming lockout feature. This feature prevents programming of data in
the designated block once the feature has been enabled. The size of the block is 8K
bytes. This block, referred to as the boot block, can contain secure code that is used to
bring up the system. Enabling the lockout feature will allow the boot code to stay in the
device while data in the rest of the device is updated. This feature does not have to be
activated; the boot block’s usage as a write protected region is optional to the user. The
address range of the boot block is 0000H to 1FFFH.
Once the feature is enabled, the data in the boot block can no longer be erased or pro-
grammed. Data in the main memory block can still be changed through the regular
programming method. To activate the lockout feature, a series of six program com-
mands to specific addresses with specific data must be performed. Please refer to the
Command Definitions table.
BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if
programming of the boot block section is locked out. When the device is in the software
product identification mode (see Software Product Identification Entry and Exit sections)
a read from address location 00002H will show if programming the boot block is locked
out. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is
high, the program lockout feature has been activated and the block cannot be pro-
grammed. The software product identification code should be used to return to standard
operation.
PRODUCT IDENTIFICATION: The product identification mode identifies the device and
manufacturer as Atmel. It may be accessed by hardware or software operation. The
hardware operation mode can be used by an external programmer to identify the correct
programming algorithm for the Atmel product.
For details, see Operating Modes (for hardware operation) or Software Product Identifi-
cation. The manufacturer and device code is the same for both modes.
DATA POLLING: The AT49BV512 features DATA polling to indicate the end of a pro-
gram cycle. During a program cycle an attempted read of the last byte loaded will result
in the complement of the loaded data on I/O7. Once the program cycle has been com-
pleted, true data is valid on all outputs and the next cycle may begin. DATA polling may
begin at any time during the program cycle.
TOGGLE BIT: In addition to DATA polling the AT49BV512 provides another method for
determining the end of a program or erase cycle. During a program or erase operation,
successive attempts to read data from the device will result in I/O6 toggling between
one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid
data will be read. Examining the toggle bit may begin at any time during a program
cycle.
HARDWARE DATA PROTECTION: Hardware features protect against inadvertent pro-
grams to the AT49BV512 in the following ways: (a) VCC sense: if VCC is below 1.8V
(typical), the program function is inhibited. (b) Program inhibit: holding any one of OE
low, CE high or WE high inhibits program cycles. (c) Noise filter: Pulses of less than
15 ns (typical) on the WE or CE inputs will not initiate a program cycle.
INPUT LEVELS: While operating with a 2.7V to 3.6V power supply, the address inputs
and control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely
affecting the operation of the device. The I/O lines can only be driven from 0 to VCC
0.6V.
+
3
1026E–FLASH–06/02
Command Definition (in Hex)
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Command
Sequence
Bus
Cycles
Addr
Addr
5555
5555
Data
DOUT
AA
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Read
1
6
4
Chip Erase
2AAA
2AAA
55
55
5555
5555
80
A0
5555
Addr
AA
DIN
2AAA
2AAA
55
5555
5555
10
Byte
Program
AA
Boot Block
Lockout(1)
6
3
3
1
5555
5555
5555
XXXX
AA
AA
AA
F0
2AAA
2AAA
2AAA
55
55
55
5555
5555
5555
80
90
F0
5555
AA
55
40
Product ID
Entry
Product ID
Exit(2)
Product ID
Exit(2)
Notes: 1. The 8K byte boot sector has the address range 0000H to 1FFFH.
2. Either one of the Product ID exit commands can be used.
Absolute Maximum Ratings*
Temperature Under Bias ............................... -55°C to +125°C
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V
4
AT49BV512
1026E–FLASH–06/02
AT49BV512
DC and AC Operating Range
AT49BV512-70
0°C - 70°C
AT49BV512-90
0°C - 70°C
AT49BV512-12
0°C - 70°C
AT49BV512-15
0°C - 70°C
Operating
Temperature (Case)
Com.
Ind.
-40°C - 85°C
2.7V to 3.6V
-40°C - 85°C
2.7V to 3.6V
-40°C - 85°C
2.7V to 3.6V
-40°C - 85°C
2.7V to 3.6V
V
CC Power Supply
Operating Modes
Mode
CE
VIL
VIL
VIH
X
OE
WE
VIH
VIL
X
Ai
Ai
Ai
X
I/O
Read
VIL
VIH
X(1)
X
DOUT
DIN
Program(2)
Standby/Write Inhibit
Program Inhibit
Program Inhibit
Output Disable
Product Identification
Hardware
High Z
VIH
X
X
VIL
VIH
X
X
High Z
VIL
VIL
VIH
A1 - A15 = VIL, A9 = VH,(3), A0 = VIL
A1 - A15 = VIL, A9 = VH,(3), A0 = VIH
A0 = VIL, A1 - A15 = VIL
Manufacturer Code(4)
Device Code(4)
Software(5)
Manufacturer Code(4)
Device Code(4)
A0 = VIH, A1 - A15 = VIL
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V 0.5V.
4. Manufacturer Code: 1FH, Device Code: 03H.
5. See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol
Parameter
Condition
Min
Max
10
10
50
1
Units
µA
µA
µA
mA
mA
V
ILI
Input Load Current
Output Leakage Current
VCC Standby Current CMOS
VCC Standby Current TTL
VCC Active Current
Input Low Voltage
VIN = 0V to VCC
ILO
VI/O = 0V to VCC
ISB1
CE = VCC - 0.3V to VCC
CE = 2.0V to VCC
f = 5 MHz; IOUT = 0 mA
ISB2
(1)
ICC
25
0.6
VIL
VIH
VOL
VOH
Input High Voltage
Output Low Voltage
Output High Voltage
2.0
2.4
V
IOL = 2.1 mA
0.45
V
IOH = -100 µA; VCC = 3.0V
V
Note:
1. In the erase mode, ICC is 50 mA.
5
1026E–FLASH–06/02
AC Read Characteristics
AT49BV512-70 AT49BV512-90 AT49BV512-12 AT49BV512-15
Symbol Parameter
Min
Max
70
Min
Max
90
Min
Max
120
120
50
Min
Max
150
150
70
Units
ns
tACC
Address to Output Delay
CE to Output Delay
(1)
tCE
tOE
tDF
tOH
70
90
ns
(2)
OE to Output Delay
0
0
0
35
40
0
0
0
ns
(3, 4)
CE or OE to Output Float
25
0
0
25
0
0
30
40
ns
Output Hold from OE, CE or
ns
Address, whichever occurred first
AC Read Waveforms(1)(2)(3)(4)
ADDRESS
ADDRESS VALID
CE
OE
tCE
tDF
tACC
tOH
OUTPUT VALID
HIGH Z
OUTPUT
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC
.
.
3. tDF is specified from OE or CE whichever occurs first (CL - 5 pF).
4. This parameter is characterized and is not 100% tested.
6
AT49BV512
1026E–FLASH–06/02
AT49BV512
Input Test Waveforms and
Measurement Level
2.4V
0.4V
AC
AC
DRIVING
LEVELS
1.5V
MEASUREMENT
LEVEL
tR, tF < 5 ns
Output Test Load
3.0V
1.8K
OUTPUT
PIN
100 pF
1.3K
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
Typ
Max
6
Units
pF
Conditions
VIN = 0V
4
8
COUT
12
pF
VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
7
1026E–FLASH–06/02
AC Byte Load Characteristics
Symbol
Parameter
Min
0
Max
Units
ns
tAS, tOES
Address, OE Set-up Time
Address Hold Time
tAH
tCS
tCH
tWP
tDS
100
0
ns
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
ns
0
ns
200
100
0
ns
ns
tDH, tOEH
Data, OE Hold Time
Write Pulse Width High
ns
tWPH
200
ns
AC Byte Load Waveforms
WE Controlled
OE
tOES
tOEH
tCH
ADDRESS
CE
tAS
tCS
tAH
WE
tWP
tDS
tWPH
tDH
DATA IN
CE Controlled
OE
tOES
tOEH
tCH
ADDRESS
WE
tAS
tCS
tAH
CE
tWP
tDS
tWPH
tDH
DATA IN
8
AT49BV512
1026E–FLASH–06/02
AT49BV512
Program Cycle Characteristics
Symbol
Parameter
Min
Typ
Max
Units
µs
tBP
Byte Programming Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
30
tAS
0
ns
tAH
100
100
0
ns
tDS
ns
tDH
ns
tWP
Write Pulse Width
Write Pulse Width High
Erase Cycle Time
200
200
ns
tWPH
tEC
ns
10
seconds
Program Cycle Waveforms
PROGRAM CYCLE
OE
CE
tWP
tAH
tWPH
tDH
tBP
WE
tAS
A0-A15
5555
2AAA
5555
ADDRESS
tDS
INPUT
DATA
DATA
AA
55
A0
Chip Erase Cycle Waveforms
OE
CE
tWP
tAH
tWPH
WE
A0-A15
DATA
tAS
tDH
5555
2AAA
5555
5555
2AAA
5555
tDS
tEC
AA
BYTE 0
55
BYTE 1
80
BYTE 2
AA
55
BYTE 4
10
BYTE 5
BYTE 3
Note:
OE must be high only when WE and CE are both low.
9
1026E–FLASH–06/02
Data Polling Characteristics(1)
Symbol
Parameter
Min
0
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
OE Hold Time
10
ns
OE to Output Delay(2)
Write Recovery Time
ns
tWR
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
WE
CE
tOEH
OE
tDH
tOE
An
tWR
I/O7
A0-A15
An
An
An
An
Toggle Bit Characteristics(1)
Symbol
Parameter
Min
0
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
tOEHP
tWR
OE Hold Time
10
ns
OE to Output Delay(2)
OE High Pulse
ns
150
0
ns
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms(1)(2)(3)
WE
CE
tOEH
tDH
tOEHP
OE
tOE
tWR
HIGH Z
I/O6
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling
input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
10
AT49BV512
1026E–FLASH–06/02
AT49BV512
Boot Block Lockout Feature
Enable Algorithm(1)
Software Product
Identification Entry(1)
LOAD DATA AA
LOAD DATA AA
TO
TO
ADDRESS 5555
ADDRESS 5555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS 2AAA
ADDRESS 2AAA
LOAD DATA 90
TO
LOAD DATA 80
TO
ADDRESS 5555
ADDRESS 5555
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(5)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
Software Product
Identification Exit(1)
ADDRESS 2AAA
LOAD DATA AA
LOAD DATA F0
TO
TO
OR
LOAD DATA 40
TO
ADDRESS 5555
ANY ADDRESS
ADDRESS 5555
LOAD DATA 55
TO
EXIT PRODUCT
IDENTIFICATION
MODE(4)
ADDRESS 2AAA
PAUSE 1 second(2)
LOAD DATA F0
TO
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
ADDRESS 5555
2. Boot block lockout feature enabled.
EXIT PRODUCT
IDENTIFICATION
MODE(4)
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A15 = VIL.
Manufacture Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does note remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturers Code: 1FH
Device Code: 03H.
11
1026E–FLASH–06/02
Ordering Information(1)
ICC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
70
25
0.05
AT49BV512-70JC
AT49BV512-70PC
AT49BV512-70TC
AT49BV512-70VC
32J
Commercial
32P6
32T
32V
(0°C - 70°C)
25
25
25
25
25
25
25
0.05
0.05
0.05
0.05
0.05
0.05
0.05
AT49BV512-70JI
AT49BV512-70PI
AT49BV512-70TI
AT49BV512-70VI
32J
Industrial
32P6
32T
32V
(-40°C - 85°C)
90
AT49BV512-90JC
AT49BV512-90PC
AT49BV512-90TC
AT49BV512-90VC
32J
Commercial
32P6
32T
32V
(0°C - 70°C)
AT49BV512-90JI
AT49BV512-90PI
AT49BV512-90TI
AT49BV512-90VI
32J
Industrial
32P6
32T
32V
(-40°C - 85°C)
120
AT49BV512-12JC
AT49BV512-12PC
AT49BV512-12TC
AT49BV512-12VC
32J
Commercial
32P6
32T
32V
(0°C - 70°C)
AT49BV512-12JI
AT49BV512-12PI
AT49BV512-12TI
AT49BV512-12VI
32J
Industrial
32P6
32T
32V
(-40°C - 85°C)
150
AT49BV512-15JC
AT49BV512-15PC
AT49BV512-15TC
AT49BV512-15VC
32J
Commercial
32P6
32T
32V
(0°C - 70°C)
AT49BV512-15JI
AT49BV512-15PI
AT49BV512-15TI
AT49BV512-15VI
32J
Industrial
32P6
32T
32V
(-40°C - 85°C)
Note:
1. The AT49BV512 has as optional boot block feature. The part number shown in the Ordering Information table is for devices
with the boot block in the lower address range (i.e., 0000H to 1FFFH). Users requiring boot block protection to be in the
higher address range should contact Atmel.
Package Type
32-lead, Plastic J-leaded Chip Carrier Package (PLCC)
32-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
32-lead, Thin Small Outline Package (TSOP) (8 x 20 mm)
32-lead, Thin Small Outline Package (VSOP) (8 x 14 mm)
32J
32P6
32T
32V
12
AT49BV512
1026E–FLASH–06/02
AT49BV512
Packaging Information
32J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
IDENTIFIER
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
E2
E1
E
B1
B
e
A2
A1
D1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
3.175
1.524
0.381
12.319
11.354
9.906
14.859
13.894
12.471
0.660
0.330
MAX
3.556
2.413
–
NOM
NOTE
SYMBOL
A
–
D2
A1
A2
D
–
–
–
12.573
D1
D2
E
–
11.506 Note 2
10.922
–
Notes:
1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
–
15.113
E1
E2
B
–
14.046 Note 2
13.487
–
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
32J
B
R
13
1026E–FLASH–06/02
32P6 – PDIP
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
COMMON DIMENSIONS
(Unit of Measure = mm)
0º ~ 15º REF
C
MIN
–
MAX
4.826
–
NOM
NOTE
SYMBOL
A
–
eB
A1
D
0.381
41.783
15.240
13.462
0.356
1.041
3.048
0.203
15.494
–
–
42.291 Note 1
15.875
E
–
E1
B
–
13.970 Note 1
0.559
–
B1
L
–
1.651
Note:
1. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
–
3.556
C
–
–
0.381
eB
e
17.526
2.540 TYP
09/28/01
DRAWING NO. REV.
32P6
TITLE
2325 Orchard Parkway
San Jose, CA 95131
32P6, 32-lead (0.600"/15.24 mm Wide) Plastic Dual
Inline Package (PDIP)
B
R
14
AT49BV512
1026E–FLASH–06/02
AT49BV512
32T – TSOP
PIN 1
0º ~ 8º
c
Pin 1 Identifier
D1
D
L
b
L1
e
A2
E
GAGE PLANE
A
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
–
MAX
1.20
0.15
1.05
20.20
NOM
–
NOTE
SYMBOL
A
A1
A2
D
0.05
0.95
19.80
18.30
7.90
0.50
–
1.00
Notes:
1. This package conforms to JEDEC reference MO-142, Variation BD.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
20.00
18.40
8.00
D1
E
18.50 Note 2
8.10
0.70
Note 2
L
0.60
L1
b
0.25 BASIC
0.22
0.17
0.10
0.27
0.21
c
–
e
0.50 BASIC
10/18/01
DRAWING NO. REV.
32T
TITLE
2325 Orchard Parkway
San Jose, CA 95131
32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline
Package, Type I (TSOP)
B
R
15
1026E–FLASH–06/02
32V – VSOP
PIN 1
0º ~ 8º
c
Pin 1 Identifier
D1
D
L
b
L1
e
A2
E
GAGE PLANE
A
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
–
MAX
1.20
0.15
1.05
14.20
NOM
–
NOTE
SYMBOL
A
A1
A2
D
0.05
0.95
13.80
12.30
7.90
0.50
–
1.00
Notes:
1. This package conforms to JEDEC reference MO-142, Variation BA.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
14.00
12.40
8.00
D1
E
12.50 Note 2
8.10
0.70
Note 2
L
0.60
L1
b
0.25 BASIC
0.22
0.17
0.10
0.27
0.21
c
–
e
0.50 BASIC
10/18/01
DRAWING NO. REV.
32V
TITLE
2325 Orchard Parkway
San Jose, CA 95131
32V, 32-lead (8 x 14 mm Package) Plastic Thin Small Outline
Package, Type I (VSOP)
B
R
16
AT49BV512
1026E–FLASH–06/02
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Corporate Headquarters
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http://www.atmel.com
© Atmel Corporation 2002.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
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Printed on recycled paper.
1026E–FLASH–06/02
xM
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