AT49F020-15PL [ATMEL]

Flash, 256KX8, 150ns, PDIP32, 0.600 INCH, PLASTIC, DIP-32;


型号：	AT49F020-15PL
厂家：	ATMEL
描述：	Flash, 256KX8, 150ns, PDIP32, 0.600 INCH, PLASTIC, DIP-32 ATM 异步传输模式光电二极管内存集成电路
文件：	总12页 (文件大小：337K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Features

• Single Voltage Operation

– 5V Read

– 5V Reprogramming

• Fast Read Access Time - 90 ns

• Internal Program Control and Timer

• 8K Bytes Boot Block With Lockout

• Fast Erase Cycle Time - 10 seconds

• Byte-By-Byte Programming - 50 µs/Byte

• Hardware Data Protection

• DATA Polling For End Of Program Detection

• Low Power Dissipation

– 50 mA Active Current

– 100 µA CMOS Standby Current

• Typical 10,000 Write Cycles

2-Megabit

(256K x 8)

5-volt Only

Flash Memory

Description

The AT49F020 is a 5-volt only in-system Flash Memory. Its 2 megabits of memory is

organized as 262,144 words by 8 bits. Manufactured with Atmel’s advanced nonvola-

tile CMOS technology, the device offers access times to 90 ns with power dissipation

of just 275 mW over the commercial temperature range. When the device is dese-

lected, the CMOS standby current is less than 100 µA.

AT49F020

To allow for simple in-system reprogrammability, the AT49F020 does not require high

input voltages for programming. Five-volt-only commands determine the read and

programming operation of the device. Reading data out of the device is similar to

reading from an EPROM. Reprogramming the AT49F020 is performed by erasing the

entire 2 megabits of memory and then programming on a byte by byte basis. The byte

(continued)

Not Recommended

for New Design

Contact Atmel to discuss

the latest design in trends

and options

Pin Configurations

PLCC Top View

Pin Name

A0 - A17

Function

Addresses

29 A14

28 A13

27 A8

26 A9

25 A11

24 OE

23 A10

22 CE

21 I/O7

Chip Enable

Output Enable

Write Enable

Data Inputs/Outputs

No Connect

A2 10

A1 11

A0 12

I/O0 13

I/O0 - I/O7

TSOP Top View

DIP Top View

Type 1

A16

A15

A12

32 VCC

31 WE

30 A17

29 A14

28 A13

27 A8

A11

A10

A13

A14

A17

VCC

A16

A15

A12

I/O7

I/O6

I/O5

I/O4

I/O3

GND

I/O2

I/O1

I/O0

26 A9

25 A11

24 OE

23 A10

22 CE

21 I/O7

20 I/O6

19 I/O5

18 I/O4

17 I/O3

A2 10

A1 11

A0 12

I/O0 13

I/O1 14

I/O2 15

GND 16

Rev. 0567C–10/98

programming time is a fast 50 µs. The end of a program

cycle can be optionally detected by the DATA polling fea-

ture. Once the end of a byte program cycle has been

detected, a new access for a read or program can begin.

The typical number of program and erase cycles is in

excess of 10,000 cycles.

The optional 8K bytes boot block section includes a repro-

gramming write lock out feature to provide data integrity.

The boot sector is designed to contain user secure code,

and when the feature is enabled, the boot sector is perma-

nently protected from being reprogrammed.

Block Diagram

DATA INPUTS/OUTPUTS

I/O0 - I/O7

VCC

GND

DATA LATCH

OE, CE AND WE

LOGIC

INPUT/OUTPUT

BUFFERS

Y DECODER

ADDRESS

Y-GATING

3FFFF

MAIN MEMORY

INPUTS

X DECODER

(248K BYTES)

02000

01FFF

OPTIONAL BOOT

BLOCK (8K BYTES)

00000

Device Operation

READ: The AT49F020 is accessed like an EPROM. When

CE and OE are low and WE is high, the data stored at the

memory location determined by the address pins is

asserted on the outputs. The outputs are put in the high

impedance state whenever CE or OE is high. This dual-line

control gives designers flexibility in preventing bus conten-

tion.

latched on the rising edge of WE or CE, whichever occurs

first. Programming is completed after the specified t_BPcycle

time. The DATA polling feature may also be used to indi-

cate the end of a program cycle.

BOOT BLOCK PROGRAMMING LOCKOUT: The device

has one designated block that has a programming lockout

feature. This feature prevents programming of data in the

designated block once the feature has been enabled. The

size of the block is 8K bytes. This block, referred to as the

boot block, can contain secure code that is used to bring up

the system. Enabling the lockout feature will allow the boot

code to stay in the device while data in the rest of the

device is updated. This feature does not have to be acti-

vated; the boot block’s usage as a write protected region is

optional to the user. The address range of the boot block is

00000H to 01FFFH.

ERASURE: Before a byte can be reprogrammed, the 256K

bytes memory array (or 248K bytes if the boot block fea-

tured is used) must be erased. The erased state of the

memory bits is a logical “1”. The entire device can be

erased at one time by using a 6-byte software code. The

software chip erase code consists of 6-byte load com-

mands to specific address locations with a specific data

pattern (please refer to the Chip Erase Cycle Waveforms).

After the software chip erase has been initiated, the device

will internally time the erase operation so that no external

clocks are required. The maximum time needed to erase

the whole chip is t_EC. If the boot block lockout feature has

been enabled, the data in the boot sector will not be

erased.

Once the feature is enabled, the data in the boot block can

no longer be erased or programmed. Data in the main

memory block can still be changed through the regular pro-

gramming method. To activate the lockout feature, a series

of six program commands to specific addresses with spe-

cific data must be performed. Please refer to the Command

Definitions table.

BYTE PROGRAMMING: Once the memory array is

erased, the device is programmed (to a logical “0”) on a

byte-by-byte basis. Please note that a data “0” cannot be

programmed back to a “1”; only erase operations can con-

vert “0”s to “1”s. Programming is accomplished via the

internal device command register and is a 4 bus cycle

operation (please refer to the Command Definitions table).

The device will automatically generate the required internal

program pulses.

BOOT BLOCK LOCKOUT DETECTION: A software

method is available to determine if programming of the boot

block section is locked out. When the device is in the soft-

ware product identification mode (see Software Product

Identification Entry and Exit sections) a read from address

location 00002H will show if programming the boot block is

locked out. If the data on I/O0 is low, the boot block can be

programmed; if the data on I/O0 is high, the program lock-

out feature has been activated and the block cannot be

The program cycle has addresses latched on the falling

edge of WE or CE, whichever occurs last, and the data

AT49F020

programmed. The software product identification code

should be used to return to standard operation.

TOGGLE BIT: In addition to DATA polling the AT49F020

provides another method for determining the end of a pro-

gram or erase cycle. During a program or erase operation,

successive attempts to read data from the device will result

in I/O6 toggling between one and zero. Once the program

cycle has completed, I/O6 will stop toggling and valid data

will be read. Examining the toggle bit may begin at any time

during a program cycle.

PRODUCT IDENTIFICATION: The product identification

mode identifies the device and manufacturer as Atmel. It

may be accessed by hardware or software operation. The

hardware operation mode can be used by an external pro-

grammer to identify the correct programming algorithm for

the Atmel product.

HARDWARE DATA PROTECTION: Hardware features

protect against inadvertent programs to the AT49F020 in

the following ways: (a) V_CCsense—if V_CCis below 3.8V

(typical), the program function is inhibited; (b) Program

inhibit—holding any one of OE low, CE high or WE high

inhibits program cycles; and (c) Noise filter—pulses of less

than 15 ns (typical) on the WE or CE inputs will not initiate

a program cycle.

For details, see Operating Modes (for hardware operation)

or Software Product Identification. The manufacturer and

device code is the same for both modes.

DATA POLLING: The AT49F020 features DATA polling to

indicate the end of a program cycle. During a program

cycle an attempted read of the last byte loaded will result in

the complement of the loaded data on I/O7. Once the pro-

gram cycle has been completed, true data is valid on all

outputs and the next cycle may begin. DATA polling may

begin at any time during the program cycle.

Command Definition (in Hex)

Command

Sequence

Bus

Cycles

1st Bus

Cycle

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

6th Bus

Cycle

Addr

Data

D_OUT

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Read

Addr

5555

Chip Erase

2AAA

5555

Addr

D_IN

2AAA

5555

Byte

Program

Boot Block

Lockout⁽¹⁾

5555

XXXX

2AAA

5555

Product ID

Entry

Product ID

Exit⁽²⁾

Product ID

Exit⁽²⁾

Notes: 1. The 8K byte boot sector has the address range 00000H to 01FFFH.

2. Either one of the Product ID exit commands can be used.

Absolute Maximum Ratings*

*NOTICE:

Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device reliability.

Temperature Under Bias................................ -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

All Input Voltages (including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground.............................-0.6V to V_CC+ 0.6V

Voltage on OE

with Respect to Ground...................................-0.6V to +13.5V

DC and AC Operating Range

AT49F020-90

0°C - 70°C

AT49F020-12

0°C - 70°C

AT49F020-15

0°C - 70°C

Com.

Operating

Temperature (Case)

Ind.

-40°C - 85°C

5V ± 10%

-40°C - 85°C

5V ± 10%

-40°C - 85°C

5V ± 10%

V_CCPower Supply

Operating Modes

Mode

V_IL

V_IH

V_IL

V_IH

X⁽¹⁾

V_IH

V_IL

I/O

Read

D_OUT

D_IN

Program⁽²⁾

Standby/Write Inhibit

Program Inhibit

Output Disable

Product Identification

High Z

V_IH

V_IL

V_IH

High Z

A1 - A17 = V_IL, A9 = V_H,⁽³⁾A0 = V_IL

A1 - A17 = V_IL, A9 = V_H,⁽³⁾A0 = V_IH

A0 = V_IL, A1 - A17=V_IL

Manufacturer Code⁽⁴⁾

Device Code⁽⁴⁾

Hardware

V_IL

V_IH

Manufacturer Code⁽⁴⁾

Device Code⁽⁴⁾

Software⁽⁵⁾

A0 = V_IH, A1 - A17=V_IL

Notes: 1. X can be V_ILor V_IH.

2. Refer to AC Programming Waveforms.

3. V_H= 12.0V ± 0.5V.

4. Manufacturer Code: 1FH, Device Code: 0BH.

5. See details under Software Product Identification Entry/Exit.

DC Characteristics

Symbol

Parameter

Condition

Min

Max

Units

µA

I_LI

Input Load Current

Output Leakage Current

V_IN= 0V to V_CC

V_I/O= 0V to V_CC

I_LO

Com.

Ind.

100

300

I_SB1

V_CCStandby Current CMOS

CE = V_CC- 0.3V to V_CC

I_SB2

V_CCStandby Current TTL

V_CCActive Current

CE = 2.0V to V_CC

(1)

I_CC

f = 5 MHz; I_OUT= 0 mA

V_IL

Input Low Voltage

0.8

V_IH

Input High Voltage

2.0

V_OL

V_OH1

V_OH2

Output Low Voltage

Output High Voltage

Output High Voltage CMOS

I_OL= 2.1 mA

0.45

I_OH= -400 µA

2.4

4.2

I_OH= -100 µA; V_CC= 4.5V

Note:

1. In the erase mode, I_CCis 90 mA.

AT49F020

AC Read Characteristics

AT49F020-90

Min Max

AT49F020-12

AT49F020-15

Symbol

Parameter

Min

Max

Min

Max

Units

t_ACC

Address to Output Delay

CE to Output Delay

OE to Output Delay

CE or OE to Output Float

120

150

(1)

t_CE

(2)

t_OE

(3)(4)

t_DF

Output Hold from OE, CE or

Address, whichever occurred first

t_OH

AC Read Waveforms^(1)(2)(3)(4)

Notes: 1. CE may be delayed up to t_ACC- t_CEafter the address transition without impact on t_ACC

2. OE may be delayed up to t_CE- t_OEafter the falling edge of CE without impact on t_CEor by t_ACC- t_OEafter an address change

without impact on t_ACC

3. t_DFis specified from OE or CE whichever occurs first (CL = 5 pF).

4. This parameter is characterized and is not 100% tested.

Input Test Waveforms and

Measurement Level

Output Test Load

t_R, t_F< 5 ns

Pin Capacitance

f = 1 MHz, T = 25°C⁽¹⁾

Symbol

C_IN

Typ

Max

Units

Conditions

V_IN= 0V

C_OUT

V_OUT= 0V

Note:

1. This parameter is characterized and is not 100% tested.

AC Byte Load Characteristics

Symbol

Parameter

Min

Max

Units

_AS, t_OES

Address, OE Set-up Time

Address Hold Time

t_AH

t_CS

t_CH

t_WP

t_DS

Chip Select Set-up Time

Chip Select Hold Time

Write Pulse Width (WE or CE)

Data Set-up Time

_DH, t_OEH

Data, OE Hold Time

Write Pulse Width High

t_WPH

AC Byte Load Waveforms

WE Controlled

CE Controlled

AT49F020

Program Cycle Characteristics

Symbol

Parameter

Min

Typ

Max

Units

µs

t_BP

Byte Programming Time

Address Set-up Time

Address Hold Time

Data Set-up Time

Data Hold Time

t_AS

t_AH

t_DS

t_DH

t_WP

Write Pulse Width

Write Pulse Width High

Erase Cycle Time

t_WPH

t_EC

seconds

Program Cycle Waveforms

Chip Erase Cycle Waveforms

Note:

1. OE must be high only when WE and CE are both low.

Data Polling Characteristics⁽¹⁾

Symbol

Parameter

Min

Typ

Max

Units

t_DH

Data Hold Time

t_OEH

t_OE

OE Hold Time

OE to Output Delay⁽²⁾

Write Recovery Time

t_WR

Notes: 1. These parameters are characterized and not 100% tested.

2. See t_OEspec in AC Read Characteristics.

Data Polling Waveforms

Toggle Bit Characteristics⁽¹⁾

Symbol

Parameter

Min

Typ

Max

Units

t_DH

Data Hold Time

OE Hold Time

t_OEH

t_OE

t_OEHP

t_WR

OE to Output Delay⁽²⁾

OE High Pulse

150

Write Recovery Time

Notes: 1. These parameters are characterized and not 100% tested.

2. See t_OEspec in AC Read Characteristics.

Toggle Bit Waveforms^(1)(2)(3)

Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The t_OEHPspecification must be met by the toggling

input(s).

2. Beginning and ending state of I/O6 will vary.

3. Any address location may be used but the address should not vary.

AT49F020

Software Product Identification Entry⁽¹⁾Boot Block Lockout

Feature Enable Algorithm⁽¹⁾

LOAD DATA AA

ADDRESS 5555

LOAD DATA 55

ADDRESS 2AAA

LOAD DATA 90

LOAD DATA 80

ADDRESS 5555

ENTER PRODUCT

IDENTIFICATION

MODE^(2)(3)(5)

LOAD DATA AA

ADDRESS 5555

Software Product Identification Exit⁽¹⁾

LOAD DATA 55

LOAD DATA AA

LOAD DATA F0

ADDRESS 2AAA

ADDRESS 5555

ANY ADDRESS

LOAD DATA 40

LOAD DATA 55

EXIT PRODUCT

IDENTIFICATION

MODE⁽⁴⁾

ADDRESS 5555

ADDRESS 2AAA

PAUSE 1 second⁽²⁾

LOAD DATA F0

ADDRESS 5555

Notes for boot block lockout feature enable:

1. Data Format: I/O7 - I/O0 (Hex);

Address Format: A14 - A0 (Hex).

EXIT PRODUCT

IDENTIFICATION

MODE⁽⁴⁾

2. Boot block lockout feature enabled.

Notes for software product identification:

1. Data Format: I/O7 - I/O0 (Hex);

Address Format: A14 - A0 (Hex).

2. A1 - A17 = V_IL.

Manufacturer Code is read for A0 = V_IL;

Device Code is read for A0 = V_IH.

3. The device does not remain in identification mode if

powered down.

4. The device returns to standard operation mode.

5. Manufacturer Code is 1FH. The Device Code is

0BH.

Ordering Information⁽¹⁾

I_CC(mA)

t_ACC

(ns)

Active

Standby

Ordering Code

Package

Operation Range

0.1

AT49F020-90JC

AT49F020-90PC

AT49F020-90TC

32J

Commercial

32P6

32T

(0° to 70°C)

0.3

0.1

0.3

0.1

0.3

AT49F020-90JI

AT49F020-90PI

AT49F020-90TI

32J

Industrial

32P6

32T

(-40° to 85°C)

120

150

AT49F020-12JC

AT49F020-12PC

AT49F020-12TC

32J

Commercial

32P6

32T

(0° to 70°C)

AT49F020-12JI

AT49F020-12PI

AT49F020-12TI

32J

Industrial

32P6

32T

(-40° to 85°C)

AT49F020-15JC

AT49F020-15PC

AT49F020-15TC

32J

Commercial

32P6

32T

(0° to 70°C)

AT49F020-15JI

AT49F020-15PI

AT49F020-15TI

32J

Industrial

32P6

32T

(-40° to 85°C)

Note:

1. The AT49F020 has an optional boot block feature. The part number shown in the Ordering Information table is for devices

with the boot block in the lower address range (i.e., 00000H to 01FFFH). Users requiring the boot block to be in the higher

address range should contact Atmel.

Package Type

32-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC)

32-Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)

32-Lead, Thin Small Outline Package (TSOP)

32J

32P6

32T

AT49F020

Packaging Information

32J, 32-Lead, Plastic J-Leaded Chip Carrier (PLCC)

Dimensions in Inches and (Millimeters)

JEDEC OUTLINE MS-016 AE

32P6, 32-Lead, 0.600" Wide, Plastic Dual Inline

Package (PDIP)

Dimensions in Inches and (Millimeters)

1.67(42.4)

1.64(41.7)

.025(.635) X 30˚ - 45˚

.045(1.14) X 45˚ PIN NO. 1

.012(.305)

IDENTIFY

.008(.203)

.566(14.4)

.530(13.5)

.553(14.0)

.490(12.4)

.547(13.9)

.032(.813)

.026(.660)

.021(.533)

.013(.330)

.595(15.1)

.585(14.9)

.090(2.29)

MAX

1.500(38.10) REF

.030(.762)

.015(.381)

.095(2.41)

.060(1.52)

.140(3.56)

.120(3.05)

.050(1.27) TYP

.220(5.59)

MAX

.005(.127)

MIN

.300(7.62) REF

.430(10.9)

.390(9.90)

SEATING

PLANE

AT CONTACT

POINTS

.065(1.65)

.015(.381)

.022(.559)

.014(.356)

.161(4.09)

.125(3.18)

.065(1.65)

.041(1.04)

.110(2.79)

.090(2.29)

.022(.559) X 45˚ MAX (3X)

.630(16.0)

.590(15.0)

.453(11.5)

.447(11.4)

REF

.495(12.6)

.485(12.3)

.012(.305)

.008(.203)

.690(17.5)

.610(15.5)

32T, 32-Lead, Plastic Thin Small Outline Package

(TSOP)

Dimensions in Millimeters and (Inches)*

JEDEC OUTLINE MO-142 BD

INDEX

MARK

18.5(.728)

18.3(.720)

20.2(.795)

19.8(.780)

0.50(.020)

BSC

0.25(.010)

0.15(.006)

7.50(.295)

REF

8.20(.323)

7.80(.307)

1.20(.047) MAX

0.15(.006)

0.05(.002)

0.20(.008)

0.10(.004)

REF

0.70(.028)

0.50(.020)

*Controlling dimension: millimeters

Atmel Headquarters

Atmel Operations

Corporate Headquarters

2325 Orchard Parkway

San Jose, CA 95131

TEL (408) 441-0311

FAX (408) 487-2600

Atmel Colorado Springs

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Colorado Springs, CO 80906

TEL (719) 576-3300

FAX (719) 540-1759

Europe

Atmel U.K., Ltd.

Atmel Rousset

Zone Industrielle

Coliseum Business Centre

Riverside Way

Camberley, Surrey GU15 3YL

England

13106 Rousset Cedex, France

TEL (33) 4 42 53 60 00

FAX (33) 4 42 53 60 01

TEL (44) 1276-686677

FAX (44) 1276-686697

Asia

Atmel Asia, Ltd.

Room 1219

Chinachem Golden Plaza

77 Mody Road

Tsimshatsui East

Kowloon, Hong Kong

TEL (852) 27219778

FAX (852) 27221369

Japan

Atmel Japan K.K.

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1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

TEL (81) 3-3523-3551

FAX (81) 3-3523-7581

Fax-on-Demand

North America:

1-(800) 292-8635

International:

1-(408) 441-0732

e-mail

literature@atmel.com

Web Site

http://www.atmel.com

BBS

1-(408) 436-4309

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-

ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s website. The Company assumes no responsibility for

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™

Marks bearing and/or are registered trademarks and trademarks of Atmel Corporation.

Terms and product names in this document may be trademarks of others.

Printed on recycled paper.

0567C–10/98/xM

AT49F020-15PL [ATMEL]

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