AT49F040-90PI [ATMEL]

4-Megabit 512K x 8 5-volt Only CMOS Flash Memory; 4兆位512K ×8 5伏只有CMOS闪存


型号：	AT49F040-90PI
厂家：	ATMEL
描述：	4-Megabit 512K x 8 5-volt Only CMOS Flash Memory 4兆位512K ×8 5伏只有CMOS闪存闪存
文件：	总12页 (文件大小：232K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Features

• Single Voltage Operation

– 5V Read

– 5V Reprogramming

• Fast Read Access Time - 70 ns

• Internal Program Control and Timer

• 16K bytes Boot Block With Lockout

• Fast Erase Cycle Time - 10 seconds

• Byte By Byte Programming - 50 µs/Byte

• Hardware Data Protection

• DATA Polling For End Of Program Detection

• Low Power Dissipation

– 50 mA Active Current

– 100 µA CMOS Standby Current

• Typical 10,000 Write Cycles

4-Megabit

(512K x 8)

5-volt Only

CMOS

Description

The AT49F040 is a 5-volt-only in-system Flash Memory. Its 4 megabits of memory is

organized as 524,288 words by 8 bits. Manufactured with Atmel’s advanced nonvola-

tile CMOS technology, the device offers access times to 70 ns with power dissipation

of just 275 mW over the commercial temperature range. When the device is dese-

lected, the CMOS standby current is less than 100 µA.

Flash Memory

AT49F040

AT49F040T

AT49F040/040T

The device contains a user-enabled “boot block” protection feature. Two versions of

the feature are available: the AT49F040 locates the boot block at lowest order

addresses (“bottom boot”); the AT49F040T locates it at highest order addresses (“top

boot”).

(continued)

DIP Top View

Pin Configurations

Pin Name Function

A0 - A18

Addresses

Chip Enable

Output Enable

Write Enable

AT49F040/040T

I/O0 - I/O7 Data Inputs/Outputs

PLCC Top View

TSOP Top View

Type 1

Rev. 0998A-A–01/98

To allow for simple in-system reprogrammability, the

AT49F040 does not require high input voltages for pro-

gramming. Five-volt-only commands determine the read

and programming operation of the device. Reading data

out of the device is similar to reading from an EPROM.

Reprogramming the AT49F040 is performed by erasing

the entire 4 megabits of memory and then programming on

a byte by byte basis. The byte programming time is a fast

50 µs. The end of a program cycle can be optionally

detected by the DATA polling feature. Once the end of a

byte program cycle has been detected, a new access for a

read or program can begin. The typical number of program

and erase cycles is in excess of 10,000 cycles.

The optional 16K bytes boot block section includes a repro-

gramming write lock out feature to provide data integrity.

The boot sector is designed to contain user secure code,

and when the feature is enabled, the boot sector is perma-

nently protected from being reprogrammed.

Block Diagram

AT49F040

AT49F040T

DATA INPUTS/OUTPUTS

I/O7 - I/O0

DATA INPUTS/OUTPUTS

I/O7 - I/O0

V_CC

GND

DATA LATCH

OE, CE, AND WE

LOGIC

INPUT/OUTPUT

BUFFERS

INPUT/OUTPUT

BUFFERS

Y DECODER

X DECODER

Y-GATING

7FFFFH

03FFFH

00000H

7FFFFH

7C000H

00000H

ADDRESS

INPUTS

MAIN MEMORY

(496K BYTES)

OPTIONAL BOOT

BLOCK (16K BYTES)

OPTIONAL BOOT

MAIN MEMORY

(496K BYTES)

BLOCK (16K BYTES)

Device Operation

READ: The AT49F040 is accessed like an EPROM. When

CE and OE are low and WE is high, the data stored at the

memory location determined by the address pins is

asserted on the outputs. The outputs are put in the high

impedance state whenever CE or OE is high. This dual-line

control gives designers flexibility in preventing bus conten-

tion.

grammed back to a “1”; only erase operations can convert

“0”s to “1”s. Programming is accomplished via the internal

device command register and is a 4 bus cycle operation

(please refer to the Command Definitions table). The

device will automatically generate the required internal pro-

gram pulses.

The program cycle has addresses latched on the falling

edge of WE or CE, whichever occurs last, and the data

latched on the rising edge of WE or CE, whichever occurs

first. Programming is completed after the specified t_BPcycle

time. The DATA polling feature may also be used to indi-

cate the end of a program cycle.

ERASURE: Before a byte can be reprogrammed, the

512K bytes memory array (or 496K bytes if the boot block

featured is used) must be erased. The erased state of the

memory bits is a logical “1”. The entire device can be

erased at one time by using a 6-byte software code. The

software chip erase code consists of 6-byte load com-

mands to specific address locations with a specific data

pattern (please refer to the Chip Erase Cycle Waveforms).

BOOT BLOCK PROGRAMMING LOCKOUT: The device

has one designated block that has a programming lockout

feature. This feature prevents programming of data in the

designated block once the feature has been enabled. The

size of the block is 16K bytes. This block, referred to as the

boot block, can contain secure code that is used to bring up

the system. Enabling the lockout feature will allow the boot

code to stay in the device while data in the rest of the

device is updated. This feature does not have to be acti-

vated; the boot block's usage as a write protected region is

optional to the user. The address range of the AT49F040

After the software chip erase has been initiated, the device

will internally time the erase operation so that no external

clocks are required. The maximum time needed to erase

the whole chip is t_EC. If the boot block lockout feature has

been enabled, the data in the boot sector will not be

erased.

BYTE PROGRAMMING: Oncethememoryarrayiserased,

the device is programmed (to a logical “0”) on a byte-by-

byte basis. Please note that a data ”0" cannot be pro-

AT49F040/040T

boot block is 00000H to 03FFFH while the address range

of the AT49F040T boot block is 7C000H to 7FFFFH.

DATA POLLING: The AT49F040 features DATA polling to

indicate the end of a program cycle. During a program

cycle an attempted read of the last byte loaded will result in

the complement of the loaded data on I/O7. Once the pro-

gram cycle has been completed, true data is valid on all

outputs and the next cycle may begin. DATA polling may

begin at any time during the program cycle.

Once the feature is enabled, the data in the boot block can

no longer be erased or programmed. Data in the main

memory block can still be changed through the regular pro-

gramming method. To activate the lockout feature, a series

of six program commands to specific addresses with spe-

cific data must be performed. Please refer to the Command

Definitions table.

TOGGLE BIT: In addition to DATA polling the AT49F040

provides another method for determining the end of a pro-

gram or erase cycle. During a program or erase operation,

successive attempts to read data from the device will result

in I/O6 toggling between one and zero. Once the program

cycle has completed, I/O6 will stop toggling and valid data

will be read. Examining the toggle bit may begin at any time

during a program cycle.

BOOT BLOCK LOCKOUT DETECTION: A software

method is available to determine if programming of the boot

block section is locked out. When the device is in the soft-

ware product identification mode (see Software Product

Identification Entry and Exit sections) a read from address

location 00002H will show if programming the boot block is

locked out. If the data on I/O0 is low, the boot block can be

programmed; if the data on I/O0 is high, the program lock-

out feature has been activated and the block cannot be

programmed. The software product identification code

should be used to return to standard operation.

HARDWARE DATA PROTECTION: Hardware features

protect against inadvertent programs to the AT49F040 in

the following ways: (a) V_CCsense: if V_CCis below 3.8V (typ-

ical), the program function is inhibited. (b) Program inhibit:

holding any one of OE low, CE high or WE high inhibits

program cycles. (c) Noise filter: pulses of less than 15 ns

(typical) on the WE or CE inputs will not initiate a program

cycle.

PRODUCT IDENTIFICATION: The product identification

mode identifies the device and manufacturer as Atmel. It

may be accessed by hardware or software operation. The

hardware operation mode can be used by an external pro-

grammer to identify the correct programming algorithm for

the Atmel product.

For details, see Operating Modes (for hardware operation)

or Software Product Identification. The manufacturer and

device code is the same for both modes.

Command Definition (in Hex)

Command

Sequence

Bus

Cycles

1st Bus

Cycle

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

6th Bus

Cycle

Addr

Data

D_OUT

Addr

Data Addr Data Addr Data

Addr

2AAA

Data Addr Data

Read

Addr

5555

XXXX

Chip Erase

2AAA

5555

Addr

5555

D_IN

5555

Byte Program

Boot Block Lockout⁽¹⁾

Product ID Entry

Product ID Exit⁽²⁾

Notes: 1. The 16K byte boot sector has the address range 00000H to 03FFFH for the AT49F040 and 7C000H to 7FFFFH for the

AT49F040T.

2. Either one of the Product ID exit commands can be used.

Absolute Maximum Ratings*

*NOTICE:

Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device reliability.

Temperature Under Bias................................ -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

All Input Voltages

(including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground.............................-0.6V to V_CC+ 0.6V

Voltage on OE

with Respect to Ground...................................-0.6V to +13.5V

AT49F040/040T

DC and AC Operating Range

AT49F040-70

0°C - 70°C

AT49F040-90

AT49F040-12

0°C - 70°C

Com.

0°C - 70°C

-40°C - 85°C

5V ± 10%

Operating

Temperature (Case)

Ind.

-40°C - 85°C

5V ± 10%

-40°C - 85°C

5V ± 10%

V_CCPower Supply

Operating Modes

Mode

V_IL

V_IH

V_IL

V_IH

X⁽¹⁾

V_IH

V_IL

I/O

Read

D_OUT

D_IN

Program⁽²⁾

Standby/Write Inhibit

Program Inhibit

Output Disable

Product Identification

High Z

V_IH

V_IL

V_IH

High Z

A1 - A18 = V_IL, A9 = V_H,⁽³⁾

A0 = V_IL

Manufacturer Code⁽⁴⁾

Device Code⁽⁴⁾

Hardware

V_IL

V_IH

A1 - A18 = V_IL, A9 = V_H,⁽³⁾

A0 = V_IH

A0 = V_IL, A1 - A18 = V_IL

A0 = V_IH, A1 - A18 = V_IL

Manufacturer Code⁽⁴⁾

Device Code⁽⁴⁾

Software⁽⁵⁾

Notes: 1. X can be V_ILor V_IH.

2. Refer to AC Programming Waveforms.

3. V_H= 12.0V ± 0.5V.

4. Manufacturer Code: 1FH, Device Code: 13H (AT49F040), 12H (AT49F040T).

5. See details under Software Product Identification Entry/Exit.

DC Characteristics

Symbol

Parameter

Condition

Min

Max

Units

µA

I_LI

Input Load Current

Output Leakage Current

V_IN= 0V to V_CC

V_I/O= 0V to V_CC

I_LO

Com.

Ind.

100

300

I_SB1

I_SB2

V_CCStandby Current CMOS

CE = V_CC- 0.3V to V_CC

V_CCStandby Current TTL

V_CCActive Current

CE = 2.0V to V_CC

(1)

I_CC

f = 5 MHz; I_OUT= 0 mA

V_IL

Input Low Voltage

0.8

V_IH

Input High Voltage

2.0

V_OL

V_OH1

V_OH2

Output Low Voltage

Output High Voltage

Output High Voltage CMOS

I_OL= 2.1 mA

.45

I_OH= -400 µA

2.4

4.2

I_OH= -100 µA; V_CC= 4.5V

Note:

1. In the erase mode, ICC is 90 mA.

AC Read Characteristics

AT49F040-70 AT49F040-90 AT49F040-12

Symbol Parameter

Min

Max

Min

Max

Min

Max

120

Units

t_ACC

Address to Output Delay

(1)

t_CE

t_OE

t_DF

CE to Output Delay

(2)

OE to Output Delay

(3)(4)

CE or OE to Output Float

t_OH

Output Hold from OE, CE or Address, whichever occurred first

AC Read Waveforms^(1)(2)(3)(4)

Notes: 1. CE may be delayed up to t_ACC- t_CEafter the address transition without impact on t_ACC

2. OE may be delayed up to t_CE- t_OEafter the falling edge of CE without impact on t_CEor by t_ACC- t_OEafter an address change

without impact on t_ACC

3. t_DFis specified from OE or CE whichever occurs first (C_L= 5 pF).

4. This parameter is characterized and is not 100% tested.

Input Test Waveforms and

Measurement Level

Output Test Load

t_R, t_F< 5 ns

Pin Capacitance

(f = 1 MHz, T = 25°C)⁽¹⁾

Typ

Max

Units

Conditions

V_IN= 0V

C_IN

C_OUT

Note:

V_OUT= 0V

1. This parameter is characterized and is not 100% tested.

AT49F040/040T

AC Byte Load Characteristics

Symbol

Parameter

Min

Max

Units

_AS, t_OES

Address, OE Set-up Time

Address Hold Time

t_AH

t_CS

t_CH

t_WP

t_DS

Chip Select Set-up Time

Chip Select Hold Time

Write Pulse Width (WE or CE)

Data Set-up Time

_DH, t_OEH

Data, OE Hold Time

Write Pulse Width High

t_WPH

AC Byte Load Waveforms

WE Controlled

CE Controlled

Program Cycle Characteristics

Symbol

Parameter

Min

Typ

Max

Units

µs

t_BP

Byte Programming Time

Address Set-up Time

Address Hold Time

Data Set-up Time

Data Hold Time

t_AS

t_AH

t_DS

t_DH

t_WP

Write Pulse Width

Write Pulse Width High

Erase Cycle Time

t_WPH

t_EC

seconds

Program Cycle Waveforms

Chip Erase Cycle Waveforms

Note:

OE must be high only when WE and CE are both low.

AT49F040/040T

Data Polling Characteristics⁽¹⁾

Symbol

Parameter

Min

Typ

Max

Units

t_DH

Data Hold Time

OE Hold Time

t_OEH

t_OE

OE to Output Delay⁽²⁾

Write Recovery Time

t_WR

Notes: 1. These parameters are characterized and not 100% tested.

2. See t_OEspec in AC Read Characteristics.

Data Polling Waveforms

Toggle Bit Characteristics⁽¹⁾

Symbol

Parameter

Min

Typ

Max

Units

t_DH

Data Hold Time

OE Hold Time

t_OEH

t_OE

t_OEHP

t_WR

OE to Output Delay⁽²⁾

OE High Pulse

150

Write Recovery Time

Notes: 1. These parameters are characterized and not 100% tested.

2. See t_OEspec in AC Read Characteristics.

Toggle Bit Waveforms^(1)(2)(3)

Notes: 1. Toggling eithr OE or CE or both OE and CE will operate toggle bit. The t_OEHPspecification must be met by the toggling

input(s).

2. Begining and ending state of I/O6 will vary.

3. Any address location may be used but the address should not vary.

Software Product

Boot Block Lockout

Identification Entry⁽¹⁾

Feature Enable Algorithm⁽¹⁾

LOAD DATA AA

ADDRESS 5555

LOAD DATA 55

ADDRESS 2AAA

LOAD DATA 55

ADDRESS 2AAA

LOAD DATA 80

ADDRESS 5555

LOAD DATA 90

ADDRESS 5555

LOAD DATA AA

ADDRESS 5555

LOAD DATA AA

ADDRESS 5555

LOAD DATA 55

ADDRESS 2AAA

ENTER PRODUCT

IDENTIFICATION

MODE^(2)(3)(5)

LOAD DATA 40

Software Product

Identification Exit⁽¹⁾

ADDRESS 5555

PAUSE 1 second⁽²⁾

LOAD DATA AA

LOAD DATA F0

ADDRESS 5555

ANY ADDRESS

Notes for boot block lockout feature enable:

LOAD DATA 55

ADDRESS 2AAA

EXIT PRODUCT

IDENTIFICATION

MODE⁽⁴⁾

1. Data Format: I/O7 - I/O0 (Hex);

Address Format: A14 - A0 (Hex).

2. Boot block lockout feature enabled.

LOAD DATA F0

ADDRESS 5555

EXIT PRODUCT

IDENTIFICATION

MODE ⁽⁴⁾

Notes for software product identification:

1. Data Format: I/O7 - I/O0 (Hex);

Address Format: A14 - A0 (Hex).

2. A1 - A18 = V_IL.

Manufacture Code is read for A0 = V_IL;

Device Code is read for A0 = V_IH.

3. The device does not remain in identification mode if

powered down.

4. The device returns to standard operation mode.

5. Manufacturer Code: 1FH

Device Code: 13H (AT49F040), 12H (AT49F040T).

AT49F040/040T

Ordering Information

I_CC(mA)

t_ACC

(ns)

Active

Standby

Ordering Code

Package

Operation Range

0.1

AT49F040-70JC

AT49F040-70PC

AT49F040-70TC

32J

Commercial

32P6

32T

(0° to 70°C)

0.3

0.1

0.3

AT49F040-70JI

AT49F040-70PI

AT49F040-70TI

32J

Industrial

32P6

32T

(-40° to 85°C)

AT49F040-90JC

AT49F040-90PC

AT49F040-90TC

32J

Commercial

32P6

32T

(0° to 70°C)

AT49F040-90JI

AT49F040-90PI

AT49F040-90TI

32J

Industrial

32P6

32T

(-40° to 85°C)

120

0.1

0.3

AT49F040-12JC

AT49F040-12PC

AT49F040-12TC

32J

Commercial

32P6

32T

(0° to 70°C)

AT49F040-12JI

AT49F040-12PI

AT49F040-12TI

32J

Industrial

32P6

32T

(-40° to 85°C)

Package Type

32J

32-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC)

32-Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)

32-Lead, Thin Small Outline Package (TSOP)

32P6

32T

Ordering Information

I_CC(mA)

t_ACC

(ns)

Active

Standby

Ordering Code

Package

Operation Range

0.1

AT49F040T-70JC

AT49F040T-70PC

AT49F040T-70TC

32J

Commercial

32P6

32T

(0° to 70°C)

0.3

0.1

0.3

0.1

0.3

AT49F040T-70JI

AT49F040T-70PI

AT49F040T-70TI

32J

Industrial

32P6

32T

(-40° to 85°C)

AT49F040T-90JC

AT49F040T-90PC

AT49F040T-90TC

32J

Commercial

32P6

32T

(0° to 70°C)

AT49F040T-90JI

AT49F040T-90PI

AT49F040T-90TI

32J

Industrial

32P6

32T

(-40° to 85°C)

120

AT49F040T-12JC

AT49F040T-12PC

AT49F040T-12TC

32J

Commercial

32P6

32T

(0° to 70°C)

AT49F040T-12JI

AT49F040T-12PI

AT49F040T-12TI

32J

Industrial

32P6

32T

(-40° to 85°C)

Package Type

32J

32-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC)

32-Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)

32-Lead, Thin Small Outline Package (TSOP)

32P6

32T

AT49F040/040T

AT49F040-90PI [ATMEL]

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