AT49F040A [ATMEL]

4-megabit (512K x 8) 5-volt Only Flash Memory; 4兆位（ 512K ×8 ）， 5伏只有闪存


型号：	AT49F040A
厂家：	ATMEL
描述：	4-megabit (512K x 8) 5-volt Only Flash Memory 4兆位（ 512K ×8 ）， 5伏只有闪存闪存
文件：	总16页 (文件大小：264K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Features

• Single-voltage Operation

– 5V Read

– 5V Reprogramming

• Fast Read Access Time – 55 ns

• Internal Program Control and Timer

• Sector Architecture

– One 16K Bytes Boot Block with Programming Lockout

– Two 8K Bytes Parameter Blocks

– Eight Main Memory Blocks (One 32K Bytes, Seven 64K Bytes)

• Fast Erase Cycle Time – 6 Seconds

• Byte-by-Byte Programming – 20 µs/Byte Typical

• Hardware Data Protection

• DATA Polling for End of Program Detection

• Low Power Dissipation

– 20 mA Active Current

– 70 µA CMOS Standby Current

• Typical 10,000 Write Cycles

4-megabit

(512K x 8)

5-volt Only

Flash Memory

Description

AT49F040A

The AT49F040A is a 5-volt only in-system reprogrammable Flash memory. Its

4 megabits of memory is organized as 524,288 words by 8 bits. Manufactured with

Atmel’s advanced nonvolatile CMOS technology, the device offers access times to

55 ns with power dissipation of just 110 mW over the commercial temperature range.

Pin Configurations

Pin Name Function

TSOP Top View (8 x 20 mm)

Type 1

A0 - A18

Addresses

Chip Enable

Output Enable

Write Enable

A11

A10

A13

A14

A17

VCC

A18

A16

A15

A12

I/O7

I/O6

I/O5

I/O4

I/O3

GND

I/O2

I/O1

I/O0

I/O0 - I/O7 Data Inputs/Outputs

PLCC Top View

29 A14

28 A13

27 A8

26 A9

25 A11

24 OE

23 A10

22 CE

21 I/O7

A2 10

A1 11

A0 12

I/O0 13

3359B–FLASH–10/04

When the device is deselected, the CMOS standby current is less than 70 µA. To allow for

simple in-system reprogrammability, the AT49F040A does not require high input voltages for

programming. Five-volt-only commands determine the read and programming operation of the

device. Reading data out of the device is similar to reading from an EPROM; it has standard

CE, OE, and WE inputs to avoid bus contention. Reprogramming the AT49F040A is per-

formed by erasing a block of data and then programming on a byte-by-byte basis. The byte

programming time is a fast 20 µs. The end of a program cycle can be optionally detected by

the DATA polling feature. Once the end of a byte program cycle has been detected, a new

access for a read or program can begin. The typical number of program and erase cycles is in

excess of 10,000 cycles.

The device is erased by executing the erase command sequence; the device internally con-

trols the erase operations. There are two 8K byte parameter block sections, eight main

memory blocks, and one boot block.

The device has the capability to protect the data in the boot block; this feature is enabled by a

command sequence. The 16K-byte boot block section includes a reprogramming lock out fea-

ture to provide data integrity. The boot sector is designed to contain user secure code, and

when the feature is enabled, the boot sector is permanently protected from being

reprogrammed.

Block Diagram

AT49F040A

DATA INPUTS/OUTPUTS

I/O7 - I/O0

VCC

GND

INPUT/OUTPUT

BUFFERS

CONTROL

LOGIC

PROGRAM

RESET

DATA LATCHES

Y DECODER

X DECODER

Y-GATING

ADDRESS

INPUTS

7FFFF

MAIN MEMORY

BLOCK 8

(64K BYTES)

70000

6FFFF

MAIN MEMORY

BLOCK 7

(64K BYTES)

60000

5FFFF

MAIN MEMORY

BLOCK 6

(64K BYTES)

50000

4FFFF

MAIN MEMORY

BLOCK 5

(64K BYTES)

40000

3FFFF

MAIN MEMORY

BLOCK 4

(64K BYTES)

30000

2FFFF

MAIN MEMORY

BLOCK 3

(64K BYTES)

20000

1FFFF

MAIN MEMORY

BLOCK 2

(64K BYTES)

10000

0FFFF

MAIN MEMORY

BLOCK 1

(32K BYTES)

08000

07FFF

PARAMETER

BLOCK 2

(8K BYTES)

06000

05FFF

PARAMETER

BLOCK 1

(8K BYTES)

04000

03FFF

BOOT BLOCK

(16K BYTES)

00000

AT49F040A

3359B–FLASH–10/04

AT49F040A

Device

Operation

READ: The AT49F040A is accessed like an EPROM. When CE and OE are low and WE is

high, the data stored at the memory location determined by the address pins is asserted on

the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This

dual-line control gives designers flexibility in preventing bus contention.

COMMAND SEQUENCES: When the device is first powered on, it will be reset to the read or

standby mode depending upon the state of the control line inputs. In order to perform other

device functions, a series of command sequences are entered into the device. The command

sequences are shown in the Command Definitions table. The command sequences are written

by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high.

The address is latched on the falling edge of CE or WE, whichever occurs last. The data is

latched by the first rising edge of CE or WE. Standard microprocessor write timings are used.

The address locations used in the command sequences are not affected by entering the com-

mand sequences.

ERASURE: Before a byte can be reprogrammed, the main memory block or parameter block

which contains the byte must be erased. The erased state of the memory bits is a logical “1”.

The entire device can be erased at one time by using a 6-byte software code. The software

chip erase code consists of 6-byte load commands to specific address locations with a specific

data pattern (please refer to the Chip Erase Cycle Waveforms).

After the software chip erase has been initiated, the device will internally time the erase opera-

tion so that no external clocks are required. The maximum time needed to erase the whole

chip is t_EC. If the boot block lockout feature has been enabled, the data in the boot sector will

not be erased.

CHIP ERASE: If the boot block lockout has been enabled, the Chip Erase function will erase

Parameter Block 1, Parameter Block 2, Main Memory Block 1 - 8 but not the boot block. If the

Boot Block Lockout has not been enabled, the Chip Erase function will erase the entire chip.

After the full chip erase the device will return back to read mode. Any command during chip

erase will be ignored.

SECTOR ERASE: As an alternative to a full chip erase, the device is organized into sectors

that can be individually erased. There are two 8K-byte parameter block sections and eight

main memory blocks. The 8K-byte parameter block sections and the eight main memory

blocks can be independently erased and reprogrammed. The Sector Erase command is a six

bus cycle operation. The sector address is latched on the falling WE edge of the sixth cycle

while the 30H data input command is latched at the rising edge of WE. The sector erase starts

after the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will

automatically time to completion.

BYTE PROGRAMMING: Once the memory array is erased, the device is programmed (to a

logical “0”) on a byte-by-byte basis. Please note that a data “0” cannot be programmed back to

a “1”; only erase operations can convert “0”s to “1”s. Programming is accomplished via the

internal device command register and is a 4 bus cycle operation (please refer to the Command

Definitions table). The device will automatically generate the required internal program pulses.

The program cycle has addresses latched on the falling edge of WE or CE, whichever occurs

last, and the data latched on the rising edge of WE or CE, whichever occurs first. Program-

ming is completed after the specified t_BPcycle time. The DATA polling feature may also be

used to indicate the end of a program cycle.

BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has

a programming lockout feature. This feature prevents programming of data in the designated

block once the feature has been enabled. The size of the block is 16K bytes. This block,

referred to as the boot block, can contain secure code that is used to bring up the system.

3359B–FLASH–10/04

Enabling the lockout feature will allow the boot code to stay in the device while data in the rest

of the device is updated. This feature does not have to be activated; the boot block’s usage as

a write protected region is optional to the user. The address range of the boot block is 00000

to 03FFF.

Once the feature is enabled, the data in the boot block can no longer be erased or pro-

grammed. Data in the main memory block can still be changed through the regular

programming method. To activate the lockout feature, a series of six program commands to

specific addresses with specific data must be performed. Please refer to the Command Defini-

tions table.

BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if pro-

gramming of the boot block section is locked out. When the device is in the software product

identification mode (see Software Product Identification Entry and Exit sections) a read from

address location 00002H will show if programming the boot block is locked out. If the data on

I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the program lockout

feature has been activated and the block cannot be programmed. The software product identi-

fication exit code should be used to return to standard operation.

PRODUCT IDENTIFICATION: The product identification mode identifies the device and man-

ufacturer as Atmel. It may be accessed by hardware or software operation. The hardware

operation mode can be used by an external programmer to identify the correct programming

algorithm for the Atmel product.

For details, see Operating Modes (for hardware operation) or Software Product Identification.

The manufacturer and device code is the same for both modes.

DATA POLLING: The AT49F040A features DATA polling to indicate the end of a program

cycle. During a program cycle an attempted read of the last byte loaded will result in the com-

plement of the loaded data on I/O7. Once the program cycle has been completed, true data is

valid on all outputs and the next cycle may begin. DATA polling may begin at any time during

the program cycle.

TOGGLE BIT: In addition to DATA polling the AT49F040A provides another method for deter-

mining the end of a program or erase cycle. During a program or erase operation, successive

attempts to read data from the device will result in I/O6 toggling between one and zero. Once

the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examin-

ing the toggle bit may begin at any time during a program cycle.

HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs

to the AT49F040A in the following ways: (a) V_CCsense: if V_CCis below 3.8V (typical), the pro-

gram function is inhibited. (b) Program inhibit: holding any one of OE low, CE high or WE high

inhibits program cycles. (c) Noise filter: pulses of less than 15 ns (typical) on the WE or CE

inputs will not initiate a program cycle.

AT49F040A

3359B–FLASH–10/04

AT49F040A

Command Definition (in Hex)⁽¹⁾

1st Bus

Cycle

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

6th Bus

Cycle

Command

Sequence

Bus

Cycles

Addr

555

Data

D_OUT

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Read

Chip Erase

AAA⁽²⁾

AAA

555

D_IN

AAA

555

Sector Erase

555

SA⁽⁵⁾

Byte Program

Boot Block Lockout⁽³⁾

Product ID Entry

Product ID Exit⁽⁴⁾

555

Addr

555

AAA

555

XXXX

Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O7 - I/O0 (Hex). The address format in each bus cycle is as follows:

A11 - A0 (Hex); A11 - A18 (don’t care).

2. Since A11 is don’t care, AAA can be replaced with 2AA.

3. The 16K byte boot sector has the address range 00000H to 03FFFH.

4. Either one of the Product ID Exit commands can be used.

5. SA = sector addresses:

SA = 00000 to 03FFF for BOOT BLOCK

SA = 04000 to 05FFF for PARAMETER BLOCK 1

SA = 06000 to 07FFF for PARAMETER BLOCK 2

SA = 08000 to FFFF for MAIN MEMORY ARRAY BLOCK 1

SA = 10000 to 1FFFF for MAIN MEMORY ARRAY BLOCK 2

SA = 20000 to 2FFFF for MAIN MEMORY ARRAY BLOCK 3

SA = 30000 to 3FFFF for MAIN MEMORY ARRAY BLOCK 4

SA = 40000 to 4FFFF for MAIN MEMORY ARRAY BLOCK 5

SA = 50000 to 5FFFF for MAIN MEMORY ARRAY BLOCK 6

SA = 60000 to 6FFFF for MAIN MEMORY ARRAY BLOCK 7

SA = 70000 to 7FFFF for MAIN MEMORY ARRAY BLOCK 8

Absolute Maximum Ratings*

*NOTICE:

Stresses beyond those listed under “Absolute Maxi-

mum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional

operation of the device at these or any other condi-

tions beyond those indicated in the operational sec-

tions of this specification is not implied. Exposure to

absolute maximum rating conditions for extended

periods may affect device reliability.

Temperature Under Bias................................ -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

All Input Voltages

(including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground.............................-0.6V to V_CC+ 0.6V

Voltage on OE

with Respect to Ground...................................-0.6V to +13.5V

3359B–FLASH–10/04

DC and AC Operating Range

AT49F040A-55

-40°C - 85°C

5V 10ꢀ

AT49F040A-70

-40°C - 85°C

5V 10ꢀ

Operating Temperature (Case)

V_CCPower Supply

Ind.

Operating Modes

Mode

V_IL

V_IH

V_IL

V_IH

X⁽¹⁾

V_IH

V_IL

I/O

Read

D_OUT

D_IN

Program/Erase⁽²⁾

Standby/Write Inhibit

High Z

V_IH

Program Inhibit

V_IL

V_IH

Output Disable

Reset

High Z

Product Identification

A1 - A18 = V_IL, A9 = V_H,⁽³⁾A0 = V_IL

A1 - A18 = V_IL, A9 = V_H,⁽³⁾A0 = V_IH

A0 = V_IL, A1 - A18 =V_IL

Manufacturer Code⁽⁴⁾

Device Code⁽⁴⁾

Hardware

V_IL

V_IH

Manufacturer Code⁽⁴⁾

Device Code⁽⁴⁾

Software⁽⁵⁾

A0 = V_IH, A1 - A18 =V_IL

Notes: 1. X can be V_ILor V_IH.

2. Refer to AC Programming Waveforms.

3. V_H= 12.0V 0.5V.

4. Manufacturer Code: 1FH, Device Code: 13H.

5. See details under Software Product Identification Entry/Exit.

DC Characteristics

Symbol

Parameter

Condition

Min

Max

Units

I_LI

Input Load Current

Output Leakage Current

V_CCStandby Current CMOS

V_CCStandby Current TTL

V_CCActive Current

Input Low Voltage

V_IN= 0V to V_CC

µA

I_LO

V_I/O= 0V to V_CC

I_SB1

CE = V_CC- 0.3V to V_CC

CE = 2.0V to V_CC

f = 5 MHz; I_OUT= 0 mA

I_SB2

(1)

I_CC

0.8

V_IL

V_IH

Input High Voltage

Output Low Voltage

Output High Voltage

2.0

2.4

V_OL

V_OH1

V_OH2

I_OL= 2.1 mA

I_OH= -400 µA

0.45

Output High Voltage CMOS

I_OH= -100 µA; V_CC= 4.5V

4.2

Note:

1. In the erase mode, I_CCis 90 mA.

AT49F040A

3359B–FLASH–10/04

AT49F040A

AC Read Characteristics

AT49F040A-55

AT49F040A-70

Symbol

Parameter

Min

Max

Min

Max

Units

t_ACC

Address to Output Delay

CE to Output Delay

OE to Output Delay

CE or OE to Output Float

(1)

t_CE

(2)

t_OE

(3)(4)

t_DF

t_OH

Output Hold from OE, CE or Address, whichever

occurred first

AC Read Waveforms ^(1)(2)(3)(4)

ADDRESS

ADDRESS VALID

t_CE

t_OE

t_DF

t_OH

t_ACC

HIGH Z

OUTPUT

VALID

OUTPUT

Notes: 1. CE may be delayed up to t_ACC- t_CEafter the address transition without impact on t_ACC

2. OE may be delayed up to t_CE- t_OEafter the falling edge of CE without impact on t_CEor by t_ACC- t_OEafter an address change

without impact on t_ACC

3. t_DFis specified from OE or CE whichever occurs first (CL = 5 pF).

4. This parameter is characterized and is not 100ꢀ tested.

3359B–FLASH–10/04

Input Test Waveform and Measurement Level

t_R, t_F< 5 ns

Output Load Test

55 ns

5.0V

1.8K

OUTPUT

30 pF

1.3K

Pin Capacitance

f = 1 MHz, T = 25°C⁽¹⁾

Symbol

C_IN

Typ

Max

Units

Conditions

V_IN= 0V

C_OUT

V_OUT= 0V

Note:

1. This parameter is characterized and is not 100ꢀ tested.

AT49F040A

3359B–FLASH–10/04

AT49F040A

AC Byte Load Characteristics

Symbol

Parameter

Min

Max

Units

_AS, t_OES

Address, OE Set-up Time

Address Hold Time

t_AH

t_CS

Chip Select Set-up Time

Chip Select Hold Time

Write Pulse Width (WE or CE)

Data Set-up Time

t_CH

t_WP

t_DS

t_DH, t_OEH

t_WPH

Data, OE Hold Time

Write Pulse Width High

AC Byte Load Waveforms

WE Controlled

t_OES

t_OEH

ADDRESS

t_AS

t_AH

t_CH

t_CS

t_WPH

t_WP

t_DH

t_DS

DATA IN

CE Controlled

t_OES

t_OEH

ADDRESS

t_AS

t_AH

t_CH

t_CS

t_WPH

t_WP

t_DH

t_DS

DATA IN

3359B–FLASH–10/04

Program Cycle Characteristics

Symbol

Parameter

Min

Typ

Max

Units

µs

t_BP

Byte Programming Time

Address Set-up Time

Address Hold Time

Data Set-up Time

Data Hold Time

t_AS

t_AH

t_DS

t_DH

t_WP

Write Pulse Width

Write Pulse Width High

Erase Cycle Time

t_WPH

t_EC

seconds

Program Cycle Waveforms

Sector or Chip Erase Cycle Waveforms

Notes: 1. OE must be high only when WE and CE are both low.

2. For chip erase, the address should be 555. For sector erase, the address depends on what sector is to be erased.

(See note 4 under command definitions.)

3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.

AT49F040A

3359B–FLASH–10/04

AT49F040A

Data Polling Characteristics⁽¹⁾

Symbol

Parameter

Min

Typ

Max

Units

t_DH

Data Hold Time

t_OEH

t_OE

OE Hold Time

OE to Output Delay⁽²⁾

Write Recovery Time

t_WR

Notes: 1. These parameters are characterized and not 100ꢀ tested.

2. See t_OEspec in AC Read Characteristics.

Data Polling Waveforms

OEH

HIGHZ

I/O7

A0-A18

Toggle Bit Characteristics⁽¹⁾

Symbol

Parameter

Min

Typ

Max

Units

t_DH

Data Hold Time

t_OEH

t_OE

t_OEHP

t_WR

OE Hold Time

OE to Output Delay⁽²⁾

OE High Pulse

Write Recovery Time

Notes: 1. These parameters are characterized and not 100ꢀ tested.

2. See t_OEspec in AC Read Characteristics.

Toggle Bit Waveforms^(1)(2)(3)

t_OEH

t_OEHP

t_OE

t_DH

HIGH Z

I/O6

t_WR

Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The t_OEHPspecification must be met by the toggling

input(s).

2. Beginning and ending state of I/O6 will vary.

3. Any address location may be used but the address should not vary.

3359B–FLASH–10/04

Software Product Identification

Entry⁽¹⁾

Boot Block Lockout Feature Enable

Algorithm⁽¹⁾

LOAD DATA AA

ADDRESS 555

LOAD DATA 55

ADDRESS AAA

LOAD DATA 80

ADDRESS 555

LOAD DATA 90

ADDRESS 555

LOAD DATA AA

ADDRESS 555

ENTER PRODUCT

IDENTIFICATION

(2)(3)(5)

MODE

LOAD DATA 55

ADDRESS AAA

Software Product Identification Exit⁽¹⁾

LOAD DATA AA

LOAD DATA F0

LOAD DATA 40

ADDRESS 555

ANY ADDRESS

LOAD DATA 55

ADDRESS AAA

EXIT PRODUCT

IDENTIFICATION

(2)

PAUSE 1 second

(4)

MODE

LOAD DATA F0

ADDRESS 555

Notes: 1. Data Format: I/O7 - I/O0 (Hex);

Address Format: A11 - A0 (Hex).

2. Boot block lockout feature enabled.

EXIT PRODUCT

IDENTIFICATION

(4)

MODE

Notes: 1. Data Format: I/O7 - I/O0 (Hex);

Address Format: A11 - A0 (Hex).

2. A1 - A18 = V_IL.

Manufacture Code is read for A0 = V_IL;

Device Code is read for A0 = V_IH.

Additional Device Code is read for address 0003H

3. The device does not remain in identification mode

if powered down.

4. The device returns to standard operation mode.

5. Manufacturer Code: 1FH

Device Code: 13H

Additional Device Code: 0FH

AT49F040A

3359B–FLASH–10/04

AT49F040A

AT49F040A Ordering Information

_CC(mA)

t_ACC

(ns)

Active

Standby

Ordering Code

Package

Operation Range

0.1

AT49F040A-55JI

AT49F040A-55TI

32J

32T

Industrial

(-40° to 85°C)

0.1

AT49F040A-70JI

AT49F040A-70TI

32J

32T

Industrial

(-40° to 85°C)

Package Type

32J

32-lead, Plastic J-leaded Chip Carrier Package (PLCC)

32T

32-lead, Plastic Thin Small Outline Package (TSOP) (8 x 20 mm)

3359B–FLASH–10/04

Packaging Information

32J – PLCC

1.14(0.045) X 45˚

PIN NO. 1

IDENTIFIER

1.14(0.045) X 45˚

0.318(0.0125)

0.191(0.0075)

0.51(0.020)MAX

45˚ MAX (3X)

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

3.175

1.524

0.381

12.319

11.354

9.906

14.859

13.894

12.471

0.660

0.330

MAX

3.556

2.413

–

NOM

NOTE

SYMBOL

–

12.573

–

11.506 Note 2

10.922

–

Notes:

1. This package conforms to JEDEC reference MS-016, Variation AE.

2. Dimensions D1 and E1 do not include mold protrusion.

Allowable protrusion is .010"(0.254 mm) per side. Dimension D1

and E1 include mold mismatch and are measured at the extreme

material condition at the upper or lower parting line.

–

15.113

–

14.046 Note 2

13.487

–

0.813

3. Lead coplanarity is 0.004" (0.102 mm) maximum.

0.533

1.270 TYP

10/04/01

TITLE

DRAWING NO.

REV.

2325 Orchard Parkway

San Jose, CA 95131

32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)

32J

AT49F040A

3359B–FLASH–10/04

AT49F040A

32T – TSOP

PIN 1

0º ~ 8º

Pin 1 Identifier

GAGE PLANE

SEATING PLANE

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

–

MAX

1.20

0.15

1.05

20.20

NOM

–

NOTE

SYMBOL

0.05

0.95

19.80

18.30

7.90

0.50

–

1.00

Notes:

1. This package conforms to JEDEC reference MO-142, Variation BD.

2. Dimensions D1 and E do not include mold protrusion. Allowable

protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.

3. Lead coplanarity is 0.10 mm maximum.

20.00

18.40

8.00

18.50 Note 2

8.10

0.70

Note 2

0.60

0.25 BASIC

0.22

0.17

0.10

0.27

0.21

–

0.50 BASIC

10/18/01

DRAWING NO. REV.

32T

TITLE

2325 Orchard Parkway

San Jose, CA 95131

32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline

Package, Type I (TSOP)

3359B–FLASH–10/04

Atmel Corporation

Atmel Operations

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

Memory

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Theresienstrasse 2

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Tel: (49) 71-31-67-0

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San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

Regional Headquarters

Microcontrollers

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Tel: 1(408) 441-0311

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Tel: (852) 2721-9778

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ASIC/ASSP/Smart Cards

Zone Industrielle

13106 Rousset Cedex, France

Tel: (33) 4-42-53-60-00

Fax: (33) 4-42-53-60-01

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906, USA

Tel: 1(719) 576-3300

Japan

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

Tel: (81) 3-3523-3551

Fax: (81) 3-3523-7581

Fax: 1(719) 540-1759

Scottish Enterprise Technology Park

Maxwell Building

East Kilbride G75 0QR, Scotland

Tel: (44) 1355-803-000

Fax: (44) 1355-242-743

Literature Requests

www.atmel.com/literature

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