AT49F4096 [ATMEL]
4 Megabit 256K x 16 5-volt Only CMOS Flash Memory; 4兆位256K ×16的5伏只有CMOS闪存
| 型号： | AT49F4096 |
| 厂家： | 
ATMEL |
| 描述： | 4 Megabit 256K x 16 5-volt Only CMOS Flash Memory |
| 文件： | 总11页 (文件大小：647K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AT49F4096
Features
Single Voltage Operation
•
- 5V Read
- 5V Reprogramming
Fast Read Access Time - 90 ns
Internal Erase/Program Control
Sector Architecture
•
•
•
- One 8K Words (16K bytes) Boot Block with Programming Lockout
- Two 8K Words (16K bytes) Parameter Blocks
- One 232K Words (464K bytes) Main Memory Array Block
Fast Sector Erase Time - 10 seconds
Word-By-Word Programming - 50 µs/Word
Hardware Data Protection
DATA Polling For End Of Program Detection
Low Power Dissipation
- 50 mA Active Current
- 300 µA CMOS Standby Current
Typical 10,000 Write Cycles
4 Megabit
(256K x 16)
5-volt Only
CMOS Flash
Memory
•
•
•
•
•
•
Description
The AT49F4096 is a 5-volt-only, 4 megabit Flash Memory organized as 256K words
of 16 bits each. Manufactured with Atmel’s advanced nonvolatile CMOS technology,
the device offers access times to 90 ns with power dissipation of just 275 mW. When
Preliminary
deselected, the CMOS standby current is less than 300 µA.
(continued)
Pin Configurations
Pin Name
A0 - A17
CE
Function
Addresses
Chip Enable
Output Enable
Write Enable
Reset
AT49F4096
OE
WE
RESET
Data
Inputs/Outputs
I/O0 - I/O15
NC
SOIC (SOP)
No Connect
TSOP Top View
Type 1
0569C
4-219
Description (Continued)
To allow for simple in-system reprogrammability, the
AT49F4096 does not require high input voltages for pro-
gramming. Five-volt-only commands determine the read
and programming operation of the device. Reading data
out of the device is similar to reading from an EPROM; it
has standard CE, OE, and WE inputs to avoid bus conten-
tion. Reprogramming the AT49F4096 is performed by first
erasing a block of data and then programming on a word-
by-word basis.
memory array block. The AT49F4096 is programmed on a
word-by-word basis.
The device has the capability to protect the data in the
boot block; this feature is enabled by a command se-
quence. Once the boot block programming lockout feature
is enabled, the data in the boot block cannot be changed
when input levels of 5.5 volts or less are used. The typical
number of program and erase cycles is in excess of
10,000 cycles.
The device is erased by executing the erase command
sequence; the device internally controls the erase opera-
tion. The memory is divided into three blocks for erase op-
erations. There are two 8K word parameter block sections
and one sector consisting of the boot block and the main
The optional 8K word boot block section includes a repro-
gramming lock out feature to provide data integrity. The
boot sector is designed to contain user secure code, and
when the feature is enabled, the boot sector is protected
from being reprogrammed.
Block Diagram
Device Operation
RESET: A RESET input pin is provided to ease some
system applications. When RESET is at a logic high level,
the device is in its standard operating mode. A low level on
the RESET input halts the present device operation and
puts the outputs of the device in a high impedance state.
When a high level is reasserted on the RESET pin, the
device returns to the Read or Standby mode, depending
upon the state of the control inputs. By applying a 12V ±
0.5V input signal to the RESET pin the boot block array
can be reprogrammed even if the boot block program lock-
out feature has been enabled (see Boot Block Program-
ming Lockout Override section).
READ: The AT49F4096 is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-
line control gives designers flexibility in preventing bus
contention.
COMMAND SEQUENCES: When the device is first pow-
ered on it will be reset to the read or standby mode de-
pending upon the state of the control line inputs. In order
to perform other device functions, a series of command
sequences are entered into the device. The command se-
quences are shown in the Command Definitions table
(I/O8 - I/O15 are don’t care inputs for the command
codes). The command sequences are written by applying
a low pulse on the WE or CE input with CE or WE low
(respectively) and OE high. The address is latched on the
falling edge of CE or WE, whichever occurs last. The data
is latched by the first rising edge of CE or WE. Standard
microprocessor write timings are used. The address loca-
tions used in the command sequences are not affected by
entering the command sequences.
ERASURE: Before a word can be reprogrammed, it must
be erased. The erased state of the memory bits is a logical
“1”. The entire device can be erased at one time by using
a 6-byte software code.
After the software chip erase has been initiated, the device
will internally time the erase operation so that no external
clocks are required. The maximum time needed to erase
the whole chip is t
.
EC
(continued)
4-220
AT49F4096
AT49F4096
Device Operation (Continued)
CHIP ERASE: If the boot block lockout has been en-
abled, the Chip Erase function is disabled; sector erases
for the parameter blocks and main memory block will still
operate. After the full chip erase the device will return back
to read mode. Any command during chip erase will be ig-
nored.
still be changed through the regular programming method.
To activate the lockout feature, a series of six program
commands to specific addresses with specific data must
be performed. Please refer to the Command Definitions
table.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the
boot block section is locked out. When the device is in the
software product identification mode (see Software Prod-
uct Identification Entry and Exit sections) a read from ad-
dress location 00002H will show if programming the boot
block is locked out. If the data on I/O0 is low, the boot
block can be programmed; if the data on I/O0 is high, the
program lockout feature has been enabled and the block
cannot be programmed. The software product identifica-
tion exit code should be used to return to standard opera-
tion.
SECTOR ERASE: As an alternative to a full chip erase,
the device is organized into three sectors that can be indi-
vidually erased. There are two 8K word parameter block
sections and one sector consisting of the boot block and
the main memory array block. The Sector Erase command
is a six bus cycle operation. The sector address is latched
on the falling WE edge of the sixth cycle while the 30H
data input command is latched at the rising edge of WE.
The sector erase starts after the rising edge of WE of the
sixth cycle. The erase operation is internally controlled; it
will automatically time to completion. When the boot block
programming lockout feature is not enabled, the boot
block and the main memory block will erase together (from
the same sector erase command). Once the boot region
has been protected, only the main memory array sector
will erase when its sector erase command is issued.
BOOT BLOCK PROGRAMMING LOCKOUT OVER-
RIDE: The user can override the boot block programming
lockout by taking the RESET pin to 12 volts. By doing this
protected boot block data can be altered through a chip
erase, sector erase or word programming. When the RE-
SET pin is brought back to TTL levels the boot block pro-
gramming lockout feature is again active.
WORD PROGRAMMING: Once a memory block is
erased, it is programmed (to a logical “0”) on a word-by-
word basis. Programming is accomplished via the internal
device command register and is a 4 bus cycle operation.
The device will automatically generate the required inter-
nal program pulses.
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
Any commands written to the chip during the embedded
programming cycle will be ignored. If a hardware reset
happens during programming, the data at the location be-
ing programmed will be corrupted. Please note that a data
“0” cannot be programmed back to a “1”; only erase opera-
tions can convert “0”s to “1”s. Programming is completed
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING: The AT49F4096 features DATA polling
to indicate the end of a program cycle. During a program
cycle an attempted read of the last byte loaded will result
in the complement of the loaded data on I/O7. Once the
program cycle has been completed, true data is valid on
all outputs and the next cycle may begin. During a chip or
sector erase operation, an attempt to read the device will
give a “0” on I/O7. Once the program or erase cycle has
completed, true data will be read from the device. DATA
polling may begin at any time during the program cycle.
after the specified t cycle time. The DATA polling fea-
ture may also be used to indicate the end of a program
cycle.
BP
BOOT BLOCK PROGRAMMING LOCKOUT: The de-
vice has one designated block that has a programming
lockout feature. This feature prevents programming of
data in the designated block once the feature has been
enabled. The size of the block is 8K words. This block,
referred to as the boot block, can contain secure code that
is used to bring up the system. Enabling the lockout fea-
ture will allow the boot code to stay in the device while data
in the rest of the device is updated. This feature does not
have to be activated; the boot block’s usage as a write
protected region is optional to the user. The address range
of the boot block is 00000H to 01FFFH.
TOGGLE BIT: I n a d d i t i o n t o DATA polling the
AT49F4096 provides another method for determining the
end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from
the device will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will
stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.
Once the feature is enabled, the data in the boot block can
no longer be erased or programmed when input levels of
5.5V or less are used. Data in the main memory block can
(continued)
4-221
Device Operation (Continued)
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT49F4096 in
thedevicewillautomatically time out 10 ms (typical) be-
fore programming. (c) Program inhibit: holding any one of
OE low, CE high or WE high inhibits program cycles. (d)
Noise filter: pulses of less than 15 ns (typical) on the WE
or CE inputs will not initiate a program cycle.
the following ways: (a) V
sense: if V
is below 3.8V
CC
CC
(typical), the program function is inhibited. (b) V power
CC
on delay: once V
has reached the V
sense level,
CC
CC
Command Definition (in Hex) (1)
Command Bus
Sequence Cycles
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Addr
Data
DOUT
AA
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
1
6
Addr
5555
Read
2AAA
2AAA
55
55
5555
5555
80
80
5555
5555
AA
AA
2AAA
2AAA
55
55
5555
10
30
Chip Erase
Sector
Erase
6
4
6
3
3
1
5555
5555
5555
5555
5555
xxxx
AA
AA
AA
AA
AA
F0
SA (4, 5)
Word
Program
2AAA
2AAA
2AAA
2AAA
55
55
55
55
5555
5555
5555
5555
A0
80
90
F0
Addr
5555
DIN
AA
Boot Block
Lockout
2AAA
55
5555
40
(2)
Product ID
Entry
Product ID
(3)
Exit
Product ID
(3)
Exit
Notes: 1. The DATA FORMAT in each bus cycle is as follows:
I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)
2. The 8K word boot sector has the address range
00000H to 01FFFH.
5. When the boot block programming lockout feature
is not enabled, the boot block and the main memory block
will erase together (from the same sector erase command).
Once the boot region has been protected, only the main
memory array sector will erase when its sector erase
command is issued.
3. Either one of the Product ID Exit commands can
be used.
4. SA = sector addresses:
SA = 03XXX for PARAMETER BLOCK 1
SA = 05XXX for PARAMETER BLOCK 2
SA = 3FXXX for MAIN MEMORY ARRAY
Absolute Maximum Ratings*
Temperature Under Bias................. -55°C to +125°C
Storage Temperature...................... -65°C to +150°C
All Input Voltages
(including NC Pins)
*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
with Respect to Ground ................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground .............-0.6V to V + 0.6V
CC
Voltage on OE
with Respect to Ground ................... -0.6V to +13.5V
4-222
AT49F4096
AT49F4096
DC and AC Operating Range
AT49F4096-90
0°C - 70°C
AT49F4096-12
0°C - 70°C
Com.
Ind.
Operating
Temperature (Case)
-40°C - 85°C
5V ± 10%
-40°C - 85°C
5V ± 10%
V
Power Supply
CC
Operating Modes
RESET
Mode
CE
OE
WE
Ai
Ai
Ai
I/O
Read
V
IL
IL
V
IL
V
IH
V
V
D
D
IH
IH
OUT
IN
(2)
Program/Erase
V
V
V
IH
IL
Standby/Write
Inhibit
(1)
V
X
X
V
X
High Z
IH
IH
Program Inhibit
Program Inhibit
Output Disable
Reset
X
X
V
V
V
V
IH
IH
IH
IH
X
X
X
V
IL
X
V
X
X
High Z
High Z
IH
X
X
V
IL
Product
Identification
A1 - A17 = VIL, A9 = VH, (3)
A0 = VIL
(4)
(4)
Manufacturer Code
Hardware
V
IL
V
IL
V
IH
V
V
IH
IH
A1 - A17 = VIL, A9 = VH, (3)
A0 = VIH
(4)
Device Code
A0 = VIL, A1 - A17 = VIL
A0 = VIH, A1 - A17 = VIL
Manufacturer Code
(5)
Software
(4)
Device Code
Notes: 1. X can be VIL or VIH.
4. Manufacturer Code: 1FH, Device Code: 92H
5. See details under Software Product Identification Entry/Exit.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
DC Characteristics
Symbol
Parameter
Condition
Min
Max
10
Units
µA
µA
µA
mA
mA
V
I
LI
Input Load Current
Output Leakage Current
V
V
= 0V to V
CC
IN
I
I
I
I
= 0V to V
CC
10
LO
I/O
V
V
V
Standby Current CMOS
Standby Current TTL
Active Current
CE = V - 0.3V to V
CC
300
3
SB1
SB2
CC
CC
CC
CC
CE = 2.0V to V
CC
(1)
f = 5 MHz; I
= 0 mA
50
CC
OUT
V
V
V
V
V
Input Low Voltage
0.8
IL
Input High Voltage
2.0
V
IH
Output Low Voltage
Output High Voltage
Output High Voltage CMOS
I
I
I
= 2.1 mA
.45
V
OL
OH1
OH2
OL
OH
OH
= -400 µA
= -100 µA; V = 4.5V
2.4
4.2
V
V
CC
Note: 1. In the erase mode, ICC is 90 mA.
4-223
AC Read Characteristics
AT49F4096-90
AT49F4096-12
Min
Max
Min
Max
Symbol Parameter
Units
ns
t
t
t
t
Address to Output Delay
CE to Output Delay
90
90
40
25
120
120
50
ACC
(1)
ns
CE
OE
DF
(2)
OE to Output Delay
0
0
0
0
ns
(3, 4)
CE or OE to Output Float
30
ns
Output Hold from OE, CE or
Address, whichever occurred first
t
0
0
ns
OH
AC Read Waveforms (1, 2, 3, 4)
Notes: 1. CE may be delayed up to tACC - tCE after the address
transition without impact on tACC
3. tDF is specified from OE or CE whichever occurs first
(CL = 5 pF).
.
2. OE may be delayed up to tCE - tOE after the falling
edge of CE without impact on tCE or by tACC - tOE
4. This parameter is characterized and is not 100% tested.
after an address change without impact on tACC
.
Output Test Load
Input Test Waveforms and Measurement Level
t , t < 5 ns
R
F
Pin Capacitance (f = 1 MHz, T = 25°C) (1)
Typ
Max
6
Units
pF
Conditions
C
C
4
8
V
V
= 0V
IN
IN
12
pF
= 0V
OUT
OUT
Note: 1. This parameter is characterized and is not 100% tested.
4-224
AT49F4096
AT49F4096
AC Word Load Characteristics
Symbol
Parameter
Min
10
50
0
Max
Units
t
t
t
t
t
t
t
t
, t
Address, OE Set-up Time
Address Hold Time
ns
ns
ns
ns
ns
ns
ns
ns
AS OES
AH
CS
CH
WP
DS
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
0
90
50
10
90
, t
Data, OE Hold Time
Write Pulse Width High
DH OEH
WPH
AC Word Load Waveforms
WE Controlled
CE Controlled
4-225
Program Cycle Characteristics
Symbol
Parameter
Min
Max
Units
µs
t
t
t
t
t
t
t
t
Word Programming Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
50
BP
10
50
50
10
90
90
ns
AS
ns
AH
ns
DS
DH
WP
WPH
EC
ns
Write Pulse Width
Write Pulse Width High
Erase Cycle Time
ns
ns
10
seconds
Program Cycle Waveforms
Sector or Chip Erase Cycle Waveforms
Note: 1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 5555. For sector
erase, the address depends on what sector is to be
erased. (See note 4 under command definitions.)
3. For chip erase, the data should be 10H, and for sector erase,
the data should be 30H.
4-226
AT49F4096
AT49F4096
Data Polling Characteristics (1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
t
t
t
t
Data Hold Time
OE Hold Time
OE to Output Delay
DH
10
ns
OEH
OE
(2)
ns
Write Recovery Time
0
ns
WR
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
Toggle Bit Characteristics (1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
t
t
t
t
t
Data Hold Time
OE Hold Time
OE to Output Delay
OE High Pulse
DH
10
ns
OEH
OE
(2)
ns
150
0
ns
OEHP
WR
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms (1, 2, 3)
Notes: 1. Toggling either OE or CE or both OE and CE will
operate toggle bit. The tOEHP specification must be
met by the toggling input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address
should not vary.
4-227
Software Product
Boot Block Lockout
Enable Algorithm(1)
Identification Entry (1)
LOAD DATA AA
TO
LOAD DATA AA
TO
ADDRESS 5555
ADDRESS 5555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS 2AAA
ADDRESS 2AAA
LOAD DATA 90
TO
LOAD DATA 80
TO
ADDRESS 5555
ADDRESS 5555
ENTER PRODUCT
IDENTIFICATION
MODE (2, 3, 5)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
Software Product
Identification Exit (1, 6)
LOAD DATA 40
TO
ADDRESS 5555
OR
LOAD DATA AA
LOAD DATA F0
TO
ANY ADDRESS
TO
PAUSE 1 second
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
EXIT PRODUCT
IDENTIFICATION
MODE (4)
Notes for boot block lockout feature enable:
1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0
(Hex) Address Format: A14 - A0 (Hex).
LOAD DATA F0
TO
ADDRESS 5555
2. Boot block lockout feature enabled.
EXIT PRODUCT
IDENTIFICATION
MODE (4)
Notes for software product identification:
1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)
Address Format: A14 - A0 (Hex).
2. A1 - A17 = VIL.
Manufacture Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 1FH
Device Code: 92H
6. Either one of the Product ID Exit commands can be used.
4-228
AT49F4096
AT49F4096
Ordering Information (1)
t
I
(mA)
ACC
CC
Ordering Code
Package
Operation Range
(ns)
Active
Standby
90
50
0.3
0.3
0.3
0.3
AT49F4096-90TC
AT49F4096-90RC
48T
44R
Commercial
(0° to 70°C)
50
50
50
AT49F4096-90TI
AT49F4096-90RI
48T
44R
Industrial
(-40° to 85°C)
120
AT49F4096-12TC
AT49F4096-12RC
48T
44R
Commercial
(0° to 70°C)
AT49F4096-12TI
AT49F4096-12RI
48T
44R
Industrial
(-40° to 85°C)
Note: 1. The AT49F4096 has as optional boot block feature. The part number shown in the Ordering Information table is for
devices with the boot block in the lower address range (i.e., 00000H to 01FFFH). Users requiring the boot block to be
in the higher address range should contact Atmel.
Package Type
48T
44R
48 Lead, Thin Small Outline Package (TSOP)
44 Lead, 0.525" Wide, Plastic Gull Wing Small Outline Package (SOIC)
4-229
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